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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. h8/3006, h8/3007 hardware manual 16 users manual rev.5.00 2007.09 renesas 16-bit single-chip microcomputer h8 family/h8/300h series h8/3006 hd6413006 h8/3007 hd6413007 rev.5.00 sep. 12, 2007 page ii of xxviii rej09b0396-0500 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials rev.5.00 sep. 12, 2007 page iii of xxviii rej09b0396-0500 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products. rev.5.00 sep. 12, 2007 page iv of xxviii rej09b0396-0500 rev.5.00 sep. 12, 2007 page v of xxviii rej09b0396-0500 preface the h8/3006 and h8/3007 are a series of high-performance microcontrollers that integrate system supporting functions together with an h8/300h cpu core. the h8/300h cpu has a 32-bit inte rnal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. it can address a 16-mbyte linear address space. the on-chip supporting functions include ram, 16-bit timers, 8-bit timers, a programmable timing pattern controller (tpc), a watchdog timer (wdt), a serial communication interface (sci), an a/d converter, a d/a converter, i/o ports, and a dma controller (dmac). the address space is divided into eight areas. th e data bus width and acce ss cycle length can be selected independently in each area, simplifying th e connection of different types of memory. four mcu operating modes (modes 1 to 4) are provided, offering a choice of data bus width initial value and address space. with these features, the h8/3 006 and h8/3007 offer easy implementation of compact, high- performance systems. this manual describes the h8/3006 and h8/3007 group hardware. for details of the instruction set, refer to the h8/300h series software manual. rev.5.00 sep. 12, 2007 page vi of xxviii rej09b0396-0500 rev.5.00 sep. 12, 2007 page vii of xxviii rej09b0396-0500 main revisions for this edition item page revision (see manual for details) all ? company name and brand names amended (before) hitachi, ltd. (after) renesas technology corp. 5.4.2 interrupt sequence figure 5.7 interrupt sequence 102 figure amended d 15 to d 0 8.7.2 register configuration table 8.14 port a pin functions (modes 1 to 4) pa 3 /tp 3 /tiocb 0 /tclkd 274 description and note amended bit pwm0 in tmdr, bits iob2 to iob0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr2 of the 8-bit timer, bit nder3 in ndera, and bit pa 3 ddr select the pin function as follows. notes: 2. tclkd input when tpsc2 = tpsc1 = tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr2 are as shown in (3) in the table below. pa 2 /tp 2 /tioca 0 /tclkc 275 table amended pin pin functions and selection method pa 2 /tp 2 / tioca 0 / tclkc bit pwm0 in tmdr, bits ioa2 to ioa0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr0 of the 8-bit timer, bit nder2 in ndera, and bit pa 2 ddr select the pin function as follows. 16-bit timer channel 0 settin g s (1) in table below (2) in table below pa 2 ddr 0 1 1 nder2 0 1 pin function tioca 0 output pa 2 input pa 2 output tp 2 output tioca 0 input * 1 tclkc input * 2 notes: 1. tioca0 input when ioa2 = 1. 2. tclkc input when tpsc2 = tpsc1 = 1 and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr0 are as shown in (3) in the table below. 16-bit timer channel 0 settin g s (2) (1) (2) (1) pwm0 0 1 ioa2 0 1 ioa1 0 0 1 ioa0 0 1 8-bit timer channel 0 settin g s (4) (3) cks2 0 1 cks1 0 1 cks0 0 1 ? ? ? ? ? ? ? ? ? ?? ? rev.5.00 sep. 12, 2007 page viii of xxviii rej09b0396-0500 item page revision (see manual for details) 8.7.2 register configuration table 8.14 port a pin functions (modes 1 to 4) pa 1 /tp 1 /tclkb/ tend 1 276 table amended pin pin functions and selection method pa 1 /tp 1 / tclkb/ tend 1 bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr3 of the 8-bit timer, bit nder1 in ndera, and bit pa 1 ddr select the pin function as follows. pa 1 ddr 0 1 1 nder1 0 1 pin function pa 1 input pa 1 output tp 1 output tclkb input * 1 tend 1 output * 2 notes: 1. tclkb input when mdf = 1 in tmdr, or tpsc2 = 1, tpsc1 = 0, and tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr3 are as shown in (1) in the table below. 2. when an external request is specified as a dmac activation source, tend 1 output re g ardless of bits pa 1 ddr and nder1. 8-bit timer channel 3 settin g s (2) (1) cks2 0 1 cks1 0 1 cks0 0 1 ? ? ? ? pa 0 /tp 0 /tclka/ tend 0 277 table amended pin pin functions and selection method pa 0 /tp 0 / tclka/ tend 0 bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr1 of the 8-bit timer, bit nder0 in ndera, and bit pa 0 ddr select the pin function as follows. pa 0 ddr 1 0 nder0 0 1 pin function pa 0 input pa 0 output tp 0 output tclka input * 1 tend 0 output * 2 notes: 1. tclka input when mdf = 1 in tmdr, or tpsc2 = 1, tpsc1 = 0 and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr0 are as shown in (1) in the table below. 2. when an external request is specified as a dmac activation source, tend 0 output re g ardless of bits pa 0 ddr and nder0. 8-bit timer channel 1 settin g s (2) (1) cks2 0 1 cks1 0 1 cks0 0 1 ? ? ?? rev.5.00 sep. 12, 2007 page ix of xxviii rej09b0396-0500 item page revision (see manual for details) 8.8.2 register configuration port b data register (pbdr): table 8.16 port b pin functions pb 3 /tp 11 /tmio 3 / dreq 1 / cs 4 281 description amended the dram interface settings by bits dras2 to dras0 in drcra, bits ois3/2 and os1/0 in 8tcsr3, bits cclr1 and cclr0 in 8tcr3, bit cs4e in cscr, bit nder11 in nderb, and bit pb 3 ddr select the pin function as follows. pb 2 /tp 10 /tmo 2 / cs 5 282 table amended pin pin functions and selection method pb 2 /tp 10 / tmo 2 / cs 5 the dram interface settin g s by bits dras2 to dras0 in drcra, bits ois3/2 and os1/0 in 8tcsr2, bit cs5e in cscr, bit nder10 in nderb, and bit pb 2 ddr select the pin function as follows. dram interface settin g s (1) in table below (2) in table below ois3/2 and os1/0 all 0 not all 0 cs5e 0 1 pb 2 ddr 1 0 1 nder10 0 1 pin function pb 2 input pb 2 output tp 10 output cs 5 output tmo 2 output cs 5 output * ???? ??? ?? ? pb 1 /tp 9 /tmio 1 / dre q 0 / cs 6 description amended bits ois3/2 and os1/0 in 8tcsr1, bits cclr1 and cclr0 in 8tcr0, bit cs6e in cscr, bit nder9 in nderb, and bit pb 1 ddr select the pin function as follows. pb 0 /tp 8 /tmo 0 / cs 7 283 description amended bits ois3/2 and os1/0 in 8tcsr0, bit cs7e in cscr, bit nder8 in nderb, and bit pb 0 ddr select the pin function as follows. 9.1.4 register configuration table 9.3 16-bit timer registers 291 table amended channel address * 1 name abbre- viation r/w initial value common h'fff64 timer interrupt status re g ister a tisra r/(w) * 2 h'88 rev.5.00 sep. 12, 2007 page x of xxviii rej09b0396-0500 item page revision (see manual for details) 9.4.6 setting initial value of 16-bit timer output figure 9.32 example of timing for setting initial value of 16-bit timer output by writing to tolr 333 figure amended t 1 tolr address n n t 2 t 3 address bus tolr 16-bit timer output pin 10.2.3 time constant registers b (tcorb) 357 note added note: * when channel 1 and channel 3 are designated for tcorb input capture, the cmfb flag is not set by a channel 0 or channel 2 compare match b. 10.2.4 timer control register (8tcr) bits 4 and 3 ? counter clear 1 and 0 (cclr1, cclr0): 359 note added note: when input capture b is set as the 8tcnt1 and 8tcnt3 counter clear source, 8tcnt0 and 8tcnt2 are not cleared by compare match b. bits 2 to 0 ? clock select 2 to 0 (csk2 to csk0): description replaced 10.2.5 timer control/status registers (8tcsr) bit 7 ? compare match/input capture flag b (cmfb): 362 note added note: * when bit ice is set to 1 in 8tcsr1 and 8tcsr3, the cmfb flag is not set when 8tcnt0 = tcorb0 or 8tcnt2 = tcorb2. bit 6 ? compare match flag a (cmfa): description amended status flag that indicates the occurrence of a tcora compare match . bit 4 ? reserved (in 8tcsr1): bit 4 ? input capture enable (ice) (in 8tcsr1 and 8tcsr3): 363 description replaced rev.5.00 sep. 12, 2007 page xi of xxviii rej09b0396-0500 item page revision (see manual for details) 10.4.5 operation with cascaded connection 373 description amended in this case, the timer operates as below. similarly, if bits cks2 to cks0 are set to (100) in either 8tcr2 or 8tcr3, the 8-bit timers of channels 2 and 3 are cascaded. 375 description amended ? the ovf flag is set to 1 in 8tcsr3 when the 8-bit counter (8tcnt3) overflows (from h'ff to h'00). 10.4.6 input capture setting 376 note added note: when tcorb1 in channel 1 is used for input capture, tcorb0 in channel 0 cannot be used as a compare match register. similarly, when tcorb3 in channel 3 is used for input capture, tcorb2 in channel 2 cannot be used as a compare match register. 11.3.3 normal tpc output figure 11.4 setup procedure for normal tpc output (example) 406 description amended 4. enable the imfa interrupt in tisra. the dmac can also be set up to transfer data to the next data register. figure 11.5 normal tpc output example (five-phase pulse output) 407 description amended ? the 16-bit timer channel to be used as the output trigger channel is set up so that gra is an output compare register and the counter will be cleared by compare match a. the trigger period is set in gra. the imiea bit is set to 1 in tisra to enable the compare match a interrupt. 13.1 overview 425 description amended the h8/3006 and h8/3007 have a serial communication interface (sci) with three independent channels. all three channels have identical functions. the sci can communicate in both asynchronous and synchronous mode. it also has a multiprocessor communication function for serial communication among two or more processors. 13.2.3 transmit shift register (tsr) 431 description amended if the tdre flag is set to 1 in ssr, however, the sci does not load the tdr contents into tsr. the cpu cannot read or write tsr directly. 13.3.4 synchronous operation 478 description amended ? the sci synchronizes with the serial clock input or output and performs receive operation. rev.5.00 sep. 12, 2007 page xii of xxviii rej09b0396-0500 item page revision (see manual for details) 14.3.4 register settings smart card mode register (scmr) settings: 499 description amended with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. in the example above, the first character data is h'3b. the parity bit is 1, following the even parity rule designated for smart cards. 14.4 usage notes note on block transfer mode support: 511 description added the smart card interface installed in the h8/3006 and h8/3007 support an ic card (smart card) interface with provision for iso/iec7816-3 t=0 (character tr ansmission). therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data retransmission are not performed). 15.1 overview 513 description amended when the a/d converter is not used, it can be halted independently to conserve power. for details see section 19.6, module standby function. the h8/3006 and h8/3007 support 70/134-state conversion as a high-speed conversion mode. note that it differs in this respect from the h8/3048 group, which supports 134/266-state conversion. 15.2.1 a/d data registers a to d (addra to addrd) 517 description amended the cpu can always read the a/d data registers. 536 table amended pin name abbreviation i/o fun c tion 16.1.3 pin configuration table 16.1 d/a converter pins analog power supply pin av cc input analog power supply and reference voltage table amended item symbol 20.2.2 ac characteristics table 20.7 control signal timing 581 nmi, irq pulse width (in recovery from software standby mode) t nmiw 20.3.6 timer input/output timing 603 description amended the timings of 16-bit and 8-bit timer are shown as follows: a.3 number of states required for execution table a.4 number of cycles per instruction 633 notes amended notes: 1. not available in the h8/3006 and h8/3007. 2. n is the value set in register r4l or r4. the source and destination are accessed n + 1 times each. rev.5.00 sep. 12, 2007 page xiii of xxviii rej09b0396-0500 item page revision (see manual for details) c.3 port 7 block diagrams figure c.3 (b) port 7 block diagram (pins p7 6 and p7 7 ) 724 figure amended p7 n c.7 port b block diagrams figure c.7 (e) port b block diagram (pin pb 6 ) 742 figure amended pb 6 figure c.7 (f) port b block diagram (pin pb 7 ) 743 figure amended rpb rev.5.00 sep. 12, 2007 page xiv of xxviii rej09b0396-0500 item page revision (see manual for details) appendix h comparison of h8/300h series product specifications h.1 differences between h8/3067 and h8/3062 group, h8/3048 group, h8/3006 and h8/3007, and h8/3002 759 table amended item h8/3067, h8/3062 group h8/3048 group h8/3006, h8/3007 h8/3002 9 a/d converter conversion start tri gg er input external tri gg er/8-bit timer compare match external tri gg er external tri gg er/8-bit timer compare match external tri gg er conversion states 70/134 134/266 70/134 134/266 all trademarks and registered trademarks are the property of their respective owners. rev.5.00 sep. 12, 2007 page xv of xxviii rej09b0396-0500 contents section 1 overview ............................................................................................................. 1 1.1 overview....................................................................................................................... .... 1 1.2 internal block diagram..................................................................................................... 6 1.3 pin description................................................................................................................ .. 7 1.3.1 pin arrangement .................................................................................................. 7 1.3.2 pin functions ....................................................................................................... 9 1.3.3 pin assignments in each mode ........................................................................... 14 section 2 cpu ...................................................................................................................... 19 2.1 overview....................................................................................................................... .... 19 2.1.1 features................................................................................................................ 19 2.1.2 differences from h8/300 cpu............................................................................. 20 2.2 cpu operating modes ...................................................................................................... 21 2.3 address space .................................................................................................................. . 22 2.4 register configuration...................................................................................................... 23 2.4.1 overview.............................................................................................................. 23 2.4.2 general registers ................................................................................................. 24 2.4.3 control registers ................................................................................................. 25 2.4.4 initial cpu register values ................................................................................. 26 2.5 data formats ................................................................................................................... .. 27 2.5.1 general register data formats ............................................................................ 27 2.5.2 memory data formats ......................................................................................... 28 2.6 instruction set ................................................................................................................ ... 30 2.6.1 instruction set overview ..................................................................................... 30 2.6.2 instructions and a ddressing m odes ..................................................................... 31 2.6.3 tables of instructions classified by function...................................................... 32 2.6.4 basic instruction formats .................................................................................... 41 2.6.5 notes on use of bit manipulation instructions.................................................... 42 2.7 addressing modes and effective address calculation ..................................................... 44 2.7.1 addressing modes ............................................................................................... 44 2.7.2 effective address calculation.............................................................................. 46 2.8 processing states.............................................................................................................. . 50 2.8.1 overview.............................................................................................................. 50 2.8.2 program execution state...................................................................................... 51 2.8.3 exception-handling state .................................................................................... 51 2.8.4 exception-handling sequences ........................................................................... 53 2.8.5 bus-released state............................................................................................... 54 rev.5.00 sep. 12, 2007 page xvi of xxviii rej09b0396-0500 2.8.6 reset state ........................................................................................................... 54 2.8.7 power-down state ............................................................................................... 54 2.9 basic operational timing ................................................................................................. 55 2.9.1 overview.............................................................................................................. 55 2.9.2 on-chip memory access timing........................................................................ 55 2.9.3 on-chip supporting modul e access timing ...................................................... 56 2.9.4 access to external address space ....................................................................... 57 section 3 mcu operating modes .................................................................................. 59 3.1 overview....................................................................................................................... .... 59 3.1.1 operating mode selection ................................................................................... 59 3.1.2 register configuration......................................................................................... 60 3.2 mode control register (mdcr) ...................................................................................... 60 3.3 system control register (syscr) ................................................................................... 61 3.4 operating mode descriptions ........................................................................................... 63 3.4.1 mode 1 ................................................................................................................. 63 3.4.2 mode 2 ................................................................................................................. 63 3.4.3 mode 3 ................................................................................................................. 64 3.4.4 mode 4 ................................................................................................................. 64 3.5 pin functions in each operating mode ............................................................................ 64 3.6 memory map in each operating mode ............................................................................ 65 3.6.1 note on reserved areas....................................................................................... 65 section 4 exception handling ......................................................................................... 69 4.1 overview....................................................................................................................... .... 69 4.1.1 exception handling types and priority............................................................... 69 4.1.2 exception handling operation............................................................................. 69 4.1.3 exception vector table ....................................................................................... 70 4.2 reset.......................................................................................................................... ........ 72 4.2.1 overview.............................................................................................................. 72 4.2.2 reset sequence .................................................................................................... 72 4.2.3 interrupts after reset............................................................................................ 74 4.3 interrupts..................................................................................................................... ...... 75 4.4 trap instruction............................................................................................................... .. 76 4.5 stack status after exception handling.............................................................................. 76 4.6 notes on stack usage ....................................................................................................... 77 section 5 interrupt controller .......................................................................................... 79 5.1 overview....................................................................................................................... .... 79 5.1.1 features................................................................................................................ 79 rev.5.00 sep. 12, 2007 page xvii of xxviii rej09b0396-0500 5.1.2 block diagram ..................................................................................................... 80 5.1.3 pin configuration................................................................................................. 81 5.1.4 register configuration......................................................................................... 81 5.2 register descriptions ........................................................................................................ 8 2 5.2.1 system control register (syscr) ...................................................................... 82 5.2.2 interrupt priority registers a and b (ipra, iprb)............................................. 83 5.2.3 irq status register (isr).................................................................................... 89 5.2.4 irq enable register (ier) .................................................................................. 90 5.2.5 irq sense control register (iscr) .................................................................... 91 5.3 interrupt sources .............................................................................................................. . 92 5.3.1 external interrupts ............................................................................................... 92 5.3.2 internal interrupts................................................................................................. 93 5.3.3 interrupt vector table.......................................................................................... 93 5.4 interrupt operation............................................................................................................ 97 5.4.1 interrupt handling process................................................................................... 97 5.4.2 interrupt sequence ............................................................................................... 102 5.4.3 interrupt res ponse time...................................................................................... 103 5.5 usage notes .................................................................................................................... .. 104 5.5.1 contention between interrupt and in terrupt-disabling instruction ...................... 104 5.5.2 instructions that inhibit interrupts........................................................................ 105 5.5.3 interrupts during eepmov instruction execution .............................................. 105 section 6 bus controller .................................................................................................... 107 6.1 overview....................................................................................................................... .... 107 6.1.1 features................................................................................................................ 107 6.1.2 block diagram ..................................................................................................... 108 6.1.3 pin configuration................................................................................................. 110 6.1.4 register configuration......................................................................................... 111 6.2 register descriptions ........................................................................................................ 1 12 6.2.1 bus width control register (abwcr)............................................................... 112 6.2.2 access state control register (astcr) ............................................................. 113 6.2.3 wait control registers h and l (wcrh, wcrl).............................................. 113 6.2.4 bus release control register (brcr) ................................................................ 117 6.2.5 bus control register (bcr) ................................................................................ 119 6.2.6 chip select control register (cscr).................................................................. 121 6.2.7 dram control register a (drcra) ................................................................. 122 6.2.8 dram control register b (drcrb) ................................................................. 124 6.2.9 refresh timer control/status register (rtmcsr) ............................................ 127 6.2.10 refresh timer count er (rtcnt)........................................................................ 128 6.2.11 refresh time constant register (rtcor) ......................................................... 129 rev.5.00 sep. 12, 2007 page xviii of xxviii rej09b0396-0500 6.3 operation ...................................................................................................................... .... 130 6.3.1 area division....................................................................................................... 130 6.3.2 bus specifications................................................................................................ 132 6.3.3 memory interfaces............................................................................................... 133 6.3.4 chip select signals .............................................................................................. 133 6.4 basic bus interface ........................................................................................................... 134 6.4.1 overview.............................................................................................................. 134 6.4.2 data size and data alignment............................................................................. 134 6.4.3 valid strobes........................................................................................................ 136 6.4.4 memory areas ..................................................................................................... 136 6.4.5 basic bus control signal timing ........................................................................ 138 6.4.6 wait control ........................................................................................................ 145 6.5 dram interface ............................................................................................................... 1 47 6.5.1 overview.............................................................................................................. 147 6.5.2 dram space and ras output pin settings ....................................................... 147 6.5.3 address multiplexing........................................................................................... 148 6.5.4 data bus............................................................................................................... 148 6.5.5 pins used for dram interface............................................................................ 149 6.5.6 basic timing........................................................................................................ 149 6.5.7 precharge state control ....................................................................................... 151 6.5.8 wait control ........................................................................................................ 152 6.5.9 byte access control and cas output pin........................................................... 153 6.5.10 burst operation.................................................................................................... 154 6.5.11 refresh control.................................................................................................... 160 6.5.12 examples of use .................................................................................................. 164 6.5.13 usage notes ......................................................................................................... 168 6.6 interval timer ................................................................................................................. .. 170 6.6.1 operation ............................................................................................................. 170 6.7 interrupt sources.............................................................................................................. . 175 6.8 burst rom interface......................................................................................................... 17 6 6.8.1 overview.............................................................................................................. 176 6.8.2 basic timing........................................................................................................ 176 6.8.3 wait control ........................................................................................................ 177 6.9 idle cycle..................................................................................................................... ..... 178 6.9.1 operation ............................................................................................................. 178 6.9.2 pin states in idle cycle ........................................................................................ 181 6.10 bus arbiter.................................................................................................................... .... 182 6.10.1 operation ............................................................................................................. 182 6.11 register and pin input timi ng .......................................................................................... 185 6.11.1 register write timing ......................................................................................... 185 rev.5.00 sep. 12, 2007 page xix of xxviii rej09b0396-0500 6.11.2 breq pin input timing ...................................................................................... 186 section 7 dma controller ................................................................................................ 187 7.1 overview....................................................................................................................... .... 187 7.1.1 features................................................................................................................ 187 7.1.2 block diagram ..................................................................................................... 188 7.1.3 functional overview............................................................................................ 188 7.1.4 pin configuration................................................................................................. 190 7.1.5 register configuration......................................................................................... 190 7.2 register descriptions (1) (short address mode) .............................................................. 191 7.2.1 memory address registers (mar) ..................................................................... 192 7.2.2 i/o address registers (ioar) ............................................................................. 192 7.2.3 execute transfer count registers (etcr).......................................................... 193 7.2.4 data transfer control registers (dtcr) ............................................................ 195 7.3 register descriptions (2) (full address mode) ................................................................ 198 7.3.1 memory address registers (mar) ..................................................................... 198 7.3.2 i/o address registers (ioar) ............................................................................. 198 7.3.3 execute transfer count registers (etcr).......................................................... 199 7.3.4 data transfer control registers (dtcr) ............................................................ 201 7.4 operation...................................................................................................................... ..... 207 7.4.1 overview.............................................................................................................. 207 7.4.2 i/o mode.............................................................................................................. 209 7.4.3 idle mode............................................................................................................. 211 7.4.4 repeat mode ........................................................................................................ 214 7.4.5 normal mode....................................................................................................... 218 7.4.6 block transfer mode ........................................................................................... 221 7.4.7 dmac activation................................................................................................ 226 7.4.8 dmac bus cycle ................................................................................................ 227 7.4.9 multiple-channel operation ................................................................................ 233 7.4.10 external bus requests, dram interface, and dmac........................................ 234 7.4.11 nmi interrupts and dmac.................................................................................. 235 7.4.12 aborting a dmac transfer................................................................................. 236 7.4.13 exiting full address mode .................................................................................. 237 7.4.14 dmac states in reset state, standby modes, and sleep mode.......................... 238 7.5 interrupts ..................................................................................................................... ...... 238 7.6 usage notes .................................................................................................................... .. 239 7.6.1 note on word data transfer................................................................................ 239 7.6.2 dmac self-access ............................................................................................. 239 7.6.3 longword access to memory address registers ................................................ 240 7.6.4 note on full address mode setup ....................................................................... 240 rev.5.00 sep. 12, 2007 page xx of xxviii rej09b0396-0500 7.6.5 note on activating dmac by internal interrupts ............................................... 241 7.6.6 nmi interrupts and block transfer mode ........................................................... 242 7.6.7 memory and i/o address register values .......................................................... 242 7.6.8 bus cycle when transfer is aborted................................................................... 243 7.6.9 transfer requests by a/d converter................................................................... 243 section 8 i/o ports .............................................................................................................. 245 8.1 overview....................................................................................................................... .... 245 8.2 port 4......................................................................................................................... ........ 248 8.2.1 overview.............................................................................................................. 248 8.2.2 register configuration......................................................................................... 249 8.3 port 6......................................................................................................................... ........ 251 8.3.1 overview.............................................................................................................. 251 8.3.2 register configuration......................................................................................... 252 8.4 port 7......................................................................................................................... ........ 255 8.4.1 overview.............................................................................................................. 255 8.4.2 register configuration......................................................................................... 255 8.5 port 8......................................................................................................................... ........ 256 8.5.1 overview.............................................................................................................. 256 8.5.2 register configuration......................................................................................... 257 8.6 port 9......................................................................................................................... ........ 261 8.6.1 overview.............................................................................................................. 261 8.6.2 register configuration......................................................................................... 262 8.7 port a......................................................................................................................... ....... 265 8.7.1 overview.............................................................................................................. 265 8.7.2 register configuration......................................................................................... 267 8.8 port b ......................................................................................................................... ....... 277 8.8.1 overview.............................................................................................................. 277 8.8.2 register configuration......................................................................................... 278 section 9 16-bit timer ....................................................................................................... 285 9.1 overview....................................................................................................................... .... 285 9.1.1 features................................................................................................................ 285 9.1.2 block diagrams ................................................................................................... 287 9.1.3 pin configuration................................................................................................. 290 9.1.4 register configuration......................................................................................... 291 9.2 register descriptions ........................................................................................................ 2 92 9.2.1 timer start register (tstr) ............................................................................... 292 9.2.2 timer synchro register (tsnc) ......................................................................... 293 9.2.3 timer mode register (tmdr) ............................................................................ 295 rev.5.00 sep. 12, 2007 page xxi of xxviii rej09b0396-0500 9.2.4 timer interrupt status re gister a (tisra)......................................................... 297 9.2.5 timer interrupt status register b (tisrb) ......................................................... 300 9.2.6 timer interrupt status re gister c (tisrc) ......................................................... 303 9.2.7 timer counters (16tcnt) .................................................................................. 305 9.2.8 general registers (gra, grb)........................................................................... 306 9.2.9 timer control registers (16tcr) ....................................................................... 307 9.2.10 timer i/o control register (tior) ..................................................................... 310 9.2.11 timer output level setting register c (tolr) ................................................. 312 9.3 cpu interface.................................................................................................................. .. 314 9.3.1 16-bit accessible registers ................................................................................. 314 9.3.2 8-bit accessible registers ................................................................................... 316 9.4 operation...................................................................................................................... ..... 317 9.4.1 overview.............................................................................................................. 317 9.4.2 basic functions.................................................................................................... 317 9.4.3 synchronization ................................................................................................... 325 9.4.4 pwm mode.......................................................................................................... 327 9.4.5 phase counting mode .......................................................................................... 331 9.4.6 setting initial value of 16-bit timer output ....................................................... 333 9.5 interrupts ..................................................................................................................... ...... 334 9.5.1 setting of status flags.......................................................................................... 334 9.5.2 timing of clearing of status flags ...................................................................... 336 9.5.3 interrupt sources and dma controller activation.............................................. 336 9.6 usage notes .................................................................................................................... .. 338 section 10 8-bit timers ..................................................................................................... 351 10.1 overview....................................................................................................................... .... 351 10.1.1 features................................................................................................................ 351 10.1.2 block diagram ..................................................................................................... 352 10.1.3 pin configuration................................................................................................. 353 10.1.4 register configuration......................................................................................... 354 10.2 register descriptions ........................................................................................................ 3 55 10.2.1 timer counters (8tcnt) .................................................................................... 355 10.2.2 time constant registers a (tcora) ................................................................. 356 10.2.3 time constant registers b (tcorb).................................................................. 357 10.2.4 timer control register (8tcr) ........................................................................... 358 10.2.5 timer control/status registers (8tcsr) ............................................................ 361 10.3 cpu interface.................................................................................................................. .. 366 10.3.1 8-bit registers ..................................................................................................... 366 10.4 operation...................................................................................................................... ..... 368 10.4.1 8tcnt count timing.......................................................................................... 368 rev.5.00 sep. 12, 2007 page xxii of xxviii rej09b0396-0500 10.4.2 compare match timing....................................................................................... 369 10.4.3 input capture si gnal timi ng ............................................................................... 371 10.4.4 timing of status flag setting .............................................................................. 372 10.4.5 operation with cascaded connection.................................................................. 373 10.4.6 input capture setting ........................................................................................... 375 10.5 interrupt ...................................................................................................................... ...... 376 10.5.1 interrupt source ................................................................................................... 376 10.5.2 a/d converter activation.................................................................................... 377 10.6 8-bit timer applica tion example..................................................................................... 377 10.7 usage notes .................................................................................................................... .. 378 10.7.1 contention between 8tcnt write and clear...................................................... 378 10.7.2 contention between 8tcnt write and increment .............................................. 379 10.7.3 contention between tcor write and compare match ...................................... 380 10.7.4 contention between tcor read and input capture ........................................... 381 10.7.5 contention between counter clearing by input capture and counter increment ............................................................................................... 382 10.7.6 contention between tcor write and input capture .......................................... 383 10.7.7 contention between 8tcnt byte write and increment in 16-bit count mode (cascaded connection) ........................................................................................ 384 10.7.8 contention between compare matches a and b ................................................. 385 10.7.9 8tcnt operation at internal clock source switchover ..................................... 385 section 11 programmable t iming pattern controller (tpc) ................................. 389 11.1 overview....................................................................................................................... .... 389 11.1.1 features................................................................................................................ 389 11.1.2 block diagram..................................................................................................... 390 11.1.3 pin configuration................................................................................................. 391 11.1.4 register configuration......................................................................................... 392 11.2 register descriptions ........................................................................................................ 3 93 11.2.1 port a data direction register (paddr) ........................................................... 393 11.2.2 port a data register (padr).............................................................................. 393 11.2.3 port b data direction register (pbddr) ........................................................... 394 11.2.4 port b data register (pbdr) .............................................................................. 394 11.2.5 next data register a (ndra) ............................................................................ 395 11.2.6 next data register b (ndrb)............................................................................. 396 11.2.7 next data enable register a (ndera).............................................................. 398 11.2.8 next data enable register b (nderb) .............................................................. 399 11.2.9 tpc output control re gister (tpcr) ................................................................. 400 11.2.10 tpc output mode register (tpmr) ................................................................... 402 11.3 operation ...................................................................................................................... .... 404 rev.5.00 sep. 12, 2007 page xxiii of xxviii rej09b0396-0500 11.3.1 overview.............................................................................................................. 404 11.3.2 output timing...................................................................................................... 405 11.3.3 normal tpc output............................................................................................. 406 11.3.4 non-overlapping tpc output ............................................................................. 408 11.3.5 tpc output triggering by input capture ............................................................ 410 11.4 usage notes .................................................................................................................... .. 410 11.4.1 operation of tpc output pins ............................................................................. 410 11.4.2 note on non-overla pping out put........................................................................ 411 section 12 watchdog timer ............................................................................................. 413 12.1 overview....................................................................................................................... .... 413 12.1.1 features................................................................................................................ 413 12.1.2 block diagram ..................................................................................................... 414 12.1.3 pin configuration................................................................................................. 414 12.1.4 register configuration......................................................................................... 415 12.2 register descriptions ........................................................................................................ 4 15 12.2.1 timer counter (tcnt)........................................................................................ 415 12.2.2 timer control/status register (tcsr) ................................................................ 416 12.2.3 reset control/status register (rstcsr) ............................................................ 418 12.2.4 notes on register access..................................................................................... 419 12.3 operation...................................................................................................................... ..... 420 12.3.1 watchdog timer op eration ................................................................................. 420 12.3.2 interval timer operation ..................................................................................... 422 12.3.3 timing of setting of over flow flag (ovf) ......................................................... 422 12.3.4 timing of setting of watchdog timer reset bit (wrst) .................................. 423 12.4 interrupts ..................................................................................................................... ...... 423 12.5 usage notes .................................................................................................................... .. 424 section 13 serial communication interface ................................................................ 425 13.1 overview....................................................................................................................... .... 425 13.1.1 features................................................................................................................ 425 13.1.2 block diagram ..................................................................................................... 427 13.1.3 pin configuration................................................................................................. 428 13.1.4 register configuration......................................................................................... 429 13.2 register descriptions ........................................................................................................ 4 30 13.2.1 receive shift register (rsr) .............................................................................. 430 13.2.2 receive data register (rdr) .............................................................................. 430 13.2.3 transmit shift register (tsr) ............................................................................. 431 13.2.4 transmit data register (tdr)............................................................................. 431 13.2.5 serial mode register (smr)................................................................................ 432 rev.5.00 sep. 12, 2007 page xxiv of xxviii rej09b0396-0500 13.2.6 serial control regi ster (scr).............................................................................. 436 13.2.7 serial status register (ssr) ................................................................................ 441 13.2.8 bit rate register (brr) ...................................................................................... 446 13.3 operation ...................................................................................................................... .... 454 13.3.1 overview.............................................................................................................. 454 13.3.2 operation in async hronous m ode ....................................................................... 457 13.3.3 multiprocessor communication........................................................................... 466 13.3.4 synchronous op eration........................................................................................ 473 13.4 sci interrupts................................................................................................................. ... 481 13.5 usage notes .................................................................................................................... .. 482 13.5.1 notes on use of sci ............................................................................................ 482 section 14 smart card interface ..................................................................................... 487 14.1 overview....................................................................................................................... .... 487 14.1.1 features................................................................................................................ 487 14.1.2 block diagram..................................................................................................... 488 14.1.3 pin configuration................................................................................................. 488 14.1.4 register configuration......................................................................................... 489 14.2 register descriptions ........................................................................................................ 4 90 14.2.1 smart card mode register (scmr) .................................................................... 490 14.2.2 serial status register (ssr) ................................................................................ 492 14.2.3 serial mode register (smr) ............................................................................... 494 14.2.4 serial control regi ster (scr).............................................................................. 494 14.3 operation ...................................................................................................................... .... 495 14.3.1 overview.............................................................................................................. 495 14.3.2 pin connections ................................................................................................... 495 14.3.3 data format ......................................................................................................... 496 14.3.4 register settings .................................................................................................. 498 14.3.5 clock.................................................................................................................... 499 14.3.6 transmitting and receiving data ........................................................................ 501 14.4 usage notes .................................................................................................................... .. 509 section 15 a/d converter ................................................................................................. 513 15.1 overview....................................................................................................................... .... 513 15.1.1 features................................................................................................................ 513 15.1.2 block diagram..................................................................................................... 514 15.1.3 pin configuration................................................................................................. 515 15.1.4 register configuration......................................................................................... 516 15.2 register descriptions ........................................................................................................ 5 16 15.2.1 a/d data registers a to d (addra to addrd) ............................................. 516 rev.5.00 sep. 12, 2007 page xxv of xxviii rej09b0396-0500 15.2.2 a/d control/status register (adcsr) ............................................................... 518 15.2.3 a/d control register (adcr) ............................................................................ 520 15.3 cpu interface.................................................................................................................. .. 522 15.4 operation...................................................................................................................... ..... 523 15.4.1 single mode (scan = 0)..................................................................................... 523 15.4.2 scan mode (scan = 1)....................................................................................... 525 15.4.3 input sampling and a/d conversion time.......................................................... 527 15.4.4 external trigger input timi ng............................................................................. 528 15.5 interrupts ..................................................................................................................... ...... 528 15.6 usage notes .................................................................................................................... .. 529 section 16 d/a converter ................................................................................................. 535 16.1 overview....................................................................................................................... .... 535 16.1.1 features................................................................................................................ 535 16.1.2 block diagram ..................................................................................................... 536 16.1.3 pin configuration................................................................................................. 536 16.1.4 register configuration......................................................................................... 537 16.2 register descriptions ........................................................................................................ 5 37 16.2.1 d/a data registers 0 and 1 (dadr0/1).............................................................. 537 16.2.2 d/a control register (dacr) ............................................................................ 538 16.2.3 d/a standby control register (dastcr).......................................................... 539 16.3 operation...................................................................................................................... ..... 540 16.4 d/a output control .......................................................................................................... 54 1 section 17 ram .................................................................................................................. 543 17.1 overview....................................................................................................................... .... 543 17.1.1 block diagram ..................................................................................................... 543 17.1.2 register configuration......................................................................................... 544 17.2 system control register (syscr) ................................................................................... 544 17.3 operation...................................................................................................................... ..... 545 section 18 clock pulse generator .................................................................................. 547 18.1 overview....................................................................................................................... .... 547 18.1.1 block diagram ..................................................................................................... 547 18.2 oscillator circuit............................................................................................................. .. 548 18.2.1 connecting a crystal resonator........................................................................... 548 18.2.2 external clock input ............................................................................................ 550 18.3 duty adjustment circuit ................................................................................................... 552 18.4 prescalers ..................................................................................................................... ..... 552 18.5 frequency divider............................................................................................................. 552 rev.5.00 sep. 12, 2007 page xxvi of xxviii rej09b0396-0500 18.5.1 register configuration......................................................................................... 553 18.5.2 division control regi ster (divcr) .................................................................... 553 18.5.3 usage notes ......................................................................................................... 554 section 19 power-down state ......................................................................................... 555 19.1 overview....................................................................................................................... .... 555 19.2 register configuration...................................................................................................... 55 7 19.2.1 system control register (syscr) ...................................................................... 557 19.2.2 module standby control re gister h (mstcrh)................................................ 559 19.2.3 module standby control re gister l (mstcrl)................................................. 560 19.3 sleep mode ..................................................................................................................... .. 562 19.3.1 transition to sleep mode..................................................................................... 562 19.3.2 exit from sleep mode.......................................................................................... 562 19.4 software sta ndby mode .................................................................................................... 563 19.4.1 transition to software standby mode ................................................................. 563 19.4.2 exit from software standby mode ...................................................................... 563 19.4.3 selection of waiting time for exit from software standby mode...................... 564 19.4.4 sample application of so ftware sta ndby mode .................................................. 565 19.4.5 note...................................................................................................................... 565 19.5 hardware standby mode .................................................................................................. 566 19.5.1 transition to hardware standby mode................................................................ 566 19.5.2 exit from hardware standby mode ..................................................................... 566 19.5.3 timing for hardware standby mode ................................................................... 566 19.6 module standby function................................................................................................. 567 19.6.1 module standby timing ...................................................................................... 567 19.6.2 read/write in m odule standb y............................................................................ 567 19.6.3 usage notes ......................................................................................................... 567 19.7 system clock output di sabling function......................................................................... 568 section 20 electrical characteristics ............................................................................. 569 20.1 absolute maximum ratings ............................................................................................. 569 20.2 electrical charact eristics................................................................................................... 5 70 20.2.1 dc characteristics ............................................................................................... 570 20.2.2 ac characteristics ............................................................................................... 580 20.2.3 a/d conversion characteristics........................................................................... 588 20.2.4 d/a conversion characteristics........................................................................... 590 20.3 operational timing........................................................................................................... 5 91 20.3.1 clock timi ng ....................................................................................................... 591 20.3.2 control signal timing ......................................................................................... 592 20.3.3 bus timing .......................................................................................................... 593 rev.5.00 sep. 12, 2007 page xxvii of xxviii rej09b0396-0500 20.3.4 dram interface bus timing .............................................................................. 599 20.3.5 tpc and i/o port timing..................................................................................... 602 20.3.6 timer input/output timing ................................................................................. 603 20.3.7 sci input/output timing ..................................................................................... 604 20.3.8 dmac timing..................................................................................................... 605 appendix a instruction set .............................................................................................. 607 a.1 instruction list ............................................................................................................... ... 607 a.2 operation code maps ....................................................................................................... 622 a.3 number of states required for execution ........................................................................ 625 appendix b internal i/o registers ................................................................................. 634 b.1 addresses ...................................................................................................................... .... 634 b.2 functions...................................................................................................................... ..... 643 appendix c i/o port block diagrams ........................................................................... 719 c.1 port 4 block diagram ....................................................................................................... 719 c.2 port 6 block diagrams...................................................................................................... 720 c.3 port 7 block diagrams...................................................................................................... 723 c.4 port 8 block diagrams...................................................................................................... 725 c.5 port 9 block diagrams...................................................................................................... 729 c.6 port a block diagrams ..................................................................................................... 735 c.7 port b block diagrams ..................................................................................................... 738 appendix d pin states ....................................................................................................... 744 d.1 port states in each mode .................................................................................................. 744 d.2 pin states at reset ............................................................................................................ . 750 appendix e timing of transition to and recovery from hardware standby mode ............................................................................................... 752 appendix f list of product codes ................................................................................. 753 appendix g package dimensions .................................................................................. 754 appendix h comparison of h8/ 300h series product specifications .................. 757 h.1 differences between h8/3067 and h8/3062 group, h8/3048 group, h8/3006 and h8/3007, and h8/3002 ...................................................................................................... 757 h.2 comparison of pin functions of 100-pin package products (fp-100b, tfp-100b) ....... 760 rev.5.00 sep. 12, 2007 page xxviii of xxviii rej09b0396-0500 1. overview rev.5.00 sep. 12, 2007 page 1 of 764 rej09b0396-0500 section 1 overview 1.1 overview the h8/3006 and h8/3007 are a series of microcontrollers (mcus) that integrate system supporting functions together with an h8/300h cpu core having an original renesas architecture. the h8/300h cpu has a 32-bit inte rnal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. it can address a 16-mbyte linear address space. its instruction set is upward-compatible at the object-code level with the h8/300 cpu, enabling easy porting of software from the h8/300 series. the on-chip system supporting functions include ram, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (tpc), a watchdog timer (wdt), a serial communication interface (sci), an a/d converter, a d/a convert er, i/o ports, a direct memory access controller (dmac), and other facilities. four mcu operating modes offer a choice of bus width and address space size. table 1.1 summarizes the features of the h8/3006 and h8/3007. 1. overview rev.5.00 sep. 12, 2007 page 2 of 764 rej09b0396-0500 table 1.1 features feature description cpu upward-compatible with the h8/300 cpu at the object-code level general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers) high-speed operation ? maximum clock rate: 20 mhz ? add/subtract: 100 ns ? multiply/divide: 700 ns 16-mbyte address space instruction features ? 8/16/32-bit data transfer, arithmetic, and logic instructions ? signed and unsigned multiply instructions (8 bits 8 bits, 16 bits 16 bits) ? signed and unsigned divide instructions (16 bits 8 bits, 32 bits 16 bits) ? bit accumulator function ? bit manipulation instructions with register-indirect specification of bit positions memory h8/3007 ? ram: 4 kbytes h8/3006 ? ram: 2 kbytes interrupt controller ? seven external interrupt pins: nmi, irq 0 to irq 5 ? 36 internal interrupts ? three selectable interrupt priority levels 1. overview rev.5.00 sep. 12, 2007 page 3 of 764 rej09b0396-0500 feature description bus controller ? address space can be partitioned into eight areas, with independent bus specifications in each area ? chip select output available for areas 0 to 7 ? 8-bit access or 16-bit access selectable for each area ? two-state or three-state access selectable for each area ? selection of two wait modes ? number of program wait states selectable for each area ? direct connection of burst rom ? direct connection of up to 8-mbyte dram (or dram interface can be used as interval timer) ? bus arbitration function dma controller (dmac) short address mode ? maximum four channels available ? selection of i/o mode, idle mode, or repeat mode ? can be activated by compare match/input capture a interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the a/d converter, transmit-data-empty and receive-data-full interrupts from the sci, or external requests full address mode ? maximum two channels available ? selection of normal mode or block transfer mode ? can be activated by compare match/input capture a interrupts from 16-bit timer channels 0 to 2, conversion-end interrupts from the a/d converter, external requests, or auto-request 16-bit timer, 3 channels ? three 16-bit timer channels, capable of processing up to six pulse outputs or six pulse inputs ? 16-bit timer counter (channels 0 to 2) ? two multiplexed output compare/input capture pins (channels 0 to 2) ? operation can be synchronized (channels 0 to 2) ? pwm mode available (channels 0 to 2) ? phase counting mode available (channel 2) ? dmac can be activated by compare match/input capture a interrupts (channels 0 to 2) 1. overview rev.5.00 sep. 12, 2007 page 4 of 764 rej09b0396-0500 feature description 8-bit timer, 4 channels ? 8-bit up-counter (external event count capability) ? two time constant registers ? two channels can be connected programmable timing pattern controller (tpc) ? maximum 16-bit pulse output, using 16-bit timer as time base ? up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) ? non-overlap mode available ? output data can be transferred by dmac watchdog timer (wdt), 1 channel ? internal reset signal can be generated by overflow ? reset signal can be output externally ? usable as an interval timer serial communication interface (sci), 3 channels ? selection of asynchronous or synchronous mode ? full duplex: can transmit and receive simultaneously ? on-chip baud-rate generator ? smart card interface functions added a/d converter ? resolution: 10 bits ? eight channels, with selection of single or scan mode ? variable analog conversion voltage range ? sample-and-hold function ? a/d conversion can be started by an external trigger or 8-bit timer compare- match ? dmac can be activated by an a/d conversion end interrupt d/a converter ? resolution: 8 bits ? two channels ? d/a outputs can be sustained in software standby mode i/o ports ? 35 input/output pins ? 12 input-only pins 1. overview rev.5.00 sep. 12, 2007 page 5 of 764 rej09b0396-0500 feature description four mcu operating modes operating modes mode address space address pins initial bus width max. bus width mode 1 1 mbyte a 19 to a 0 8 bits 16 bits mode 2 1 mbyte a 19 to a 0 16 bits 16 bits mode 3 16 mbytes a 23 to a 0 8 bits 16 bits mode 4 16 mbytes a 23 to a 0 16 bits 16 bits power-down state ? sleep mode ? software standby mode ? hardware standby mode ? module standby function ? programmable system clock frequency division other features ? on-chip clock pulse generator product lineup part no. model package h8/3007 hd6413007f 100-pin qfp (fp-100b) 5 v 10 % (5 v) hd6413007te 100-pin tqfp (tfp-100b) hd6413007fp 100-pin qfp (fp-100a) hd6413007vf 100-pin qfp (fp-100b) 2.7 to 5.5 v (low voltage) hd6413007vte 100-pin tqfp (tfp-100b) hd6413007vfp 100-pin qfp (fp-100a) h8/3006 hd6413006f 100-pin qfp (fp-100b) 5 v 10 % (5 v) hd6413006te 100-pin tqfp (tfp-100b) hd6413006fp 100-pin qfp (fp-100a) hd6413006vf 100-pin qfp (fp-100b) 2.7 to 5.5 v (low voltage) hd6413006vte 100-pin tqfp (tfp-100b) hd6413006vfp 100-pin qfp (fp-100a) 1. overview rev.5.00 sep. 12, 2007 page 6 of 764 rej09b0396-0500 1.2 internal block diagram figure 1.1 shows an internal block diagram. v v v v v v v v v cc cc cc ss ss ss ss ss ss d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 data bus port 4 port 9 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 p9 /sck / irq p9 /sck / irq p9 /rxd p9 /rxd p9 /txd p9 /txd 5 4 3 2 1 0 1 0 1 0 1 0 5 4 da 1 /an 7 /p7 7 da 0 /an 6 /p7 6 an 5 /p7 5 an 4 /p7 4 an 3 /p7 3 an 2 /p7 2 an 1 /p7 1 an 0 /p7 0 port 7 a 20 /tiocb 2 /tp 7 /pa 7 a 21 /tioca 2 /tp 6 /pa 6 a 22 /tiocb 1 /tp 5 /pa 5 a 23 /tioca 1 /tp 4 /pa 4 tclkd/tiocb 0 /tp 3 /pa 3 tclkc/tioca 0 /tp 2 /pa 2 tend 1 /tclkb/tp 1 /pa 1 tend 0 /tclka/tp 0 /pa 0 port a rxd 2 /tp 15 /pb 7 txd 2 /tp 14 /pb 6 sck 2 / lcas /tp 13 /pb 5 ucas /tp 12 /pb 4 cs 4 / dreq 1 /tmio 3 /tp 11 /pb 3 cs 5 /tmo 2 /tp 10 /pb 2 cs 6 / dreq 0 /tmio 1 /tp 9 /pb 1 cs 7 /tmo 0 /tp 8 /pb 0 port 8 cs 0 /p8 4 adtrg / cs 1 / irq 3 /p8 3 cs 2 / irq 2 /p8 2 cs 3 / irq 1 /p8 1 rfsh / irq 0 /p8 0 md 2 md 1 md 0 extal xtal stby res reso nmi h8/300h cpu clock pulse g enerator interrupt controller dma controller (dmac) serial communication interface (sci) 3 channels watchdo g timer (wdt) address bus data bus (upper) data bus (lower) address bus as rd hwr lwr /p6 7 back /p6 2 breq /p6 1 wait /p6 0 ram 16-bit timer unit 8-bit timer unit a/d converter d/a converter port 6 bus controller pro g rammable timin g pattern controller (tpc) port b v ref av cc av ss figure 1.1 block diagram 1. overview rev.5.00 sep. 12, 2007 page 7 of 764 rej09b0396-0500 1.3 pin description 1.3.1 pin arrangement the pin arrangement of the h8/3006, h8/3007 fp-100b and tfp-100b packages is shown in figure 1.2, and that of the fp-100a package in figure 1.3. v cc cs 7 /tmo 0 /tp 8 /pb 0 cs 6 / dreq 0 /tmio 1 /tp 9 /pb 1 cs 5 /tmo 2 /tp 10 /pb 2 cs 4 / dreq 1 /tmio 3 /tp 11 /pb 3 ucas /tp 12 /pb 4 sck 2 / lcas /tp 13 /pb 5 txd 2 /tp 14 /pb 6 rxd 2 /tp 15 /pb 7 0 1 2 3 4 5 0 1 2 3 4 5 6 reso v ss txd /p9 txd /p9 rxd /p9 rxd /p9 irq /sck /p9 irq /sck /p9 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 d /p4 md md md lwr hwr rd as v xtal extal v nmi res stby p6 7 / p6 / back p6 / bre q p6 / wait v a 19 a 18 a 17 a 16 a 15 a 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 a 13 a 12 a 11 a 10 a 9 a 8 v ss a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 /p4 7 0 1 0 1 0 1 0 1 2 3 4 5 6 4 5 2 1 0 2 1 0 cc ss ss v ss to p v i e w (fp-100b, tfp-100b) index av cc v ref p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 /da 0 p7 7 /an 7 /da 1 av ss p8 0 / irq 0 / rfsh p8 1 / irq 1 / cs 3 p8 2 / irq 2 / cs 2 p8 3 / irq 3 / cs 1 / adtrg p8 4 / cs 0 v ss pa 0 /tp 0 /tclka/ tend 0 pa 1 /tp 1 /tclkb/ tend 1 pa 2 /tp 2 /tioca 0 /tclkc pa 3 /tp 3 /tiocb 0 /tclkd pa 4 /tp 4 /tioca 1 /a 23 pa 5 /tp 5 /tiocb 1 /a 22 pa 6 /tp 6 /tioca 2 /a 21 pa 7 /tp 7 /tiocb 2 /a 20 figure 1.2 pin arrangement (fp-100b or tfp-100b, top view) 1. overview rev.5.00 sep. 12, 2007 page 8 of 764 rej09b0396-0500 p7 0 /an 0 v ref av cc md 2 md 1 md 0 lwr hwr rd as v cc xtal extal v ss nmi res stby p6 7 / p6 2 / back p6 1 / bre q p6 0 / wait v ss a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a /tioca /tp /pa a /tiocb /tp /pa cs /tmo /tp /pb cs / dreq /tmio /tp /pb cs /tmo /tp /pb cs / dreq /tmio /tp /pb ucas /tp /pb sck / lcas /tp /pb txd /tp /pb rxd /tp /pb reso txd /p9 txd /p9 rxd /p9 rxd /p9 irq /sck /p9 irq /sck /p9 d /p4 d /p4 d /p4 d /p4 d 4 /p4 4 d 5 /p4 5 d 6 /p4 6 d 7 /p4 7 d 8 d 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 21 26 6 20 27 7 08 0 19 1 4 11 3 1 3 2 2 15 7 2 4 12 5 13 6 14 6 7 210 2 5 0 ss 0 1 0 1 404 515 0 1 0 1 2 3 0 1 2 3 2 3 v cc v ss 80 79 78 77 76 v top view (fp-100a) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 a 11 a 10 a 9 a 8 v ss a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc d 15 d 14 d 13 d 12 d 11 d 10 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 /da 0 p7 7 /an 7 /da 1 av ss p8 0 / irq 0 / rfsh p8 1 / irq 1 / cs 3 p8 2 / irq 2 / cs 2 p8 3 / irq 3 / cs 1 / adtrg p8 4 / cs 0 v ss pa 0 /tp 0 /tclka/ tend 0 pa 1 /tp 1 /tclkb/ tend 1 pa 2 /tp 2 /tioca 0 /tclkc pa 3 /tp 3 /tiocb 0 /tclkd pa 4 /tp 4 /tioca 1 /a 23 pa 5 /tp 5 /tiocb 1 /a 22 figure 1.3 pin arrangem ent (fp-100a, top view) 1. overview rev.5.00 sep. 12, 2007 page 9 of 764 rej09b0396-0500 1.3.2 pin functions table 1.2 summarizes the pin functions. table 1.2 pin functions pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function power v cc 1, 35, 68 3, 37, 70 input power: for connection to the power supply. connect all v cc pins to the system power supply. v ss 11, 22, 44, 57, 65, 92 13, 24, 46, 59, 67, 94 input ground: for connection to ground (0 v). connect all v ss pins to the 0-v system power supply. clock xtal 67 69 input for connection to a crystal resonator. for examples of crystal resonator and external clock input, see section 18, clock pulse generator. extal 66 68 input for connection to a crystal resonator or input of an external clock signal. for examples of crystal resonator and external clock input, see section 18, clock pulse generator. 61 63 output system clock: supplies the system clock to external devices. operating mode control md 2 to md 0 75 to 73 77 to 75 input mode 2 to mode 0: for setting the operating mode, as follows. inputs at these pins must not be changed during operation. md 2 md 1 md 0 operating mode 0 0 0 ? 0 0 1 mode 1 0 1 0 mode 2 0 1 1 mode 3 1 0 0 mode 4 1 0 1 ? 1 1 0 ? 1 1 1 ? 1. overview rev.5.00 sep. 12, 2007 page 10 of 764 rej09b0396-0500 pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function system control res 63 65 input reset input: when driven low, this pin resets the chip. reso 10 12 output reset output: outputs the reset signal generated by the watchdog timer to external devices stby 62 64 input standby: when driven low, this pin forces a transition to hardware standby mode. breq 59 61 input bus request: used by an external bus master to request the bus right back 60 62 output bus request acknowledge: indicates that the bus has been granted to an external bus master interrupts nmi 64 66 input nonmaskable interrupt: requests a nonmaskable interrupt irq 5 to irq 0 17, 16, 90 to 87 19, 18, 92 to 89 input interrupt request 5 to 0: maskable interrupt request pins address bus a 23 to a 0 100 to 97, 56 to 45, 43 to 36 99, 100, 1, 2, 58 to 47, 45 to 38 output address bus: outputs address signals data bus d 15 to d 0 34 to 23, 21 to 18 36 to 25, 23 to 20 input/ output data bus: bidirectional data bus bus control cs 7 to cs 0 2 to 5, 88 to 91 4 to 7, 90 to 93 output chip select: select signals for areas 7 to 0 as 69 71 output address strobe: goes low to indicate valid address output on the address bus rd 70 72 output read: goes low to indicate reading from the external address space hwr 71 73 output high write: goes low to indicate writing to the external address space; indicates valid data on the upper data bus (d 15 to d 8 ). lwr 72 74 output low write: goes low to indicate writing to the external address space; indicates valid data on the lower data bus (d 7 to d 0 ). wait 58 60 input wait: requests insertion of wait states in bus cycles during access to the external address space 1. overview rev.5.00 sep. 12, 2007 page 11 of 764 rej09b0396-0500 pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function rfsh 87 89 output refresh: indicates a refresh cycle dram interface cs 2 to cs 5 89, 88, 5, 4 91, 90, 7, 6 output row address strobe ras : row address strobe signal for dram rd 70 72 output write enable we : write enable signal for dram hwr ucas 71 6 73 8 output upper column address strobe ucas : column address strobe signal for dram lwr lcas 72 7 74 9 output lower column address strobe lcas : column address strobe signal for dram dreq 1 , dreq 0 5, 3 7, 5 input dma request 1 and 0: dmac activation requests dma controller (dmac) tend 1 , tend 0 94, 93 96, 95 output transfer end 1 and 0: these signals indicate that the dmac has ended a data transfer. 16-bit timer tclkd to tclka 96 to 93 98 to95 input clock input d to a: external clock inputs tioca 2 to tioca 0 99, 97, 95 1, 99, 97 input/ output input capture/output compare a2 to a0: gra2 to gra0 output compare or input capture, or pwm output tiocb 2 to tiocb 0 100, 98, 96 2, 100, 98 input/ output input capture/output compare b2 to b0: grb2 to grb0 output compare or input capture, or pwm output 8-bit timer tmo 0 , tmo 2 2, 4 4, 6 output compare match output: compare match output pins tmio 1 , tmio 3 3, 5 5, 7 input/ output input capture input/compare match output: input capture input or compare match output pins tclkd to tclka 96 to 93 98 to 95 input counter external clock input: these pins input an external clock to the counters. 1. overview rev.5.00 sep. 12, 2007 page 12 of 764 rej09b0396-0500 pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function program- mable timing pattern controller (tpc) tp 15 to tp 0 9 to 2, 100 to 93 11 to 4, 2, 1, 100 to 95 output tpc output 15 to 0: pulse output txd 2 to txd 0 8, 13, 12 10, 15, 14 output transmit data (channels 0, 1, 2): sci data output rxd 2 to rxd 0 9, 15, 14 11, 17, 16 input receive data (channels 0, 1, 2): sci data input serial communi- cation interface (sci) sck 2 to sck 0 7, 17, 16 9, 19, 18 input/ output serial clock (channels 0, 1, 2): sci clock input/output a/d converter an 7 to an 0 85 to 78 87 to 80 input analog 7 to 0: analog input pins adtrg 90 92 input a/d conversion external trigger input: external trigger input for starting a/d conversion d/a converter da 1 , da 0 85, 84 87, 86 output analog output: analog output from the d/a converter a/d and d/a converters av cc 76 78 input power supply pin for the a/d and d/a converters. connect to the system power supply when not using the a/d and d/a converters. av ss 86 88 input ground pin for the a/d and d/a converters. connect to system ground (0 v). v ref 77 79 input reference voltage input pin for the a/d and d/a converters. connect to the system power supply when not using the a/d and d/a converters. 1. overview rev.5.00 sep. 12, 2007 page 13 of 764 rej09b0396-0500 pin no. type symbol fp-100b tfp-100b fp-100a i/o name and function i/o ports p4 7 to p4 0 26 to 23, 21 to 18 28 to 25, 23 to 20 input/ output port 4: eight-bit input/output pins. the direction of each-bit pin can be selected in the port 4 data direction register (p4ddr). p6 7 , p6 2 to p6 0 61 to 58 63 to 60 input/ output port 6: four-bit input/output pins. the direction of each-bit pin can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 85 to 78 87 to 80 input port 7: eight-bit input pins p8 4 to p8 0 91 to 87 93 to 89 input/ output port 8: five-bit input/output pins. the direction of each-bit pin can be selected in the port 8 data direction register (p8ddr). p9 5 to p9 0 17 to 12 19 to 14 input/ output port 9: six-bit input/output pins. the direction of each-bit pin can be selected in the port 9 data direction register (p9ddr). pa 7 to pa 0 100 to 93 2, 1, 100 to 95 input/ output port a: eight-bit input/output pins. the direction of each-bit pin can be selected in the port a data direction register (paddr). pb 7 to pb 0 9 to 2 11 to 4 input/ output port b: eight-bit input/output pins. the direction of each-bit pin can be selected in the port b data direction register (pbddr). 1. overview rev.5.00 sep. 12, 2007 page 14 of 764 rej09b0396-0500 1.3.3 pin assignments in each mode table 1.3 lists the pin assignments in each mode. table 1.3 pin assignments in each mode (fp-100b or tfp-100b, fp-100a) pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 1 3 v cc v cc v cc v cc 2 4 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 3 5 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 4 6 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 5 7 pb 3 /tp 11 /tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 /tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 /tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 /tmio 3 / dreq 1 / cs 4 6 8 pb 4 /tp 12 / ucas pb 4 /tp 12 / ucas pb 4 /tp 12 / ucas pb 4 /tp 12 / ucas 7 9 pb 5 /tp 13 / lcas / sck 2 pb 5 /tp 13 / lcas / sck 2 pb 5 /tp 13 / lcas / sck 2 pb 5 /tp 13 / lcas / sck 2 8 10 pb 6 /tp 14 /txd 2 pb 6 /tp 14 /txd 2 pb 6 /tp 14 /txd 2 pb 6 /tp 14 /txd 2 9 11 pb 7 /tp 15 /rxd 2 pb 7 /tp 15 /rxd 2 pb 7 /tp 15 /rxd 2 pb 7 /tp 15 /rxd 2 10 12 reso reso reso reso 11 13 v ss v ss v ss v ss 12 14 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 13 15 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 14 16 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 15 17 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 16 18 p9 4 / irq 4 /sck 0 p9 4 / irq 4 /sck 0 p9 4 / irq 4 /sck 0 p9 4 / irq 4 /sck 0 17 19 p9 5 / irq 5 /sck 1 p9 5 / irq 5 /sck 1 p9 5 / irq 5 /sck 1 p9 5 / irq 5 /sck 1 18 20 p4 0 /d 0 * 1 p4 0 /d 0 * 2 p4 0 /d 0 * 1 p4 0 /d 0 * 2 19 21 p4 1 /d 1 * 1 p4 1 /d 1 * 2 p4 1 /d 1 * 1 p4 1 /d 1 * 2 20 22 p4 2 /d 2 * 1 p4 2 /d 2 * 2 p4 2 /d 2 * 1 p4 2 /d 2 * 2 21 23 p4 3 /d 3 * 1 p4 3 /d 3 * 2 p4 3 /d 3 * 1 p4 3 /d 3 * 2 22 24 v ss v ss v ss v ss 23 25 p4 4 /d 4 * 1 p4 4 /d 4 * 2 p4 4 /d 4 * 1 p4 4 /d 4 * 2 1. overview rev.5.00 sep. 12, 2007 page 15 of 764 rej09b0396-0500 pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 24 26 p4 5 /d 5 * 1 p4 5 /d 5 * 2 p4 5 /d 5 * 1 p4 5 /d 5 * 2 25 27 p4 6 /d 6 * 1 p4 6 /d 6 * 2 p4 6 /d 6 * 1 p4 6 /d 6 * 2 26 28 p4 7 /d 7 * 1 p4 7 /d 7 * 2 p4 7 /d 7 * 1 p4 7 /d 7 * 2 27 29 d 8 d 8 d 8 d 8 28 30 d 9 d 9 d 9 d 9 29 31 d 10 d 10 d 10 d 10 30 32 d 11 d 11 d 11 d 11 31 33 d 12 d 12 d 12 d 12 32 34 d 13 d 13 d 13 d 13 33 35 d 14 d 14 d 14 d 14 34 36 d 15 d 15 d 15 d 15 35 37 v cc v cc v cc v cc 36 38 a 0 a 0 a 0 a 0 37 39 a 1 a 1 a 1 a 1 38 40 a 2 a 2 a 2 a 2 39 41 a 3 a 3 a 3 a 3 40 42 a 4 a 4 a 4 a 4 41 43 a 5 a 5 a 5 a 5 42 44 a 6 a 6 a 6 a 6 43 45 a 7 a 7 a 7 a 7 44 46 v ss v ss v ss v ss 45 47 a 8 a 8 a 8 a 8 46 48 a 9 a 9 a 9 a 9 47 49 a 10 a 10 a 10 a 10 48 50 a 11 a 11 a 11 a 11 49 51 a 12 a 12 a 12 a 12 50 52 a 13 a 13 a 13 a 13 51 53 a 14 a 14 a 14 a 14 52 54 a 15 a 15 a 15 a 15 53 55 a 16 a 16 a 16 a 16 54 56 a 17 a 17 a 17 a 17 1. overview rev.5.00 sep. 12, 2007 page 16 of 764 rej09b0396-0500 pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 55 57 a 18 a 18 a 18 a 18 56 58 a 19 a 19 a 19 a 19 57 59 v ss v ss v ss v ss 58 60 p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait 59 61 p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq 60 62 p6 2 / back p6 2 / back p6 2 / back p6 2 / back 61 63 p6 7 / p6 7 / p6 7 / p6 7 / 62 64 stby stby stby stby 63 65 res res res res 64 66 nmi nm i nmi nmi 65 67 v ss v ss v ss v ss 66 68 extal extal extal extal 67 69 xtal xtal xtal xtal 68 70 v cc v cc v cc v cc 69 71 as as as as 70 72 rd rd rd rd 71 73 hwr hwr hwr hwr 72 74 lwr lwr lwr lwr 73 75 md 0 md 0 md 0 md 0 74 76 md 1 md 1 md 1 md 1 75 77 md 2 md 2 md 2 md 2 76 78 av cc av cc av cc av cc 77 79 v ref v ref v ref v ref 78 80 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 79 81 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 80 82 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 81 83 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 82 84 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 83 85 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 84 86 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 85 87 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 1. overview rev.5.00 sep. 12, 2007 page 17 of 764 rej09b0396-0500 pin no. pin name fp-100b tfp-100b fp-100a mode 1 mode 2 mode 3 mode 4 86 88 av ss av ss av ss av ss 87 89 p8 0 / irq 0 / rfsh p8 0 / irq 0 / rfsh p8 0 / irq 0 / rfsh p8 0 / irq 0 / rfsh 88 90 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 p8 1 / irq 1 / cs 3 89 91 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 p8 2 / irq 2 / cs 2 90 92 p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg p8 3 / irq 3 / cs 1 / adtrg 91 93 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 92 94 v ss v ss v ss v ss 93 95 pa 0 /tp 0 /tclka/ tend 0 pa 0 /tp 0 /tclka/ tend 0 pa 0 /tp 0 /tclka/ tend 0 pa 0 /tp 0 /tclka/ tend 0 94 96 pa 1 /tp 1 /tclkb/ tend 1 pa 1 /tp 1 /tclkb/ tend 1 pa 1 /tp 1 /tclkb/ tend 1 pa 1 /tp 1 /tclkb/ tend 1 95 97 pa 2 /tp 2 /tioca 0 / tclkc pa 2 /tp 2 /tioca 0 / tclkc pa 2 /tp 2 /tioca 0 / tclkc pa 2 /tp 2 /tioca 0 / tclkc 96 98 pa 3 /tp 3 /tiocb 0 / tclkd pa 3 /tp 3 /tiocb 0 / tclkd pa 3 /tp 3 /tiocb 0 / tclkd pa 3 /tp 3 /tiocb 0 / tclkd 97 99 pa 4 /tp 4 /tioca 1 pa 4 /tp 4 /tioca 1 pa 4 /tp 4 /tioca 1 / a 23 pa 4 /tp 4 /tioca 1 / a 23 98 100 pa 5 /tp 5 /tiocb 1 pa 5 /tp 5 /tiocb 1 pa 5 /tp 5 /tiocb 1 / a 22 pa 5 /tp 5 /tiocb 1 / a 22 99 1 pa 6 /tp 6 /tioca 2 pa 6 /tp 6 /tioca 2 pa 6 /tp 6 /tioca 2 / a 21 pa 6 /tp 6 /tioca 2 / a 21 100 2 pa 7 /tp 7 /tiocb 2 pa 7 /tp 7 /tiocb 2 a 20 a 20 notes: 1. in modes 1 and 3, the p4 0 to p4 7 functions of pins p4 0 /d 0 to p4 7 /d 7 are selected after a reset, but they can be changed by software. 2. in modes 2 and 4, the d 0 to d 7 functions of pins p4 0 /d 0 to p4 7 /d 7 are selected after a reset, but they can be changed by software. 1. overview rev.5.00 sep. 12, 2007 page 18 of 764 rej09b0396-0500 2. cpu rev.5.00 sep. 12, 2007 page 19 of 764 rej09b0396-0500 section 2 cpu 2.1 overview the h8/300h cpu is a high-speed cen tral processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 cpu. the h8/300h cpu has sixteen 16-bit general registers, can address a 16-mbyte linear addr ess space, and is ideal for realtime control. 2.1.1 features the h8/300h cpu has th e following features. ? upward compatibility with h8/300 cpu can execute h8/300 series object programs ? general-register architecture sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? sixty-two basic instructions ? 8/16/32-bit data transfer, arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacemen t [@(d:16, ern) or @(d:24, ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, or @aa:24] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8, pc) or @(d:16, pc)] ? memory indirect [@@aa:8] ? 16-mbyte linear address space 2. cpu rev.5.00 sep. 12, 2007 page 20 of 764 rej09b0396-0500 ? high-speed operation ? all frequently-used instructions execute in two to four states ? maximum clock frequency: 20 mhz ? 8/16/32-bit register-register add/subtract: 100 ns ? 8 8-bit register-register multiply: 700 ns ? 16 8-bit register-register divide: 700 ns ? 16 16-bit register-register multiply: 1.1 s ? 32 16-bit register-register divide: 1.1 s ? two cpu operating modes ? normal mode (not available in the h8/3006 and h8/3007) ? advanced mode ? low-power mode transition to power-down state by sleep instruction 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8/300h has the following enhancements. ? more general registers eight 16-bit registers have been added. ? expanded address space ? advanced mode supports a maximum 16-mbyte address space. ? normal mode supports the same 64-kbyt e address space as the h8/300 cpu. ? enhanced addressing the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? data transfer, arithmetic, and logic instructions can operate on 32-bit data. ? signed multiply/divide instructions and other instructions have been added. 2. cpu rev.5.00 sep. 12, 2007 page 21 of 764 rej09b0396-0500 2.2 cpu operating modes the h8/300h cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports up to 16 mbytes. cpu operatin g modes note: * normal mode is not available in the h8/3006 and h8/3007. normal mode * advanced mode maximum 64 kbytes, pro g ram and data areas combined maximum 16 mbytes, pro g ram and data areas combined figure 2.1 cpu operating modes 2. cpu rev.5.00 sep. 12, 2007 page 22 of 764 rej09b0396-0500 2.3 address space figure 2.2 shows a simple memory map for the h8/3006 and h8/3007. the h8/300h cpu can address a linear address space with a maximum si ze of 64 kbytes in normal mode, and 16 mbytes in advanced mode. for further details see secti on 3.6, memory map in each operating mode. the 1-mbyte operating modes use 20-bit addressing. the upper 4 bits of effective addresses are ignored. h'00000 h'fffff h'000000 h'ffffff a. 1-mbyte mode b. 16-mbyte mode h'0000 note: * normal mode is not available in the h8/3006 and h8/3007. h'ffff advanced mode normal mode * figure 2.2 memory map 2. cpu rev.5.00 sep. 12, 2007 page 23 of 764 rej09b0396-0500 2.4 register configuration 2.4.1 overview the h8/300h cpu has the internal registers shown in figure 2.3. there are two types of registers: general registers and control registers. er0 er1 er2 er3 er4 er5 er6 er7 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l 0 7 0 7 0 15 (sp) 23 0 pc 7 ccr 6543210 iuihunzvc general registers (ern) control registers (cr) le g end: sp: pc: ccr: i: ui: h: u: n: z: v: c: stack pointer pro g ram counter condition code re g ister interrupt mask bit user bit or interrupt mask bit half-carry fla g user bit ne g ative fla g zero fla g overflow fla g carry fla g figure 2.3 cpu registers 2. cpu rev.5.00 sep. 12, 2007 page 24 of 764 rej09b0396-0500 2.4.2 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used without distinction between data registers and address registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit regist ers or as address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general register s designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2.4 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address re g isters ? 32-bit re g isters ? 16-bit re g isters ? 8-bit re g isters er re g isters er0 to er7 e re g isters (extended re g isters) e0 to e7 r re g isters r0 to r7 rh re g isters r0h to r7h rl re g isters r0l to r7l figure 2.4 usage of general registers 2. cpu rev.5.00 sep. 12, 2007 page 25 of 764 rej09b0396-0500 general register er7 has the function of stack poi nter (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.5 shows the stack. free area stack area sp (er7) figure 2.5 stack 2.4.3 control registers the control registers are the 24-bit program coun ter (pc) and the 8-bit condition code register (ccr). program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant pc bit is ignored. when an instruction is fetched, the least significant pc bit is regarded as 0. condition code register (ccr): this 8-bit register contains internal cpu status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7?interrupt mask bit (i): masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. bit 6?user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details see section 5, interrupt controller. bit 5?half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if th ere is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 2. cpu rev.5.00 sep. 12, 2007 page 26 of 764 rej09b0396-0500 bit 4?user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3?negative flag (n): stores the value of the most significant bit of data, regarded as the sign bit. bit 2?zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1?overflow flag (v): set to 1 when an arithmetic overflo w occurs, and cleared to 0 at other times. bit 0?carry flag (c): set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions , to indicate a borrow ? shift and rotate instructions the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave flag bits unchanged. operations can be performed on ccr by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used by conditional branch (bcc) instructions. for the action of each instruction on the flag bits , see appendix a.1, instruction list. for the i and ui bits, see section 5, interrupt controller. 2.4.4 initial cpu register values in reset exception handling, pc is initialized to a value loaded from the vector table, and the i bit in ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the initial value of the stack pointer (er7) is also undefined. the stack pointer (er7) must therefore be initialized by an mov.l instruction executed immediately after a reset. 2. cpu rev.5.00 sep. 12, 2007 page 27 of 764 rej09b0396-0500 2.5 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipul ation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figures 2.6 and 2.7 show the data formats in general registers. 7 rnh rnl rnh rnl rnh rnl 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data 6543210 70 don't care 76543210 70 don't care don't care 70 43 lower di g it upper di g it 7 43 lower di g it upper di g it don't care 0 70 don't care msb lsb don't care 70 msb lsb data type data format general register rnh: rnl: general re g ister rh general re g ister rl le g end: figure 2.6 general re gister data formats (1) 2. cpu rev.5.00 sep. 12, 2007 page 28 of 764 rej09b0396-0500 rn en ern word data word data lon g word data 15 0 msb lsb general register data type data format 15 0 msb lsb 31 16 msb 15 0 lsb le g end ern: en: rn: msb: lsb: :: general re g ister general re g ister e general re g ister r most si g nificant bit least si g nificant bit figure 2.7 general re gister data formats (2) 2.5.2 memory data formats figure 2.8 shows the data formats on memory . the h8/300h cpu can access word data and longword data on memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at th e preceding address. this also applies to instruction fetches. 2. cpu rev.5.00 sep. 12, 2007 page 29 of 764 rej09b0396-0500 76543210 address l address l lsb msb msb lsb 70 msb lsb 1-bit data byte data word data lon g word data address data type data format address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.8 memory data formats when er7 (sp) is used as an address register to access the stack, the operand size should be word size or longword size. 2. cpu rev.5.00 sep. 12, 2007 page 30 of 764 rej09b0396-0500 2.6 instruction set 2.6.1 instruction set overview the h8/300h cpu has 64 types of instructions, which are classified in table 2.1. table 2.1 instructio n classification function instruction types data transfer mov, push * 1 , pop * 1 , movtpe * 2 , movfpe * 2 5 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, mulxs, divxu, divxs, cmp, neg, exts, extu 18 logic operations and, or, xor, not 4 shift operations shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst , band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 3 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total 64 types notes: 1. pop.w rn is identical to mov.w @sp+, rn. push.w rn is identical to mov.w rn, @?sp. pop.l ern is identical to mov.l @sp+, rn. push.l ern is identical to mov.l rn, @?sp. 2. not available in the h8/3006 and h8/3007. 3. bcc is a generic branching instruction. 2. cpu rev.5.00 sep. 12, 2007 page 31 of 764 rej09b0396-0500 2.6.2 instructions and addressing modes table 2.2 indicates the instructions available in the h8/300h cpu. table 2.2 instructions and addressing modes addressing modes function instruction #xx rn @ern @ (d:16, ern) @ (d:24, ern) @ern+/ @?ern @ aa:8 @ aa:16 @ aa:24 @ (d:8, pc) @ (d:16, pc) @@ aa:8 ? data mov bwl bwl bwl bwl bwl bwl b bwl bwl ? ? ? ? transfer pop, push ? ? ? ? ? ? ? ? ? ? ? ? wl movfpe, movtpe ? ? ? ? ? ? ? ? ? ? ? ? ? arithmetic add, cmp bwl bwl ? ? ? ? ? ? ? ? ? ? ? operations sub wl bwl ? ? ? ? ? ? ? ? ? ? ? addx, subx b b ? ? ? ? ? ? ? ? ? ? ? adds, subs ? l ? ? ? ? ? ? ? ? ? ? ? inc, dec ? bwl ? ? ? ? ? ? ? ? ? ? ? daa, das ? b ? ? ? ? ? ? ? ? ? ? ? mulxu, mulxs, divxu, divxs ? bw ? ? ? ? ? ? ? ? ? ? ? neg ? bwl ? ? ? ? ? ? ? ? ? ? ? extu, exts ? wl ? ? ? ? ? ? ? ? ? ? ? and, or, xor ? bwl ? ? ? ? ? ? ? ? ? ? ? logic operations not ? bwl ? ? ? ? ? ? ? ? ? ? ? shift instructions ? bwl ? ? ? ? ? ? ? ? ? ? ? bit manipulation ? b b ? ? ? b ? ? ? ? ? ? branch bcc, bsr ? ? ? ? ? ? ? ? ? ? ? ? ? jmp, jsr ? ? ? ? ? ? ? ? ? ? rts ? ? ? ? ? ? ? ? ? ? ? system trapa ? ? ? ? ? ? ? ? ? ? ? ? control rte ? ? ? ? ? ? ? ? ? ? ? ? sleep ? ? ? ? ? ? ? ? ? ? ? ? ldc b b w w w w ? w w ? ? ? stc ? b w w w w ? w w ? ? ? ? andc, orc, xorc b ? ? ? ? ? ? ? ? ? ? ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? block data transfer ? ? ? ? ? ? ? ? ? ? ? ? bw 2. cpu rev.5.00 sep. 12, 2007 page 32 of 764 rej09b0396-0500 2.6.3 tables of instructions classified by function tables 2.3 to 2.10 summarize the instructions in each functional category. the operation notation used in these tables is defined next. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division and logical or logical exclusive or logical move ? not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit data or address registers (er0 to er7). 2. cpu rev.5.00 sep. 12, 2007 page 33 of 764 rej09b0396-0500 table 2.3 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. similarly, pop.l ern is identical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. similarly, push.l ern is identical to mov.l ern, @?sp. note: * size refers to the operand size. b: byte w: word l: longword 2. cpu rev.5.00 sep. 12, 2007 page 34 of 764 rej09b0396-0500 table 2.4 arithmetic operation instructions instruction size * function add,sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from data in a general register. use the subx or add instruction.) addx, subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register. inc, dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds, subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa, das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. 2. cpu rev.5.00 sep. 12, 2007 page 35 of 764 rej09b0396-0500 instruction size * function divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder, or 32 bits 16 bits 16-bit quotient and 16-bit remainder cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets ccr according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. exts w/l rd (sign extension) rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. extu w/l rd (zero extension) rd extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. note: * size refers to the operand size. b: byte w: word l: longword 2. cpu rev.5.00 sep. 12, 2007 page 36 of 764 rej09b0396-0500 table 2.5 logic opera tion instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? rd rd takes the one's complement (logical complement) of general register contents. note: * size refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal, shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll, shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl, rotr b/w/l rd (rotate) rd rotates general register contents. rotxl, rotxr b/w/l rd (rotate) rd rotates general register contents, including the carry bit. note: * size refers to the operand size. b: byte w: word l: longword 2. cpu rev.5.00 sep. 12, 2007 page 37 of 764 rej09b0396-0500 table 2.7 bit manipulation instructions instruction size * function bset b 1 ( 2. cpu rev.5.00 sep. 12, 2007 page 38 of 764 rej09b0396-0500 instruction size * function bor b c ( 2. cpu rev.5.00 sep. 12, 2007 page 39 of 764 rej09b0396-0500 table 2.8 branching instructions instruction size function bcc ? branches to a specified address if address specified condition is met. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine 2. cpu rev.5.00 sep. 12, 2007 page 40 of 764 rej09b0396-0500 table 2.9 system co ntrol instructions instruction size * function trapa ? starts trap-instruction exception handling rte ? returns from an exception-handling routine sleep ? causes a transition to the power-down state ldc b/w (eas) ccr moves the source operand contents to the condition code register. the condition code register size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfe r to memory, data is written by word access. andc b ccr #imm ccr logically ands the condition code register with immediate data. orc b ccr #imm ccr logically ors the condition code register with immediate data. xorc b ccr #imm ccr logically exclusive-ors the condition code register with immediate data. nop ? pc + 2 pc only increments the program counter. note: * size refers to the operand size. b: byte w: word 2. cpu rev.5.00 sep. 12, 2007 page 41 of 764 rej09b0396-0500 table 2.10 block transfer instruction instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l ? 1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4 ? 1 r4 until r4 = 0 else next; block transfer instruction. this instruction transfers the number of data bytes specified by r4l or r4, starting from the address indicated by er5, to the location starting at the address indicated by er6. at the end of the transfer, the next instruction is executed. 2.6.4 basic instruction formats the h8/300h instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an ef fective address extension (ea field), and a condition field (cc). operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first 4 bits of the instruction. some instructions have two operation fields. register field: specifies a general register. address regist ers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. a 24-bit address or di splacement is treated as 32-bit data in which the first 8 bits are 0 (h'00). condition field: specifies the branching condition of bcc instructions. figure 2.9 shows examples of instruction formats. 2. cpu rev.5.00 sep. 12, 2007 page 42 of 764 rej09b0396-0500 op nop, rts, etc. op rn rm op rn rm ea (disp) operation field only add.b rn, rm, etc. operation field and re g ister fields mov.b @(d:16, rn), rm operation field, re g ister fields, and effective address extension bra d:8 operation field, effective address extension, and condition field op cc ea (disp) figure 2.9 instruction formats 2.6.5 notes on use of bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, modify a bit in the byte, then write the byte back. care is required wh en these instructions are used to access registers with write-only bits, or to access ports. step description 1 read read one data byte at the specified address 2 modify modify one bit in the data byte 3 write write the modified data byte back to the specified address example 1: bclr is executed to clear bit 0 in the port 4 data direction register (p4ddr) under the following conditions. p4 7 , p4 6 : input pins p4 5 ? p4 0 : output pins the intended purpose of this bclr instruction is to switch p4 0 from output to input. 2. cpu rev.5.00 sep. 12, 2007 page 43 of 764 rej09b0396-0500 before execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output ddr 0 0 1 1 1 1 1 1 execution of bclr instruction bclr #0, @p4ddr ; execute bclr instruction on ddr after execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output output output output output output output output input ddr 1 1 1 1 1 1 1 0 explanation: to execute the bclr instruction, the cpu begins by reading p4ddr. since p4ddr is a write-only register, it is read as h'ff, even though its true value is h'3f. next the cpu clears bit 0 of the read data, changing the value to h'fe. finally, the cpu writes this value (h'fe) back to p4ddr to complete the bclr instruction. as a result, p4 0 ddr is cleared to 0, making p4 0 an input pin. in addition, p4 7 ddr and p4 6 ddr are set to 1, making p4 7 and p4 6 output pins. the bclr instruction can be used to clear flags in the on-chip registers to 0. in the case of the irq status register (isr), for example, a flag mu st be read as a condition for clearing it, but when using the bclr instruction, if it is known that a flag has been set to 1 in an interrupt-handling routine, for instance, it is not necessa ry to read the fl ag ahead of time. 2. cpu rev.5.00 sep. 12, 2007 page 44 of 764 rej09b0396-0500 2.7 addressing modes and eff ective address calculation 2.7.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructi ons can use all addressing modes except program- counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16, ern)/@(d:24, ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @ ? ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 1 register direct ? rn: the register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2 register indirect ? @ern: the register field of the instru ction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand. 3 register indirect with displacement ? @(d:16, ern) or @(d:24, ern): a 16-bit or 24-bit displacement contained in the inst ruction code is added to the contents of an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. a 16-bit displacement is sign-extended when added. 2. cpu rev.5.00 sep. 12, 2007 page 45 of 764 rej09b0396-0500 4 register indirect with po st-increment or pre-decrement ? @ern+ or @?ern: ? register indirect with post-increment ? @ern+ the register field of the instru ction code specifies an address register (ern) the lower 24 bits of which contain the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. ? register indirect with pre-decrement ? @ ? ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. the result is also stored in the addre ss register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the resulting register value should be even. 5 absolute address ? @aa:8, @aa:16, or @aa:24: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h 'ffff). for a 16-bit absolute address the upper 8 bits are a sign extension. a 24-bit absolute address can acce ss the entire address space. table 2.12 indicates the accessible address ranges. table 2.12 absolute address access ranges absolute address 1-mbyte modes 16-mbyte modes 8 bits (@aa:8) h'fff00 to h'fffff (1048320 to 1048575) h'ffff00 to h'ffffff (16776960 to 16777215) 16 bits (@aa:16) h'00000 to h'07fff, h'f8000 to h'fffff (0 to 32767, 1015808 to 1048575) h'000000 to h'007fff, h'ff8000 to h'ffffff (0 to 32767, 16744448 to 16777215) 24 bits (@aa:24) h'00000 to h'fffff (0 to 1048575) h'000000 to h'ffffff (0 to 16777215) 6 immediate ? #xx:8, #xx:16, or #xx:32: the instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the instruction codes of the adds, subs, inc, and dec instructions contain immediate data implicitly. the instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. the trapa instruction code contains 2-bit immediate data specifying a vector address. 2. cpu rev.5.00 sep. 12, 2007 page 46 of 764 rej09b0396-0500 7 program-counter relative ? @(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit pc contents to generate a 24-bit branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. 8 memory indirect ? @@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byte of the memory operand is ignored, generating a 24-bit branch address. see figure 2.10. the upper bits of the 8-bit absolute address are assume d to be 0 (h'0000), so the address range is 0 to 255 (h'000000 to h'0000ff). note that the first part of this range is also the exception vector area. for further details see section 5, interrupt controller. specified by @aa:8 reserved branch address figure 2.10 memory-indirect branch address specification when a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. the accessed data or instruction code therefore begins at the preceding address. see section 2.5.2, memory data formats. 2.7.2 effective address calculation table 2.13 explains how an effective address is calculated in each addressing mode. in the 1-mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. 2. cpu rev.5.00 sep. 12, 2007 page 47 of 764 rej09b0396-0500 table 2.13 effective address calculation addressing mode and instruction format no. effective address calculation effective address register direct (rn) 1 operand is general register contents op rm rn register indirect (@ern) 2 op r general register contents 31 0 23 0 register indirect with displacement @(d:16, ern)/@(d:24, ern) 3 op r general register contents 31 0 23 0 sign extension disp register indirect with post-increment or pre-decrement 4 general register contents 31 0 23 0 1, 2, or 4 op r general register contents 31 0 23 0 1, 2, or 4 op r register indirect with post-increment @ern+ register indirect with pre-decrement @?ern 1 for a byte operand, 2 for a word operand, 4 for a longword operand 2. cpu rev.5.00 sep. 12, 2007 page 48 of 764 rej09b0396-0500 addressing mode and instru c tion format no. effe c tive address cal c ulation effe c tive address absolute address @aa:8 5 op pro g ram-counter relative @(d:8, pc) or @(d:16, pc) 7 0 23 0 abs 23 0 87 @aa:16 @aa:24 op abs 23 0 16 15 h'ffff si g n extension op 23 0 abs immediate #xx:8, #xx:16, or #xx:32 6 operand is immediate data op disp 23 0 pc contents disp op imm si g n extension 2. cpu rev.5.00 sep. 12, 2007 page 49 of 764 rej09b0396-0500 addressing mode and instru c tion format no. effe c tive address cal c ulation effe c tive address 8 le g end: r, rm, rn: op: disp: imm: abs: re g ister field operation field displacement immediate data absolute address memory indirect @@aa:8 8 op 23 0 abs 23 0 87 h'0000 15 0 abs 16 15 normal mode op 23 0 abs 23 0 87 h'0000 0 abs advanced mode 31 h'00 memory contents memory contents 2. cpu rev.5.00 sep. 12, 2007 page 50 of 764 rej09b0396-0500 2.8 processing states 2.8.1 overview the h8/300h cpu has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-rel eased state. the power-down state includes sleep mode, software standby mode, and hardware stan dby mode. figure 2.11 classifies the processing states. figure 2.13 indicates the state transitions. processin g states pro g ram execution state bus-released state reset state power-down state the cpu executes pro g ram instructions in sequence a transient state in which the cpu executes a hardware sequence (savin g pc and ccr, fetchin g a vector, etc.) in response to a reset, interrupt, or other exception the external bus has been released in response to a bus request si g nal from a bus master other than the cpu the cpu and all on-chip supportin g modules are initialized and halted the cpu is halted to conserve power sleep mode software standby mode hardware standby mode exception-handlin g state figure 2.11 processing states 2. cpu rev.5.00 sep. 12, 2007 page 51 of 764 rej09b0396-0500 2.8.2 program execution state in this state the cpu executes program instructions in normal sequence. 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cp u alters the normal program flow due to a reset, interrupt, or trap instruction. the cpu fetches a starting address from the exception vector table and bran ches to that address. in inte rrupt and trap exception handling the cpu references the stack pointer (er7) a nd saves the program counter and condition code register. types of exception handling and their priority: exception handling is performed for resets, interrupts, and trap instructions. table 2.14 indicates the types of exception handling and their priority. trap instruc tion exceptions are accepted at all tim es in the program execution state. table 2.14 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately when res changes from low to high interrupt end of instruction execution or end of exception handling * when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed note: * interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. figure 2.12 classifies the exception sources. for further details about exception sources, vector numbers, and vector addresses, see section 4, exception handling, and section 5, interrupt controller. 2. cpu rev.5.00 sep. 12, 2007 page 52 of 764 rej09b0396-0500 exception sources reset interrupt trap instruction external interrupts internal interrupts (from on-chip supportin g modules) figure 2.12 classificati on of exception sources bus-released state exception-handlin g state reset state pro g ram execution state sleep mode software standby mode hardware standby mode power-down state bus request end of bus release end of bus release bus request end of exception handlin g exception handlin g source interrupt source sleep instruction with ssby = 0 sleep instruction with ssby = 1 nmi, irq , irq , or irq interrupt stby = hi g h, res = low res = hi g h 01 2 * 1 * 2 notes: 1. 2. from any state except hardware standby mode, a transition to the reset state occurs whenever res g oes low. from any state, a transition to hardware standby mode occurs when stby g oes low. figure 2.13 state transitions 2. cpu rev.5.00 sep. 12, 2007 page 53 of 764 rej09b0396-0500 2.8.4 exception-handling sequences reset exception handling: reset exception handling has the highest priority. the reset state is entered when the res signal goes low. reset exception handling starts after that, when res changes from low to high. when reset exception handling starts the cpu fetches a start address from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during the reset exception-handling sequence and immediately after it ends. interrupt exception handling and trap instruction exception handling: when these exception-handling sequences begin, the cpu references the stack pointer (er7) and pushes the program counter and condition code register on the stack. next, if the ue bit in the system control register (syscr) is set to 1, the cpu sets the i bit in the condition code register to 1. if the ue bit is cleared to 0, the cpu sets both the i bit and the ui bit in the condition code register to 1. then the cpu fetches a start address from the exception vector table and execu tion branches to that address. figure 2.14 shows the stack afte r the exception-handling sequence. sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp (er7) before exception handlin g starts sp (er7) sp+1 sp+2 sp+3 sp+4 after exception handlin g ends stack area ccr pc even address pushed on stack le g end: ccr: sp: condition code re g ister stack pointer notes: 1. 2. pc is the address of the first instruction executed after the return from the exception-handlin g routine. re g isters must be saved and restored by word access or lon g word access, startin g at an even address. figure 2.14 stack structu re after exception handling 2. cpu rev.5.00 sep. 12, 2007 page 54 of 764 rej09b0396-0500 2.8.5 bus-released state in this state the bus is released to a bus master other than the cpu, in response to a bus request. the bus masters other than the cpu are the dma c ontroller, the dram interface, and an external bus master. while the bus is released, the cpu halts except for internal operations. interrupt requests are not accepted. for details see section 6.10, bus arbiter. 2.8.6 reset state when the res input goes low all current processing stops and the cpu enters the reset state. the i bit in the condition code register is set to 1 by a reset. all interrupts are masked in the reset state. reset exception handling starts when the res signal changes from low to high. the reset state can also be entered by a watc hdog timer overflow. for details see section 12, watchdog timer. 2.8.7 power-down state in the power-down state the cpu stops operating to conserve power. there are three modes: sleep mode, software standby mode, and hardware standby mode. sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the ssby bit is cleared to 0 in the system control register (syscr). cpu operations stop immediately after execu tion of the sleep instruction, but the contents of cpu registers are retained. software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit is set to 1 in syscr. the cpu and clock halt and all on-chip supporting modules stop operating. the on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. hardware standby mode: a transition to hardware standby mode is made when the stby input goes low. as in software standby mode, the cpu and all clocks halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. for further information see section 19, power-down state. 2. cpu rev.5.00 sep. 12, 2007 page 55 of 764 rej09b0396-0500 2.9 basic operational timing 2.9.1 overview the h8/300h cpu operates accord ing to the system clock ( ). the interval from one rise of the system clock to the next rise is referred to as a ?state.? a memory cycle or bus cycle consists of two or three states. the cpu uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. access to the external address space can be controlled by the bus controller. 2.9.2 on-chip memory access timing on-chip memory is accessed in two states. the data bus is 16 bits wide, permitting both byte and word access. figure 2.15 shows the on-chip memory access cycle. figure 2. 16 indicates the pin states. t state bus cycle internal address bus internal read si g nal internal data bus (read access) internal write si g nal internal data bus (write access) 1 t state 2 read data address write data figure 2.15 on-chip memory access cycle 2. cpu rev.5.00 sep. 12, 2007 page 56 of 764 rej09b0396-0500 t , , , as 1 t 2 address bus d to d 15 0 rd hwr lwr hi g h address hi g h impedance figure 2.16 pin states dur ing on-chip memory access 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in thr ee states. the data bus is 8 or 16 bits wide, depending on the internal i/o register being accessed. figure 2. 17 shows the on-chip supporting module access timing. figure 2. 18 indicates the pin states. address bus internal read si g nal internal data bus internal write si g nal address internal data bus t state bus cycle 1 t state 2 t state 3 read access write access write data read data figure 2.17 access cycle fo r on-chip supporting modules 2. cpu rev.5.00 sep. 12, 2007 page 57 of 764 rej09b0396-0500 t , , , as 1 t 2 address bus d to d 15 0 rd hwr lwr hi g h hi g h impedance t 3 address figure 2.18 pin states during access to on-chip supporting modules 2.9.4 access to external address space the external address space is divided into eight areas (areas 0 to 7). bus-controller settings determine whether each area is accessed via an 8- bit or 16-bit bus, and whether it is accessed in two or three states. for details see section 6, bus controller. 2. cpu rev.5.00 sep. 12, 2007 page 58 of 764 rej09b0396-0500 3. mcu operating modes rev.5.00 sep. 12, 2007 page 59 of 764 rej09b0396-0500 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8/3006 and h8/3007 have four operating modes (modes 1 to 4) that are selected by the mode pins (md 2 to md 0 ) as indicated in table 3.1. the input at these pins determines the size of the address space and the initial bus mode. table 3.1 operating mode selection description operating mode pins initial bus on-chip mode md 2 md 1 md 0 address space mode * 1 ram ? 0 0 0 setting prohibited setting prohibited setting prohibited mode 1 0 0 1 1 mbyte 8 bits enabled * 2 mode 2 0 1 0 1 mbyte 16 bits enabled * 2 mode 3 0 1 1 16 mbytes 8 bits enabled * 2 mode 4 1 0 0 16 mbytes 16 bits enabled * 2 ? 1 0 1 ? ? ? ? 1 1 0 ? ? ? ? 1 1 1 ? ? ? notes: 1. in modes 1 to 4, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings made in the area bus width control register (abwcr). for details see section 6, bus controller. 2. if the rame bit in syscr is cleared to 0, these addresses become external addresses. for the address space size there are two choices: 1 mbyte, or 16 mbyte.the external data bus is either 8 or 16 bits wide depending on abwcr sett ings. if 8-bit access is selected for all areas, 8- bit bus mode is used. for details see section 6, bus controller. modes 1 and 2 support a maximum address space of 1 mbyte. modes 3 and 4 support a maximum address space of 16 mbytes. the h8/3006 and h8/3007 can be used only in modes 1 to 4. the inputs at the mode pins must select one of these four modes. the inputs at the mode pins must not be changed during operation. 3. mcu operating modes rev.5.00 sep. 12, 2007 page 60 of 764 rej09b0396-0500 when changing the mode, the chip must be placed in the reset state before the mode pin inputs are changed. 3.1.2 register configuration the h8/3006 and h8/3007 have a mode control register (mdcr) that indicates the inputs at the mode pins (md 2 to md 0 ), and a system control register (syscr). table 3.2 summarizes these registers. table 3.2 registers address * name abbreviation r/w initial value h'ee011 mode control register mdcr r undetermined h'ee012 system control register syscr r/w h'09 note: * lower 20 bits of the address in advanced mode. 3.2 mode control register (mdcr) mdcr is an 8-bit read-only register that indicates the current operating mode of the h8/3006 and h8/3007. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 ? r * 2 mds2 ? r 1 mds1 ? r ** reserved bits mode sele c t 2 to 0 bits indicatin g the current operatin g mode note: determined by pins md to md . * 20 bits 7 and 6 ? reserved: these bits can not be modified and are always read as 1. bits 5 to 3 ? reserved: these bits can not be modified and are always read as 0. bits 2 to 0 ? mode select 2 to 0 (mds2 to mds0): these bits indicate the logic levels at pins md 2 to md 0 (the current operating mode). mds2 to mds0 correspond to md 2 to md 0 . mds2 to mds0 are read-only bits. the mode pin (md 2 to md 0 ) levels are latched into these bits when mdcr is read. 3. mcu operating modes rev.5.00 sep. 12, 2007 page 61 of 764 rej09b0396-0500 3.3 system control register (syscr) syscr is an 8-bit register that controls the operation of the h8/3006 and h8/3007. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby enables transition to software standby mode user bit enable selects whether to use the ui bit in ccr as a user bit or an interrupt mask bit nmi edge select selects the valid edge of the nmi input ram enable enables or disables on-chip ram standby timer select 2 to 0 these bits select the waiting time at recovery from software standby mode selects the output state of the address bus and bus control signals in software standby mode software standby output port enable bit 7 ? software standby (ssby): enables transition to software standby mode. (for further information about software standby mode see section 19, power-down state.) when software standby mode is exited by an extern al interrupt and a transition is made to normal operation, this bit remains set to 1. to clear this bit, write 0. bit 7 ssby description 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode 3. mcu operating modes rev.5.00 sep. 12, 2007 page 62 of 764 rej09b0396-0500 bits 6 to 4 ? standby timer select 2 to 0 (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. when using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. for further information about wa iting time selection, see secti on 19.4.3, selection of waiting time for exit from software standby mode. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 waiting time = 8,192 states (initial value) 1 waiting time = 16,384 states 1 0 waiting time = 32,768 states 1 waiting time = 65,536 states 1 0 0 waiting time = 131,072 states 1 waiting time = 262,144 states 1 0 waiting time = 1,024 states 1 illegal setting bit 3 ? user bit enable (ue): selects whether to use the ui bit in the condition code register as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as an interrupt mask bit 1 ui bit in ccr is used as a user bit (initial value) bit 2 ? nmi edge select (nmieg): selects the valid edge of the nmi input. bit 2 nmieg description 0 an interrupt is requested at the falling edge of nmi (initial value) 1 an interrupt is requested at the rising edge of nmi 3. mcu operating modes rev.5.00 sep. 12, 2007 page 63 of 764 rej09b0396-0500 bit 1 ? software standby output port enable (ssoe): specifies whether the address bus and bus control signals ( cs 0 to cs 7 , as , rd , hwr , lwr , ucas , lcas , and rfsh ) are kept as outputs or fixed hi gh, or placed in the high-impedan ce state in software standby mode. bit 1 ssoe description 0 in software standby mode, the address bus and bus control signals are all high- impedance (initial value) 1 in software standby mode, the address bus retains its output state and bus control signals are fixed high bit 0 ? ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized by the rising edge of the res signal. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 3.4 operating mode descriptions 3.4.1 mode 1 a maximum 1-mbyte address space can be accessed. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. if at least one area is designated for 16-bit access in abwcr, the bus mode switches to 16 bits. 3.4.2 mode 2 a maximum 1-mbyte address space can be accessed. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. if all areas are designated for 8-bit access in abwcr, the bus mode switches to 8 bits. 3. mcu operating modes rev.5.00 sep. 12, 2007 page 64 of 764 rej09b0396-0500 3.4.3 mode 3 part of port a function as address pins a 23 to a 20 , permitting access to a maximum 16-mbyte address space. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. if at least one area is designated for 16-bit access in ab wcr, the bus mode switches to 16 bits. a 23 to a 21 are valid when 0 is written in bits 7 to 5 of the bus release control register (brcr). (in this mode a 20 is always used for address output.) 3.4.4 mode 4 part of port a function as address pins a 23 to a 20 , permitting access to a maximum 16-mbyte address space. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. if all areas are designated for 8-bit access in abwc r, the bus mode switches to 8 bits. a 23 to a 21 are valid when 0 is written in bits 7 to 5 of brcr. (in this mode a 20 is always used for address output.) 3.5 pin functions in each operating mode the pin functions of port 4 and port a vary depending on the operating mode. table 3.3 indicates their functions in each operating mode. table 3.3 pin functions in each mode port mode 1 mode 2 mode 3 mode 4 port 4 p4 7 to p4 0 * 1 d 7 to d 0 * 1 p4 7 to p4 0 * 1 d 7 to d 0 * 1 port a pa 7 to pa 4 pa 7 to pa 4 pa 6 to pa 4 , a 20 * 2 pa 6 to pa 4 , a 20 * 2 notes: 1. initial state. the bus mode can be switched by settings in abwcr. these pins function as p4 7 to p4 0 in 8-bit bus mode, and as d 7 to d 0 in 16-bit bus mode. 2. initial state. a 20 is always an address output pin. pa 6 to pa 4 are switched over to a 23 to a 21 output by writing 0 in bits 7 to 5 of brcr. 3. mcu operating modes rev.5.00 sep. 12, 2007 page 65 of 764 rej09b0396-0500 3.6 memory map in each operating mode figures 3.1 and 3.2 show a memory maps of the h8/3006 and h8/3007. the address space is divided into eight areas. the initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. the address locations of the on-chip ram and internal i/o registers differ between the 1-mbyte modes (modes 1, 2), and the 16-mbyte modes (modes 3, 4). the address range specifiable by the cpu in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. 3.6.1 note on reserved areas the memory map of the h8/3006 and h8/3007 include s reserved areas to which read/write access is prohibited. note that normal operation is not guaranteed if the following reserved areas are accessed. the internal i/o register space of the h8/3006 and h8/3007 includes a reserved area to which access is prohibited. for details, see appendix b, internal i/o registers. 3. mcu operating modes rev.5.00 sep. 12, 2007 page 66 of 764 rej09b0396-0500 h'00000 h'000ff h'07fff memory-indirect branch addresses 16-bit absolute addresses modes 1 and 2 (1 mbyte) h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space external address space vector area on-chip ram * on-chip ram * 8-bit absolute addresses 16-bit absolute addresses h'f8000 h'fef1f h'fef20 h'fff00 h'fff1f h'fff20 h'fffe9 h'fffea h'fffff modes 3 and 4 (16 mbytes) h'000000 h'0000ff h'007fff memory-indirect branch addresses 16-bit absolute addresses h'1fffff h'200000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space vector area external address space 8-bit absolute addresses 16-bit absolute addresses h'ff8000 h'ffef1f h'ffef20 h'ffff1f h'ffff20 h'ffff00 h'ffffe9 h'ffffea h'ffffff h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff note: * external addresses can be accessed by disablin g on-chip ram. internal i/o re g isters (1) internal i/o re g isters (1) internal i/o re g isters (2) internal i/o re g isters (2) external address space h'ee000 h'ee0ff external address space figure 3.1 h8/3007 memory map in each operating mode 3. mcu operating modes rev.5.00 sep. 12, 2007 page 67 of 764 rej09b0396-0500 h'00000 h'000ff h'07fff memory-indirect branch addresses 16-bit absolute addresses modes 1 and 2 (1 mbyte) h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space external address space external address space vector area on-chip ram * on-chip ram * 8-bit absolute addresses 16-bit absolute addresses h'f8000 h'ff71f h'ff720 h'fff00 h'fff1f h'fff20 h'fffe9 h'fffea h'fffff modes 3 and 4 (16 mbytes) h'000000 h'0000ff h'007fff memory-indirect branch addresses 16-bit absolute addresses h'1fffff h'200000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 external address space vector area external address space 8-bit absolute addresses 16-bit absolute addresses h'ff8000 h'fff71f h'fff720 h'ffff1f h'ffff20 h'ffff00 h'ffffe9 h'ffffea h'ffffff h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff internal i/o re g isters (1) internal i/o re g isters (1) internal i/o re g isters (2) internal i/o re g isters (2) external address space h'ee000 h'ee0ff note: * external addresses can be accessed by disablin g on-chip ram. figure 3.2 h8/3006 memory map in each operating mode 3. mcu operating modes rev.5.00 sep. 12, 2007 page 68 of 764 rej09b0396-0500 4. exception handling rev.5.00 sep. 12, 2007 page 69 of 764 rej09b0396-0500 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in pr iority order. trap in struction exceptions are accepted at all times in the program execution state. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin interrupt interrupt requests are handled when execution of the current instruction or handling of the current exception is completed low trap instruction (trapa) started by execution of a trap instruction (trapa) 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows. 1. the program counter (pc) and condition code register (ccr) are pushed onto the stack. 2. the ccr interrupt mask bit is set to 1. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. note: for a reset exception, steps 2 and 3 above are carried out. 4. exception handling rev.5.00 sep. 12, 2007 page 70 of 764 rej09b0396-0500 4.1.3 exception vector table the exception sources are classified as shown in figure 4.1. different vectors are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. exception sources ? reset ? interrupts ? trap instruction external interrupts: internal interrupts: nmi, irq to irq 36 interrupts from on-chip supportin g modules 0 5 figure 4.1 exception sources 4. exception handling rev.5.00 sep. 12, 2007 page 71 of 764 rej09b0396-0500 table 4.2 exception vector table vector address * 1 exception source vector number advanced mode normal mode * 3 reset 0 h'0000 to h'0003 h'0000 to h'0001 reserved for system use 1 h'0004 to h'0007 h'0002 to h'0003 2 h'0008 to h'000b h'0004 to h'0005 3 h'000c to h'000f h'0006 to h'0007 4 h'0010 to h'0013 h'0008 to h'0009 5 h'0014 to h'0017 h'000a to h'000b 6 h'0018 to h'001b h'000c to h'000d external interrupt (nmi) 7 h'001c to h'001f h'000e to h'000f trap instruction (4 sources) 8 h'0020 to h'0023 h'0010 to h'0011 9 h'0024 to h'0027 h'0012 to h'0013 10 h'0028 to h'002b h'0014 to h'0015 11 h'002c to h'002f h'0016 to h'0017 external interrupt irq 0 12 h'0030 to h'0033 h'0018 to h'0019 external interrupt irq 1 13 h'0034 to h'0037 h'001a to h'001b external interrupt irq 2 14 h'0038 to h'003b h'001c to h'001d external interrupt irq 3 15 h'003c to h'003f h'001e to h'001f external interrupt irq 4 16 h'0040 to h'0043 h'0020 to h'0021 external interrupt irq 5 17 h'0044 to h'0047 h'0022 to h'0023 reserved for system use 18 h'0048 to h'004b h'0024 to h'0025 19 h'004c to h'004f h'0026 to h'0027 internal interrupts * 2 20 to 63 h'0050 to h'0053 to h'00fc to h'00ff h'0028 to h'0029 to h'007e to h'007f notes: 1. lower 16 bits of the address. 2. for the internal interrupt vectors, see section 5.3.3, interrupt vector table. 3. normal mode is not available in the h8/3006 and h8/3007. 4. exception handling rev.5.00 sep. 12, 2007 page 72 of 764 rej09b0396-0500 4.2 reset 4.2.1 overview a reset is the highest-priority exception. when the res pin goes low, all processing halts and the chip enters the reset state. a reset initializes the internal state of the cpu and the registers of the on-chip supporting modules. reset exception handling begins when the res pin changes from low to high. the chip can also be reset by overflow of the watchdog timer. for details see section 12, watchdog timer. 4.2.2 reset sequence the chip enters the reset state when the res pin goes low. to ensure that the chip is properly reset, hold the res pin low for at last 20 ms at power-up. to reset the chip during operation, hold the res pin low for at least 10 system clock ( ) cycles. see appendix d.2, pin states at reset, for the states of the pins in the reset state. when the res pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows. ? the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit is set to 1 in ccr. ? the contents of the reset vector address (h'0000 to h'0003) are read, and program execution starts from the address indicat ed in the vector address. figure 4.2 shows the reset sequence in modes 1 and 3. figure 4.3 shows the reset sequence in modes 2 and 4. 4. exception handling rev.5.00 sep. 12, 2007 page 73 of 764 rej09b0396-0500 address bus res rd hwr d to d 15 8 vector fetch internal processing prefetch of first program instruction (1), (3), (5), (7) (2), (4), (6), (8) (9) (10) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. address of reset vector: (1) = h'000000, (3) = h'000001, (5) = h'000002, (7) = h'000003 start address (contents of reset exception handling vector address) start address first instruction of program high (1) (3) (5) (7) (9) (2) (4) (6) (8) (10) lwr , figure 4.2 reset sequence (modes 1 and 3) 4. exception handling rev.5.00 sep. 12, 2007 page 74 of 764 rej09b0396-0500 address bus res rd hwr d to d 15 0 vector fetch internal processin g prefetch of first pro g ram instruction (1), (3) (2), (4) (5) (6) note: after a reset, the wait-state controller inserts three wait states in every bus cycle. hi g h lwr , address of reset vector: (1) = h'000000, (3) = h'000002 start address (contents of reset exception handlin g vector address) start address first instruction of pro g ram (2) (4) (3) (1) (5) (6) figure 4.3 reset sequence (modes 2 and 4) 4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immedi ately after a reset. the first instruction of the program is always executed immediatel y after the reset state ends. this instruction should initialize the stack pointer (example: mov.l #xx:32, sp). 4. exception handling rev.5.00 sep. 12, 2007 page 75 of 764 rej09b0396-0500 4.3 interrupts interrupt exception handling can be requested by seven external sources (nmi, irq 0 to irq 5 ), and 36 internal sources in the on-chip supporting modules. figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. the on-chip supporting modules that can request interrupts are the watchdog timer (wdt), dram interface, 16-bit timer, 8-bit timer, dma controller (dmac), serial communication interface (sci), and a/d converter. each inte rrupt source has a separate vector address. nmi is the highest-priority interrupt and is al ways accepted. interrupts are controlled by the interrupt controller. the interrupt controller can assign interrupts other than nmi to two priority levels, and arbitrate between simultaneous interrupts. interrupt priorities are assigned in interrupt priority registers a and b (ipra and iprb) in the interrupt controller. for details on interrupts see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq to irq (6) wdt * 1 (1) dram interface * 2 (1) 16-bit timer (9) 8-bit timer (8) dmac (4) sci (12) a/d converter (1) notes: numbers in parentheses are the number of interrupt sources. 1. 2. when the watchdo g timer is used as an interval timer, it g enerates an interrupt request at every counter overflow. when the dram interface is used as an interval timer, it g enerates an interrupt request at compare match. 0 5 figure 4.4 interrupt sou rces and number of interrupts 4. exception handling rev.5.00 sep. 12, 2007 page 76 of 764 rej09b0396-0500 4.4 trap instruction trap instruction exception handling starts when a trapa instruction is executed. if the ue bit is set to 1 in the system control register (syscr), the exception handling sequence sets the i bit to 1 in ccr. if the ue bit is 0, the i and ui bits are both set to 1. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. 4.5 stack status after exception handling figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp (er7) sp (er7) sp+1 sp+2 sp+3 sp+4 before exception handlin g after exception handlin g stack area ccr pc e pc h pc l even address pushed on stack le g end: pc e : pc h : pc l : ccr: sp: notes: 1. pc indicates the address of the first instruction that will be executed after return. 2. re g isters must be saved in word or lon g word size at even addresses. bits 23 to 16 of pro g ram counter (pc) bits 15 to 8 of pro g ram counter (pc) bits 7 to 0 of pro g ram counter (pc) condition code re g ister stack pointer figure 4.5 stack after completion of exception handling 4. exception handling rev.5.00 sep. 12, 2007 page 77 of 764 rej09b0396-0500 4.6 notes on stack usage when accessing word data or longword data, the h8 /3006 and h8/3007 regard the lowest address bit as 0. the stack should always be accessed by word access or longword access, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (mov.w rn, @?sp) push.l ern (mov.l ern, @?sp) use the following instructions to restore registers: pop.w rn (mov.w @sp+, rn) pop.l ern (mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.6 shows an example of what happens when the sp value is odd. trapa instruction executed ccr le g end: ccr: pc: r1l: sp: sp pc r1l pc sp sp mov. b r1l, @-er7 sp set to h'fffeff data saved above sp ccr contents lost condition code re g ister pro g ram counter general re g ister r1l stack pointer note: the dia g ram illustrates modes 3 and 4. h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff figure 4.6 operation when sp value is odd 4. exception handling rev.5.00 sep. 12, 2007 page 78 of 764 rej09b0396-0500 5. interrupt controller rev.5.00 sep. 12, 2007 page 79 of 764 rej09b0396-0500 section 5 interrupt controller 5.1 overview 5.1.1 features the interrupt controller has the following features: ? interrupt priority registers (iprs) for setting interrupt priorities interrupts other than nmi can be assigned to two priority levels on a module-by-module basis in interrupt priority registers a and b (ipra and iprb). ? three-level enable/disable state setting possible by means of the i and ui bits in the cpu's condition code register (ccr) and the ue bit in the system control register (syscr) ? seven external interrupt pins nmi has the highest priority and is always accepted; either the rising or falling edge can be selected. for each of irq 0 to irq 5 , sensing of the falling edge or level sensing can be selected independently. 5. interrupt controller rev.5.00 sep. 12, 2007 page 80 of 764 rej09b0396-0500 5.1.2 block diagram figure 5.1 shows a block diagram of the interrupt controller. iscr ier ipra, iprb . . . ovf tme tei teie . . . . . . . cpu ccr i ui ue syscr iscr: ier: isr: ipra: iprb: syscr: nmi input irq input irq input section isr interrupt controller priority decision lo g ic interrupt request vector number irq sense control re g ister irq enable re g ister irq status re g ister interrupt priority re g ister a interrupt priority re g ister b system control re g ister le g end: figure 5.1 interrupt controller block diagram 5. interrupt controller rev.5.00 sep. 12, 2007 page 81 of 764 rej09b0396-0500 5.1.3 pin configuration table 5.1 lists the interrupt pins. table 5.1 interrupt pins name abbreviation i/o function nonmaskable interrupt nmi input nonmaskable interrupt, rising edge or falling edge selectable external interrupt request 5 to 0 irq 5 to irq 0 input maskable interrupts, falling edge or level sensing selectable 5.1.4 register configuration table 5.2 lists the registers of the interrupt controller. table 5.2 interrupt controller registers address * 1 name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 h'ee014 irq sense control register iscr r/w h'00 h'ee015 irq enable register ier r/w h'00 h'ee016 irq status register isr r/(w) * 2 h'00 h'ee018 interrupt priority register a ipra r/w h'00 h'ee019 interrupt priority register b iprb r/w h'00 notes: 1. lower 20 bits of the address in advanced mode. 2. only 0 can be written, to clear flags. 5. interrupt controller rev.5.00 sep. 12, 2007 page 82 of 764 rej09b0396-0500 5.2 register descriptions 5.2.1 system control register (syscr) syscr is an 8-bit readable/writable register that controls software standby mode, selects the action of the ui bit in ccr, selects the nmi edge, and enables or disables the on-chip ram. only bits 3 and 2 are described here. for the other bits, see section 3.3, system control register (syscr). syscr is initialized to h'09 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby standby timer sele c t 2 to 0 user bit enable selects whether to use the ui bit in ccr as a user bit or interrupt mask bit nmi edge sele c t selects the nmi input ed g e software standby output port enable ram enable bit 3 ? user bit enable (ue): selects whether to use the ui bit in ccr as a user bit or an interrupt mask bit. bit 3 ue description 0 ui bit in ccr is used as interrupt mask bit 1 ui bit in ccr is used as user bit (initial value) 5. interrupt controller rev.5.00 sep. 12, 2007 page 83 of 764 rej09b0396-0500 bit 2 ? nmi edge select (nmieg): selects the nmi input edge. bit 2 nmieg description 0 interrupt is requested at falling edge of nmi input (initial value) 1 interrupt is requested at rising edge of nmi input 5.2.2 interrupt priority registers a and b (ipra, iprb) ipra and iprb are 8-bit readable/writable registers that control interrupt priority. 5. interrupt controller rev.5.00 sep. 12, 2007 page 84 of 764 rej09b0396-0500 interrupt priority register a (ipra): ipra is an 8-bit readable/writable register in which interrupt priority levels can be set. bit initial value read/write 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 0 ipra0 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w priority level a7 selects the priority level of irq interrupt requests priority level a3 selects the priority level of wdt, dram interface, and a/d converter interrupt requests priority level a2 selects the priority level of 16-bit timer channel 0 interrupt requests priority level a1 selects the priority level of 16-bit timer channel 1 interrupt requests priority level a0 selects the priority level of 16-bit timer channel 2 interrupt requests selects the priority level of irq interrupt requests priority level a6 selects the priority level of irq and irq interrupt requests priority level a5 selects the priority level of irq and irq interrupt requests priority level a4 0 1 23 45 ipra is initialized to h'00 by a reset and in hardware standby mode. 5. interrupt controller rev.5.00 sep. 12, 2007 page 85 of 764 rej09b0396-0500 bit 7 ? priority level a7 (ipra7): selects the priority level of irq 0 interrupt requests. bit 7 ipra7 description 0 irq 0 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 0 interrupt requests have priority level 1 (high priority) bit 6 ? priority level a6 (ipra6): selects the priority level of irq 1 interrupt requests. bit 6 ipra6 description 0 irq 1 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 1 interrupt requests have priority level 1 (high priority) bit 5 ? priority level a5 (ipra5): selects the priority level of irq 2 and irq 3 interrupt requests. bit 5 ipra5 description 0 irq 2 and irq 3 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 2 and irq 3 interrupt requests have priority level 1 (high priority) bit 4 ? priority level a4 (ipra4): selects the priority level of irq 4 and irq 5 interrupt requests. bit 4 ipra4 description 0 irq 4 and irq 5 interrupt requests have priority level 0 (low priority) (initial value) 1 irq 4 and irq 5 interrupt requests have priority level 1 (high priority) bit 3 ? priority level a3 (ipra3): selects the priority level of wdt, dram interface, and a/d converter interrupt requests. bit 3 ipra3 description 0 wdt, dram interface, and a/d converter interrupt requests have priority level 0 (low priority) (initial value) 1 wdt, dram interface, and a/d converter interrupt requests have priority level 1 (high priority) 5. interrupt controller rev.5.00 sep. 12, 2007 page 86 of 764 rej09b0396-0500 bit 2 ? priority level a2 (ipra2): selects the priority level of 16-bit timer channel 0 interrupt requests. bit 2 ipra2 description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) bit 1 ? priority level a1 (ipra1): selects the priority level of 16-bit timer channel 1 interrupt requests. bit 1 ipra1 description 0 16-bit timer channel 1 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 1 interrupt requests have priority level 1 (high priority) bit 0 ? priority level a0 (ipra0): selects the priority level of 16-bit timer channel 2 interrupt requests. bit 0 ipra0 description 0 16-bit timer channel 2 interrupt requests have priority level 0 (low priority) (initial value) 1 16-bit timer channel 2 interrupt requests have priority level 1 (high priority) 5. interrupt controller rev.5.00 sep. 12, 2007 page 87 of 764 rej09b0396-0500 interrupt priority register b (iprb): iprb is an 8-bit readable/writable register in which interrupt priority levels can be set. bit initial value read/write 7 iprb7 0 r/w 6 iprb6 0 r/w 5 iprb5 0 r/w 4 ? 0 r/w 3 iprb3 0 r/w 0 ? 0 r/w 2 iprb2 0 r/w 1 iprb1 0 r/w priority level b7 selects the priority level of 8-bit timer channel 0, 1 interrupt requests priority level b3 selects the priority level of sci channel 0 interrupt requests priority level b2 selects the priority level of sci channel 1 interrupt requests priority level b1 selects the priority level of sci channel 2 interrupt requests reserved bit selects the priority level of 8-bit timer channel 2, 3 interrupt requests priority level b6 selects the priority level of dmac interrupt requests (channels 0 and 1) priority level b5 reserved bit iprb is initialized to h'00 by a reset and in hardware standby mode. 5. interrupt controller rev.5.00 sep. 12, 2007 page 88 of 764 rej09b0396-0500 bit 7 ? priority level b7 (iprb7): selects the priority level of 8-bit timer channel 0, 1 interrupt requests. bit 7 iprb7 description 0 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(initial value) 1 8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority) bit 6 ? priority level b6 (iprb6): selects the priority level of 8-bit timer channel 2, 3 interrupt requests. bit 6 iprb6 description 0 8-bit timer channel 2, 3 interrupt requests have priority level 0 (low priority)(initial value) 1 8-bit timer channel 2, 3 interrupt requests have priority level 1 (high priority) bit 5 ? priority level b5 (iprb5): selects the priority level of dmac interrupt requests (channels 0 and 1). bit 5 iprb5 description 0 dmac interrupt requests (channels 0 and 1) have priority level 0 (initial value) (low priority) 1 dmac interrupt requests (channels 0 and 1) have priority level 1 (high priority) bit 4 ? reserved: this bit can be written and read, but it does not affect interrupt priority. bit 3 ? priority level b3 (iprb3): selects the priority level of sci channel 0 interrupt requests. bit 3 iprb3 description 0 sci channel 0 interrupt requests have priority level 0 (low priority) (initial value) 1 sci channel 0 interrupt requests have priority level 1 (high priority) 5. interrupt controller rev.5.00 sep. 12, 2007 page 89 of 764 rej09b0396-0500 bit 2 ? priority level b2 (iprb2): selects the priority level of sci channel 1 interrupt requests. bit 2 iprb2 description 0 sci channel 1 interrupt requests have priority level 0 (low priority) (initial value) 1 sci channel 1 interrupt requests have priority level 1 (high priority) bit 1 ? priority level b1 (iprb1): selects the priority level of sci channel 2 interrupt requests. bit 1 iprb1 description 0 sci channel 2 interrupt requests have priority level 0 (low priority) (initial value) 1 sci channel 2 interrupt requests have priority level 1 (high priority) bit 0 ? reserved: this bit can be written and read, but it does not affect interrupt priority. 5.2.3 irq status register (isr) isr is an 8-bit readable/writable regist er that indicates the status of irq 0 to irq 5 interrupt requests. bit initial value read/write 7 ? 0 ? these bits indicate irq to irq interrupt request status note: only 0 can be written, to clear fla g s. * 6 ? 0 ? 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f 0 r/(w) * 50 irq to irq flags 50 reserved bits isr is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6 ? reserved: these bits can not be modified and are always read as 0. 5. interrupt controller rev.5.00 sep. 12, 2007 page 90 of 764 rej09b0396-0500 bits 5 to 0 ? irq 5 to irq 0 flags (irq5f to irq0f): these bits indicate the status of irq 5 to irq 0 interrupt requests. bits 5 to 0 irq5f to irq0f description 0 [clearing conditions] (initial value) ? 0 is written in irqnf after reading the irqnf flag when irqnf = 1. ? irqnsc = 0, irqn input is high, and interrupt exception handling is carried out. ? irqnsc = 1 and irqn interrupt exception handling is carried out. 1 [setting conditions] ? irqnsc = 0 and irqn input is low. ? irqnsc = 1 and irqn input changes from high to low. note: n = 5 to 0 5.2.4 irq enable register (ier) ier is an 8-bit readable/writable regi ster that enables or disables irq 0 to irq 5 interrupt requests. bit initial value read/write 7 ? 0 r/w these bits enable or disable irq to irq interrupts 6 ? 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e 0 r/w 50 irq to irq enable 50 reserved bits ier is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6 ? reserved: these bits can be written and read, but they do not enable or disable interrupts. bits 5 to 0 ? irq 5 to irq 0 enable (irq5e to irq0e): these bits enable or disable irq 5 to irq 0 interrupts. bits 5 to 0 irq5e to irq0e description 0 irq 5 to irq 0 interrupts are disabled (initial value) 1 irq 5 to irq 0 interrupts are enabled 5. interrupt controller rev.5.00 sep. 12, 2007 page 91 of 764 rej09b0396-0500 5.2.5 irq sense control register (iscr) iscr is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins irq 5 to irq 0 . bit initial value read/write 7 ? 0 r/w these bits select level sensin g or fallin g -ed g e sensin g for irq to irq interrupts 6 ? 0 r/w 5 irq5sc 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc 0 r/w 50 irq to irq sense c ontrol 50 reserved bits iscr is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 6 ? reserved: these bits can be written and read, but they do not select level or falling-edge sensing. bits 5 to 0 ? irq 5 to irq 0 sense control (irq5sc to irq0sc): these bits select whether interrupts irq 5 to irq 0 are requested by level sensing of pins irq 5 to irq 0 , or by falling-edge sensing. bits 5 to 0 irq5sc to irq0sc description 0 interrupts are requested when irq 5 to irq 0 inputs are low (initial value) 1 interrupts are requested by falling-edge input at irq 5 to irq 0 5. interrupt controller rev.5.00 sep. 12, 2007 page 92 of 764 rej09b0396-0500 5.3 interrupt sources the interrupt sources include external interrupts (nmi, irq 0 to irq 5 ) and 36 internal interrupts. 5.3.1 external interrupts there are seven external interrupts: nmi, and irq 0 to irq 5 . of these, nmi, irq 0 , irq 1 , and irq 2 can be used to exit software standby mode. nmi: nmi is the highest-priority interrupt and is always accepted, regardless of the states of the i and ui bits in ccr. the nmieg bit in syscr selects whether an interrupt is requested by the rising or falling edge of the input at the nmi pin. nmi interrupt exception handling has vector number 7. irq 0 to irq 5 interrupts: these interrupts are requested by input signals at pins irq 0 to irq 5 . the irq 0 to irq 5 interrupts have the following features. ? iscr settings can select whether an interrupt is requested by the low level of the input at pins irq 0 to irq 5 , or by the falling edge. ? ier settings can enable or disable the irq 0 to irq 5 interrupts. interrupt priority levels can be assigned by four bits in ipra (ipra7 to ipra4). ? the status of irq 0 to irq 5 interrupt requests is indicated in isr. the isr flags can be cleared to 0 by software. figure 5.2 shows a block diagram of interrupts irq 0 to irq 5 . input ed g e/level sense circuit irqnsc irqnf s r q irqne irqn interrupt request clear si g nal irqn note: n = 5 to 0 figure 5.2 block diagram of interrupts irq 0 to irq 5 5. interrupt controller rev.5.00 sep. 12, 2007 page 93 of 764 rej09b0396-0500 figure 5.3 shows the timing of the setting of the interrupt flags (irqnf). irqn note: n = 5 to 0 irqnf input pin figure 5.3 timing of setting of irqnf interrupts irq 0 to irq 5 have vector numbers 12 to 17. these interrupts are detected regardless of whether the corresponding pin is set for input or output. when using a pin for external interrupt input, clear its ddr bit to 0 and do not use the pin for chip select output, refresh output, sci input/output, or a/d external trigger input. 5.3.2 internal interrupts thirty-six internal interrupts are requested from the on-chip supporting modules. ? each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. ? interrupt priority levels can be assigned in ipra and iprb. ? 16-bit timer, sci, and a/d converter interrupt requests can activate the dmac, in which case no interrupt request is sent to the interrupt controller, and the i and ui bits are disregarded. 5.3.3 interrupt vector table table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. in the default priority order, smaller vector numbers have higher priority. the priority of interrupts other than nmi can be changed in ipra and iprb. the priority order after a reset is the default order shown in table 5.3. 5. interrupt controller rev.5.00 sep. 12, 2007 page 94 of 764 rej09b0396-0500 table 5.3 interrupt sources, v ector addresses, and priority vector address * interrupt source origin vector number advanced mode ipr priority nmi external 7 h'001c to h'001f ? high irq 0 pins 12 h'0030 to h'0033 ipra7 irq 1 13 h'0034 to h0037 ipra6 irq 2 irq 3 14 15 h'0038 to h'003b h'003c to h'003f ipra5 irq 4 irq 5 16 17 h'0040 to h'0043 h'0044 to h'0047 ipra4 reserved ? 18 19 h'0048 to h'004b h'004c to h'004f wovi (interval timer) watchdog timer 20 h'0050 to h'0053 ipra3 cmi (compare match) dram interface 21 h'0054 to h'0057 reserved ? 22 h'0058 to h'005b adi (a/d end) a/d 23 h'005e to h'005f imia0 (compare match/ input capture a0) imib0 (compare match/ input capture b0) ovi0 (overflow 0) 16-bit timer channel 0 24 25 26 h'0060 to h'0063 h'0064 to h'0067 h'0068 to h'006b ipra2 reserved ? 27 h'006c to h'006f imia1 (compare match/ inputcapture a1) imib1 (compare match/ input capture b1) ovi1 (overflow 1) 16-bit timer channel 1 28 29 30 h'0070 to h'0073 h'0074 to h'0077 h'0078 to h'007b ipra1 reserved ? 31 h'007c to h'007f low 5. interrupt controller rev.5.00 sep. 12, 2007 page 95 of 764 rej09b0396-0500 vector address * interrupt source origin vector number advanced mode ipr priority imia2 (compare match/ input capture a2) imib2 (compare match/ input capture b2) ovi2 (overflow 2) 16-bit timer channel 2 32 33 34 h'0080 to h'0083 h'0084 to h'0087 h'0088 to h'008b ipra0 high reserved ? 35 h'008c to h'008f cmia0 (compare match a0) cmib0 (compare match b0) cmia1/cmib1 (compare match a1/b1) tovi0/tovi1 (overflow 0/1) 8-bit timer channel 0/1 36 37 38 39 h'0090 to h'0093 h'0094 to h'0097 h'0098 to h'009b h'009c to h'009f iprb7 cmia2 (compare match a2) cmib2 (compare match b2) cmia3/cmib3 (compare match a3/b3) tovi2/tovi3 (overflow 2/3) 8-bit timer channel 2/3 40 41 42 43 h'00a0 to h'00a3 h'00a4 to h'00a7 h'00a8 to h'00ab h'00ac to h'00af iprb6 dend0a dend0b dend1a dend1b dmac 44 45 46 47 h'00b0 to h'00b3 h'00b4 to h'00b7 h'00b8 to h'00bb h'00bc to h'00bf iprb5 reserved ? 48 49 50 51 h'00c0 to h'00c3 h'00c4 to h'00c7 h'00c8 to h'00cb h'00cc to h'00cf ? low 5. interrupt controller rev.5.00 sep. 12, 2007 page 96 of 764 rej09b0396-0500 vector address * interrupt source origin vector number advanced mode ipr priority eri0 (receive error 0) rxi0 (receive data full 0) txi0 (transmit data empty 0) tei0 (transmit end 0) sci channel 0 52 53 54 55 h'00d0 to h'00d3 h'00d4 to h'00d7 h'00d8 to h'00db h'00dc to h'00df iprb3 high eri1 (receive error 1) rxi1 (receive data full 1) txi1 (transmit data empty 1) tei1 (transmit end 1) sci channel 1 56 57 58 59 h'00e0 to h'00e3 h'00e4 to h'00e7 h'00e8 to h'00eb h'00ec to h'00ef iprb2 eri2 (receive error 2) rxi2 (receive data full 2) txi2 (transmit data empty 2) tei2 (transmit end 2) sci channel 2 60 61 62 63 h'00f0 to h'00f3 h'00f4 to h'00f7 h'00f8 to h'00fb h'00fc to h'00ff iprb1 low note: * lower 16 bits of the address. 5. interrupt controller rev.5.00 sep. 12, 2007 page 97 of 764 rej09b0396-0500 5.4 interrupt operation 5.4.1 interrupt handling process the h8/3006 and h8/3007 handle interrupts differ ently depending on the setting of the ue bit. when ue = 1, interrupts are controlled by the i bit. when ue = 0, interrupts are controlled by the i and ui bits. table 5.4 indicates how interrupts are handled for all setting combinations of the ue, i, and ui bits. nmi interrupts are always accepted except in the reset and hardware standby states. irq interrupts and interrupts from the on-chip supporting modules have their own enable bits. interrupt requests are ignored when the enable bits are cleared to 0. table 5.4 ue, i, and ui bit settings and interrupt handling syscr ccr ue i ui description 1 0 ? all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 ? no interrupts are accepted except nmi. 0 0 ? all interrupts are accepted. interrupts with priority level 1 have higher priority. 1 0 nmi and interrupts with priority level 1 are accepted. 1 no interrupts are accepted except nmi. ue = 1: interrupts irq 0 to irq 5 and interrupts from the on-chip supporting modules can all be masked by the i bit in the cpu's ccr. interrupts are masked when the i bit is set to 1, and unmasked when the i bit is cleared to 0. interrupts with priority level 1 have higher priority. figure 5.4 is a flowchart showing how interrupts are accepted when ue = 1. 5. interrupt controller rev.5.00 sep. 12, 2007 page 98 of 764 rej09b0396-0500 pro g ram execution state interrupt requested? nmi no ye s no ye s no priority level 1? no irq 0 ye s no irq 1 ye s tei2 ye s no irq 0 ye s no irq 1 ye s tei2 ye s no i = 0 ye s save pc and ccr i 1 branch to interrupt service routine pendin g ye s read vector address figure 5.4 process up to in terrupt acceptance when ue = 1 5. interrupt controller rev.5.00 sep. 12, 2007 page 99 of 764 rej09b0396-0500 ? if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. ? when the interrupt controller receives one or mo re interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. ? the interrupt controller checks the i bit. if the i bit is cleared to 0, the selected interrupt request is accepted. if the i bit is set to 1, only nmi is accepted; other interrupt requests are held pending. ? when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. ? in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. ? next the i bit is set to 1 in ccr, masking all interrupts except nmi. ? the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. ue = 0: the i and ui bits in the cpu's ccr and the ipr bits enable three-level masking of irq 0 to irq 5 interrupts and interrupts from the on-chip supporting modules. ? interrupt requests with priority level 0 are masked when the i bit is set to 1, and are unmasked when the i bit is cleared to 0. ? interrupt requests with priority level 1 are masked when the i and ui bits are both set to 1, and are unmasked when either the i bit or the ui bit is cleared to 0. ? for example, if the interrupt enable bits of all interrupt requests are set to 1, ipra is set to h'20, and iprb is set to h'00 (giving irq 2 and irq 3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. if i = 0, all interrupts are unmasked (priority order: nmi > irq 2 > irq 3 >irq 0 ?). b. if i = 1 and ui = 0, only nmi, irq 2 , and irq 3 are unmasked. c. if i = 1 and ui = 1, all interrupts are masked except nmi. 5. interrupt controller rev.5.00 sep. 12, 2007 page 100 of 764 rej09b0396-0500 figure 5.5 shows the transitions among the above states. all interrupts are unmasked only nmi, irq , and irq are unmasked exception handlin g , or i 1, ui 1 a. b. 2 3 all interrupts are masked except nmi c. ui 0 i 0 exception handlin g , or ui 1 i 0 i 1, ui 0 figure 5.5 interrupt masking state transitions (example) figure 5.6 is a flowchart showing how interrupts are accepted when ue = 0. ? if an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. ? when the interrupt controller receives one or mo re interrupt requests, it selects the highest- priority request, following the ipr interrupt priority settings, and holds other requests pending. if two or more interrupts with the same ipr setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. ? the interrupt controller checks the i bit. if the i b it is cleared to 0, the selected interrupt request is accepted regardless of its ipr setting, and regardless of the ui bit. if the i bit is set to 1 and the ui bit is cleared to 0, only nmi and interrupts with pr iority level 1 are accepted; interrupt requests with priority level 0 are held pending. if the i bit and ui bit are both set to 1, interrupt requests are held pending. ? when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. ? in interrupt exception handling, pc and ccr are saved to the stack area. the pc value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. ? the i and ui bits are set to 1 in ccr, masking all interrupts except nmi. ? the vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. 5. interrupt controller rev.5.00 sep. 12, 2007 page 101 of 764 rej09b0396-0500 pro g ram execution state interrupt requested? nmi no ye s no ye s no priority level 1? no irq 0 ye s no irq 1 ye s tei2 ye s no irq 0 ye s no irq 1 ye s tei2 ye s no i = 0 ye s no i = 0 ye s ui = 0 ye s no save pc and ccr i 1, ui 1 pendin g branch to interrupt service routine ye s read vector address figure 5.6 process up to in terrupt acceptance when ue = 0 5. interrupt controller rev.5.00 sep. 12, 2007 page 102 of 764 rej09b0396-0500 5.4.2 interrupt sequence figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. address bus interrupt request si g nal rd hwr d to d 15 0 (1) (2), (4) (3) (5) (7) note: mode 2, with pro g ram code and stack in external memory area accessed in two states via 16-bit bus. lwr , interrupt level decision and wait for end of instruction interrupt accepted instruction prefetch internal processin g stack vector fetch internal processin g prefetch of interrupt service routine instruction hi g h instruction prefetch address (not executed; return address, same as pc contents) instruction code (not executed) instruction prefetch address (not executed) sp ? 2 sp ? 4 (6), (8) (9), (11) (10), (12) (13) (14) pc and ccr saved to stack vector address startin g address of interrupt service routine (contents of vector address) startin g address of interrupt service routine; (13) = (10), (12) first instruction of interrupt service routine (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) figure 5.7 interrupt sequence 5. interrupt controller rev.5.00 sep. 12, 2007 page 103 of 764 rej09b0396-0500 5.4.3 interrupt response time table 5.5 indicates the interrupt response time from the occurrence of an in terrupt request until the first instruction of the interrupt service routine is executed. table 5.5 interrupt response time external memory on-chip 8-bit bus 16-bit bus no. item memory 2 states 3 states 2 states 3 states 1 interrupt priority decision 2 * 1 2 * 1 2 * 1 2 * 1 2 * 1 2 maximum number of states until end of current instruction 1 to 23 1 to 27 1 to 31 * 4 1 to 23 1 to 25 * 4 3 saving pc and ccr to stack 4 8 12 * 4 4 6 * 4 4 vector fetch 4 8 12 * 4 4 6 * 4 5 instruction prefetch * 2 4 8 12 * 4 4 6 * 4 6 internal processing * 3 4 4 4 4 4 total 19 to 41 31 to 57 43 to 73 19 to 41 25 to 49 notes: 1. 1 state for internal interrupts. 2. prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. internal processing after the interrupt is accepted and internal processing after vector fetch. 4. the number of states increases if wait states are inserted in external memory access. 5. interrupt controller rev.5.00 sep. 12, 2007 page 104 of 764 rej09b0396-0500 5.5 usage notes 5.5.1 contention between interrupt and interrupt-disabling instruction when an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. if an interrupt occurs while a bclr, mov, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. if a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. this also applies to the clearing of an interrupt flag to 0. figure 5.8 shows an example in which an imiea b it is cleared to 0 in the 16-bit timer's tisra register. imia exception handlin g tisra write cycle by cpu tisra address internal address bus internal write si g nal imiea imia imfa interrupt si g nal figure 5.8 contention between interrupt and int errupt-disabling instruction this type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. 5. interrupt controller rev.5.00 sep. 12, 2007 page 105 of 764 rej09b0396-0500 5.5.2 instructions that inhibit interrupts the ldc, andc, orc, and xorc instructions inhibit interrupts. when an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a cpu interrupt. if the cpu is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the cpu always continues by executing the next instruction. 5.5.3 interrupts during eepmov instruction execution the eepmov.b and eepmov.w instructions differ in their reaction to interrupt requests. when the eepmov.b instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even nmi. when the eepmov.w instruction is executing a transfer, interrupt requests other than nmi are not accepted until the transfer is completed. if nmi is requested, nmi exception handling starts at a transfer cycle boundary. the pc value saved on the stack is the address of the next instruction. programs should be coded as follows to allow for nmi interrupts during eepmov.w execution: l1: eepmov.w mov.w r4,r4 bne l1 5. interrupt controller rev.5.00 sep. 12, 2007 page 106 of 764 rej09b0396-0500 6. bus controller rev.5.00 sep. 12, 2007 page 107 of 764 rej09b0396-0500 section 6 bus controller 6.1 overview the h8/3006 and h8/3007 have an on-chip bus controller (bsc) that manages the external address space divided into eight areas. the bus sp ecifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function that controls the operation of the internal bus masters-the cpu, dma controller (dmac), and dr am interface and can release the bus to an external device. 6.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as eight areas (0 to 7) of 128 kbytes in 1m-byte modes, or 2 mbytes in 16-mbyte modes ? bus specifications can be set independently for each area ? dram/burst rom interfaces can be set ? basic bus interface ? chip select ( cs 0 to cs 7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? two-state access or three-state access can be selected for each area ? program wait states can be inserted for each area ? pin wait insertion capability is provided ? dram interface ? dram interface can be set for areas 2 to 5 ? row address/column address multiplexed output (8/9/10 bits) ? 2-cas byte access mode ? burst operation (fast page mode) ? t p cycle insertion to secu re ras precharging time ? choice of cas-before-ras refreshing or self-refreshing 6. bus controller rev.5.00 sep. 12, 2007 page 108 of 764 rej09b0396-0500 ? burst rom interface ? burst rom interface can be set for area 0 ? selection of two- or three-state burst access ? idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle ? bus arbitration function ? a built-in bus arbiter grants the bus right to the cpu, dmac, dram interface, or an external bus master ? other features ? the refresh counter (refresh timer) can be used as an interval timer 6.1.2 block diagram figure 6.1 shows a block diagram of the bus controller. 6. bus controller rev.5.00 sep. 12, 2007 page 109 of 764 rej09b0396-0500 internal address bus abwcr astcr bcr cscr area decoder chip select control signals cs 0 to cs 7 bus control circuit wcrh wcrl brcr dram control legend: dram interface wait state controller wait back breq internal data bus cpu bus request signal dmac bus request signal dram interface bus request signal cpu bus acknowledge signal dmac bus acknowledge signal dram interface bus acknowledge signal bus arbiter bus mode control signal internal signals internal signals bus size control signal access state control signal wait request signal : bus width control register : access state control register : dram control register a : dram control register b : wait control register h : wait control register l : bus release control register : chip select control register : refresh timer control/status register : refresh timer counter : refresh time constant register astcr drcra drcrb wcrh wcrl brcr cscr rtmcsr rtcnt rtcor abwcr drcra drcrb rtmcsr rtcnt rtcor bcr : bus control register figure 6.1 block diagram of bus controller 6. bus controller rev.5.00 sep. 12, 2007 page 110 of 764 rej09b0396-0500 6.1.3 pin configuration table 6.1 summarizes the input/output pins of the bus controller. table 6.1 bus controller pins name abbreviation i/o function chip select 0 to 7 cs 0 to cs 7 output strobe signals selecting areas 0 to 7 address strobe as output strobe signal indicating valid address output on the address bus read rd output strobe signal indicating reading from the external address space high write hwr output strobe signal indicating writing to the external address space, with valid data on the upper data bus (d 15 to d 8 ) low write lwr output strobe signal indicating writing to the external address space, with valid data on the lower data bus (d 7 to d 0 ) wait wait input wait request signal for access to external three-state access areas bus request breq input request signal for releasing the bus to an external device bus acknowledge back output acknowledge signal indicating release of the bus to an external device 6. bus controller rev.5.00 sep. 12, 2007 page 111 of 764 rej09b0396-0500 6.1.4 register configuration table 6.2 summarizes the bus controller's registers. table 6.2 bus controller registers address * 1 name abbreviation r/w initial value h'ee020 bus width control register abwcr r/w h'ff * 2 h'ee021 access state control register astcr r/w h'ff h'ee022 wait control register h wcrh r/w h'ff h'ee023 wait control register l wcrl r/w h'ff h'ee013 bus release control register brcr r/w h'fe * 3 h'ee01f chip select control register cscr r/w h'0f h'ee024 bus control register bcr r/w h'c6 h'ee026 dram control register a drcra r/w h'10 h'ee027 dram control register b drcrb r/w h'08 h'ee028 refresh timer control/status register rtmcsr r/(w) * 4 h'07 h'ee029 refresh timer counter rtcnt r/w h'00 h'ee02a refresh time constant register rtcor r/w h'ff notes: 1. lower 20 bits of the address in advanced mode. 2. in modes 2 and 4, the initial value is h'00. 3. in modes 3 and 4, the initial value is h'ee. 4. for bit 7, only 0 can be written to clear the flag. 6. bus controller rev.5.00 sep. 12, 2007 page 112 of 764 rej09b0396-0500 6.2 register descriptions 6.2.1 bus width control register (abwcr) abwcr is an 8-bit readable/wr itable register that selects 8- bit or 16-bit access for each area. 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w bit modes 1 and 3 initial value read/write initial value read/write modes 2 and 4 when abwcr contains h'ff (selecting 8-bit access fo r all areas), the chip operates in 8-bit bus mode: the upper data bus (d 15 to d 8 ) is valid, and port 4 is an input/output port. when at least one bit is cleared to 0 in abwcr, the chip operates in 16-bit bus mode with a 16-bit data bus (d 15 to d 0 ). in modes 1 and 3, abwcr is initialized to h'ff by a reset and in hardware standby mode. in modes 2 and 4, abwcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0 ? area 7 to 0 bus width control (abw7 to abw0): these bits select 8-bit access or 16-bit access for the corresponding areas. bits 7 to 0 abw7 to abw0 description 0 areas 7 to 0 are 16-bit access areas 1 areas 7 to 0 are 8-bit access areas abwcr specifies the data bus width of external memory areas. the data bus width of on-chip memory and registers is fixed, and does not depend on abwcr settings. 6. bus controller rev.5.00 sep. 12, 2007 page 113 of 764 rej09b0396-0500 6.2.2 access state control register (astcr) astcr is an 8-bit readable/wr itable register that selects wh ether each area is accessed in two states or three states. bit 7 6 5 4 3 2 1 0 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bits selecting number of states for access to each area astcr is initialized to h'ff by a reset and in ha rdware standby mode. it is not initialized in software standby mode. bits 7 to 0 ? area 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is accessed in two or three states. bits 7 to 0 ast7 to ast0 description 0 areas 7 to 0 are accessed in two states 1 areas 7 to 0 are accessed in three states (initial value) astcr specifies the number of states in which external areas are accessed. on-chip memory and registers are accessed in a fixed number of states that does not depend on astcr settings. when the corresponding area is designated as dram space by bits dras2 to dras0 in dram control register a (drcra), the number of access states does not depend on the ast bit setting. when an ast bit is cleared to 0, programmable wait insertion is not performed. 6.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable regi sters that select the number of program wait states for each area. on-chip memory and registers are accessed in a fi xed number of states th at does not depend on wcrh/wcrl settings. wcrh and wcrl are initialized to h'ff by a reset and in hardware standby mode. they are not initialized in software standby mode. 6. bus controller rev.5.00 sep. 12, 2007 page 114 of 764 rej09b0396-0500 wcrh bit 7 6 5 4 3 2 1 0 w71 w70 w61 w60 w51 w50 w41 w40 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bits 7 and 6 ? area 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 w71 bit 6 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value) bits 5 and 4 ? area 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 w61 bit 4 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value) 6. bus controller rev.5.00 sep. 12, 2007 page 115 of 764 rej09b0396-0500 bits 3 and 2 ? area 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 w51 bit 2 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value) bits 1 and 0 ? area 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 w41 bit 0 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value) wcrl bit 7 6 5 4 3 2 1 0 w31 w30 w21 w20 w11 w10 w01 w00 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w 6. bus controller rev.5.00 sep. 12, 2007 page 116 of 764 rej09b0396-0500 bits 7 and 6 ? area 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 w31 bit 6 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value) bits 5 and 4 ? area 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 w21 bit 4 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value) bits 3 and 2 ? area 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 w11 bit 2 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value) 6. bus controller rev.5.00 sep. 12, 2007 page 117 of 764 rej09b0396-0500 bits 1 and 0 ? area 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 w01 bit 0 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value) 6.2.4 bus release control register (brcr) brcr is an 8-bit readable/writable register that enables address output on bus lines a 23 to a 20 and enables or disables release of the bus to an external device. 7 a23e 1 ? 1 r/w address 23 to 20 enable these bits enable pa 7 to pa 4 to be used for a 23 to a 20 address output 6 a22e 1 ? 1 r/w 5 a21e 1 ? 1 r/w 4 a20e 1 ? 0 ? 3 ? 1 ? 1 ? 2 ? 1 ? 1 ? 1 ? 1 ? 1 ? 0 brle 0 r/w 0 r/w bit initial value read/write initial value read/write modes 3 and 4 modes 1 and 2 reserved bits bus release enable enables or disables release of the bus to an external device brcr is initialized to h'fe in modes 1 and 2, and to h'ee in modes 3 and 4, by a reset and in hardware standby mode. it is not initialized in software standby mode. 6. bus controller rev.5.00 sep. 12, 2007 page 118 of 764 rej09b0396-0500 bit 7 ? address 23 enable (a23e): enables pa 4 to be used as the a 23 address output pin. writing 0 in this bit enables a 23 output from pa 4 . in modes 1 and 2, this bit cannot be modified and pa 4 has its ordinary port functions. bit 7 a23e description 0 pa 4 is the a 23 address output pin 1 pa 4 is an input/output pin (initial value) bit 6 ? address 22 enable (a22e): enables pa 5 to be used as the a 22 address output pin. writing 0 in this bit enables a 22 output from pa 5 . in modes 1 and 2, this bit cannot be modified and pa 5 has its ordinary port functions. bit 6 a22e description 0 pa 5 is the a 22 address output pin 1 pa 5 is an input/output pin (initial value) bit 5 ? address 21 enable (a21e): enables pa 6 to be used as the a 21 address output pin. writing 0 in this bit enables a 21 output from pa 6 . in modes 1 and 2, this bit cannot be modified and pa 6 has its ordinary port functions. bit 5 a21e description 0 pa 6 is the a 21 address output pin 1 pa 6 is an input/output pin (initial value) bit 4 ? address 20 enable (a20e): initial value of this bit varies depending on the mode. this bit can not be modified. bit 4 a20e description 0 pa 7 is the a 20 address output pin (initial value in mode 3 or 4) 1 pa 7 is an input/output pin (initial value in mode 1 or 2) bits 3 to 1 ? reserved: these bits cannot be modified and are always read as 1. 6. bus controller rev.5.00 sep. 12, 2007 page 119 of 764 rej09b0396-0500 bit 0 ? bus release enable (brle): enables or disables release of the bus to an external device. bit 0 brle description 0 the bus cannot be released to an external device breq and back can be used as input/output pins (initial value) 1 the bus can be released to an external device 6.2.5 bus control register (bcr) bit 7 6 5 4 3 2 1 0 icis1 icis0 brome brsts1 brsts0 ? rdea waite initial value 1 1 0 0 0 1 1 0 read/write r/w r/w r/w r/w r/w ? r/w r/w bcr is an 8-bit readable/writable re gister that enables or disables idle cycle insertion, selects the area division unit, and enables or disables wait pin input. bcr is initialized to h'c6 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7 ? idle cycle insertion 1 (icis1): selects whether one idle cycl e state is to be inserted between bus cycles in case of consecutive ex ternal read cycles for different areas. bit 7 icis1 description 0 no idle cycle inserted in case of consecutive external read cycles for different areas 1 idle cycle inserted in case of consecutive external read cycles for different areas (initial value) bit 6 ? idle cycle insertion 0 (icis0): selects whether one idle cycl e state is to be inserted between bus cycles in case of consecu tive external read and write cycles. bit 6 icis0 description 0 no idle cycle inserted in case of consecutive external read and write cycles 1 idle cycle inserted in case of consecutive external read and write cycles (initial value) 6. bus controller rev.5.00 sep. 12, 2007 page 120 of 764 rej09b0396-0500 bit 5 ? burst rom enable (brome): selects whether area 0 is a burst rom interface area. bit 5 brome description 0 area 0 is a basic bus interface area (initial value) 1 area 0 is a burst rom interface area bit 4 ? burst cycle select 1 (brsts1): selects the number of burst cycle states for the burst rom interface. bit 4 brsts1 description 0 burst access cycle comprises 2 states (initial value) 1 burst access cycle comprises 3 states bit 3 ? burst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst rom interface burst access. bit 3 brsts0 description 0 max. 4 words in burst access (burst access on match of address bits above a3) (initial value) 1 max. 8 words in burst access (burst access on match of address bits above a4) bit 2 ? reserved: read-only bit, always read as 1. bit 1 ? area division unit select (rdea): selects the memory map area division units. this bit is valid in modes 3 and 4, and is invalid in modes 1 and 2. bit 1 rdea description 0 area divisions are as follows: area 0: 2 mbytes area 4: 1.93 mbytes area 1: 2 mbytes area 5: 4 kbytes area 2: 8 mbytes area 6: 23.75 kbytes area 3: 2 mbytes area 7: 22 bytes 1 areas 0 to 7 are the same size (2 mbytes) (initial value) 6. bus controller rev.5.00 sep. 12, 2007 page 121 of 764 rej09b0396-0500 bit 0 ? wait pin enable (waite): enables or disables wait insertion by means of the wait pin. bit 0 waite description 0 wait pin wait input is disabled, and the wait pin can be used as an input/output port (initial value) 1 wait pin wait input is enabled 6.2.6 chip select control register (cscr) cscr is an 8-bit readable/writable register that enables or disables output of chip select signals ( cs 7 to cs 4 ). if output of a chip select signal is enabled by a setting in this register, the corresponding pin functions a chip select signal ( cs 7 to cs 4 ) output regardless of any other settings. reserved bits chip select 7 to 4 enable these bits enable or disable chip select signal output bit initial value read/write 7 cs7e 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 0 r/w 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? cscr is initialized to h'0f by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4 ? chip select 7 to 4 enable (cs7e to cs4e): these bits enable or disable output of the corresponding chip select signal. bit n csne description 0 output of chip select signal csn is disabled (initial value) 1 output of chip select signal csn is enabled note: n = 7 to 4 bits 3 to 0 ? reserved: these bits cannot be modified and are always read as 1. 6. bus controller rev.5.00 sep. 12, 2007 page 122 of 764 rej09b0396-0500 6.2.7 dram control register a (drcra) bit 7 6 5 4 3 2 1 0 dras2 dras1 dras0 ? be rdm srfmd rfshe initial value 0 0 0 1 0 0 0 0 read/write r/w r/w r/w ? r/w r/w r/w r/w drcra is an 8-bit readab le/writable register that selects th e areas that have a dram interface function, and the access mode, and enables or disa bles self-refreshing an d refresh pin output. drcra is initialized to h'10 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. bits 7 to 5 ? dram area select (dras2 to dras0): these bits select which of areas 2 to 5 are to function as dram interface areas (dram space), and at the same time select the ras output pin corresponding to each dram space. description bit 7 dras2 bit 6 dras1 bit 5 dras0 area 5 area 4 area 3 area 2 0 0 0 normal normal normal normal 1 normal normal normal dram space ( cs 2 ) 1 0 normal normal dram space ( cs 3 ) dram space ( cs 2 ) 1 normal normal dram space ( cs 2 ) * 1 0 0 normal dram space ( cs 4 ) dram space ( cs 3 ) dram space ( cs 2 ) 1 dram space ( cs 5 ) dram space ( cs 4 ) dram space ( cs 3 ) dram space ( cs 2 ) 1 0 dram space ( cs 4 ) * dram space ( cs 2 ) * 1 dram space ( cs 2 ) * note: * a single csn pin serves as a common ras output pin for a number of areas. unused csn pins can be used as input/output ports. when any of bits dras2 to dras0 is set to 1, it is not possible to write to drcrb, rtmcsr, rtcnt, or rtcor. however, 0 can be written to the cmf flag in rtmcsr to clear the flag. 6. bus controller rev.5.00 sep. 12, 2007 page 123 of 764 rej09b0396-0500 when an arbitrary value has been set in dras2 to dras0, a write of a different value other than 000 must not be performed. bit 4 ? reserved: this bit cannot be modified and is always read as 1. bit 3 ? burst access enable (be): enables or disables burst access to dram space. dram space burst access is performed in fast page mode. bit 3 be description 0 burst disabled (always full access) (initial value) 1 dram space access performed in fast page mode bit 2 ? ras down mode (rdm): selects whether to wait for the next dram access with the ras signal held low (ras down mode), or to drive the ras signal high again (ras up mode), when burst access is enabled for dram space (b e = 1), and access to dram is interrupted. caution is required when the hwr and lwr are used as the ucas and lcas output pins. for details, see ras down mode and ras up mode in section 6.5.10, burst operation. bit 2 rdm description 0 dram interface: ras up mode selected (initial value) 1 dram interface: ras down mode selected bit 1 ? self-refresh mode (srfmd): specifies dram self-refreshing in software standby mode. when any of areas 2 to 5 is designated as dram space, dram self-refreshing is possible when a transition is made to software standby mode after the srfmd bit has been set to 1. the normal access state is restored when software standby mode is exited, regardless of the srfmd setting. bit 1 srfmd description 0 dram self-refreshing disabled in software standby mode (initial value) 1 dram self-refreshing enabled in software standby mode 6. bus controller rev.5.00 sep. 12, 2007 page 124 of 764 rej09b0396-0500 bit 0 ? refresh pin enable (rfshe): enables or disables rfsh pin refresh signal output. if areas 2 to 5 are not designated as dram space, this bit should not be set to 1. bit 0 rfshe description 0 rfsh pin refresh signal output disabled (initial value) ( rfsh pin can be used as input/output port) 1 rfsh pin refresh signal output enabled 6.2.8 dram control register b (drcrb) bit 7 6 5 4 3 2 1 0 mxc1 mxc0 csel rcyce ? tpc rcw rlw initial value 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w ? r/w r/w r/w drcrb is an 8-bit readable/writable register that selects the number of address multiplex column address bits for the dram interf ace, the column address strobe out put pin, enabling or disabling of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state insertion between ras and cas , and enabling or disabling of wait state insertion in refresh cycles. drcrb is initialized to h'08 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. the settings in this register are invalid when bits dras2 to dras0 in drcra are all 0. 6. bus controller rev.5.00 sep. 12, 2007 page 125 of 764 rej09b0396-0500 bits 7 and 6 ? multiplex control 1 and 0 (mxc1, mxc0): these bits select the row address/column address multiplexing method used on the dram interface. in burst operation, the row address used for comparison is determined by the setting of these bits and the bus width of the relevant area set in abwcr. bit 7 mxc1 bit 6 mxc0 description 0 0 column address: 8 bits compared address: modes 1, 2 8-bit access space a 19 to a 8 16-bit access space a 19 to a 9 modes 3, 4 8-bit access space a 23 to a 8 16-bit access space a 23 to a 9 1 column address: 9 bits compared address: modes 1, 2 8-bit access space a 19 to a 9 16-bit access space a 19 to a 10 modes 3, 4 8-bit access space a 23 to a 9 16-bit access space a 23 to a 10 1 0 column address: 10 bits compared address: modes 1, 2 8-bit access space a 19 to a 10 16-bit access space a 19 to a 11 modes 3, 4 8-bit access space a 23 to a 10 16-bit access space a 23 to a 11 1 illegal setting bit 5 ? cas output pin select (csel): selects the ucas and lcas output pins when areas 2 to 5 are designated as dram space. bit 5 csel description 0 pb4 and pb5 selected as ucas and lcas output pins (initial value) 1 hwr and lwr selected as ucas and lcas output pins 6. bus controller rev.5.00 sep. 12, 2007 page 126 of 764 rej09b0396-0500 bit 4 ? refresh cycle enable (rcyce): cas-before-ras enables or disables refresh cycle insertion. when none of areas 2 to 5 has been designated as dram space, refresh cycles are not inserted regardless of the setting of this bit. bit 4 rcyce description 0 refresh cycles disabled (initial value) 1 dram refresh cycles enabled bit 3 ? reserved: this bit cannot be modified and is always read as 1. bit 2 ? tp cycle control (tpc): selects whether a 1-state or two- state precharge cycle (tp) is to be used for dram read/write cycles and cas-be fore-ras refresh cycles. the setting of this bit does not affect the self-refresh function. bit 2 tpc description 0 1-state precharge cycle inserted (initial value) 1 2-state precharge cycle inserted bit 1 ? ras - cas wait (rcw): controls wait state (trw) insertion between t r and t c1 in dram read/write cycles. the setting of this bit does not affect refresh cycles. bit 1 rcw description 0 wait state (trw) insertion disabled (initial value) 1 one wait state (trw) inserted bit 0 ? refresh cycle wait control (rlw): controls wait state (t rw ) insertion for cas-before- ras refresh cycles. the setting of this bit does not affect dram read/write cycles. bit 0 rlw description 0 wait state (t rw ) insertion disabled (initial value) 1 one wait state (t rw ) inserted 6. bus controller rev.5.00 sep. 12, 2007 page 127 of 764 rej09b0396-0500 6.2.9 refresh timer contro l/status register (rtmcsr) bit 7 6 5 4 3 2 1 0 cmf cmie cks2 cks1 cks0 ? ? ? initial value 0 0 0 0 0 1 1 1 read/write r/(w) * r/w r/w r/w r/w ? ? ? rtmcsr is an 8-bit readable/writable register that selects the refresh timer counter clock. when the refresh timer is used as an interval timer, rt mcsr also enables or disables interrupt requests. bits 7 and 6 of rtmcsr are initialized to 0 by a reset and in the standby modes. bits 5 to 3 are initialized to 0 by a reset and in hardware sta ndby mode; they are not initialized in software standby mode. note: only 0 can be written to clear the flag. bit 7 ? compare match flag (cmf): status flag that indicates a match between the values of rtcnt and rtcor. bit 7 cmf description 0 [clearing conditions] ? when the chip is reset and in standby mode ? read cmf when cmf = 1, then write 0 in cmf (initial value) 1 [setting condition] when rtcnt = rtcor bit 6 ? compare match interrupt enable (cmie): enables or disables the cmi interrupt requested when the cmf flag is set to 1 in rtmcsr. the cmie bit is always cleared to 0 when any of areas 2 to 5 is designated as dram space. bit 6 cmie description 0 the cmi interrupt requested by cmf is disabled (initial value) 1 the cmi interrupt requested by cmf is enabled 6. bus controller rev.5.00 sep. 12, 2007 page 128 of 764 rej09b0396-0500 bits 5 to 3 ? refresh counter clock select (cks2 to cks0): these bits select the clock to be input to rtcnt from among 7 clocks obtained by dividing the system clock ( ). when the input clock is selected with bits cks2 to cks0, rtcnt begins counting up. bit 5 cks2 bit 4 cks1 bit 3 cks0 description 0 0 0 count operation halted (initial value) 1 /2 used as counter clock 1 0 /8 used as counter clock 1 /32 used as counter clock 1 0 0 /128 used as counter clock 1 /512 used as counter clock 1 0 /2048 used as counter clock 1 /4096 used as counter clock bits 2 to 0 ? reserved: these bits cannot be modified and are always read as 1. 6.2.10 refresh timer counter (rtcnt) bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w rtcnt is an 8-bit readable/writable up-counter. rtcnt is incremented by an internal clock sel ected by bits cks2 to cks0 in rtmcsr. when rtcnt matches rtcor (compare match), the cmf flag in rtmcsr is set to 1 and rtcnt is cleared to h'00. if the rcyce bit in drcrb is set to 1 at this time, a refresh cycle is started. also, if the cmie bit in rtmcsr is set to 1, a compare match interrupt (cmi) is generated. rtcnt is initialized to h'00 by a reset and in standby mode. 6. bus controller rev.5.00 sep. 12, 2007 page 129 of 764 rej09b0396-0500 6.2.11 refresh time constant register (rtcor) bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w rtcor is an 8-bit readable/writable register that sets the rtcnt compare-match interval. rtcor and rtcnt are constantly compared. when th eir values match, the cmf flag is set to 1 in rtmcsr, and rtcnt is simultaneously cleared to h'00. rtcor is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. note: only byte access should be used with this register. 6. bus controller rev.5.00 sep. 12, 2007 page 130 of 764 rej09b0396-0500 6.3 operation 6.3.1 area division the external address space is divided into areas 0 to 7. each area has a size of 128 kbytes in the 1- mbyte modes, or 2-mbytes in the 16-mbyte modes. figure 6.2 shows a general view of the memory map. h'00000 h'1ffff h'20000 h'3ffff h'40000 h'5ffff h'60000 h'7ffff h'80000 h'9ffff h'a0000 h'bffff h'c0000 h'dffff h'e0000 h'fffff area 0 (128 kbytes) area 1 (128 kbytes) area 2 (128 kbytes) area 3 (128 kbytes) area 4 (128 kbytes) area 5 (128 kbytes) area 6 (128 kbytes) area 7 (128 mbytes) h'000000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'ffffff area 0 (2 mbytes) area 1 (2 mbytes) area 2 (2 mbytes) area 3 (2 mbytes) area 4 (2 mbytes) area 5 (2 mbytes) area 6 (2 mbytes) area 7 (2 mbytes) (a) 1-mbyte modes (modes 1 and 2) (b) 16-mbyte modes (modes 3 and 4) figure 6.2 access area ma p for each operating mode chip select signals ( cs 0 to cs 7 ) can be output for areas 0 to 7. the bus specifications for each area are selected in abwcr, astcr, wcrh, and wcrl. in 16-mbyte mode, the area division units can be selected with the rdea bit in bcr. 6. bus controller rev.5.00 sep. 12, 2007 page 131 of 764 rej09b0396-0500 h'000000 h'1fffff h'200000 h'3fffff h'400000 h'5fffff h'600000 h'7fffff h'800000 h'9fffff h'a00000 h'bfffff h'c00000 h'dfffff h'e00000 h'fee000 h'fee0ff h'fee100 h'ff7fff h'ff8000 h'ff8fff h'ff9000 h'ffef1f h'ffef20 h'fffeff h'ffff00 h'ffff1f h'ffff20 h'ffffe9 h'ffffea h'ffffff area 0 2 mbytes area 1 2 mbytes area 2 2 mbytes area 3 2 mbytes area 4 2 mbytes area 5 2 mbytes area 6 2 mbytes area 7 1.93 mbytes internal i/o re g isters (1) area 7 67.5 kbytes on-chip ram 4 kbytes internal i/o re g isters (2) area 7 22 bytes area 0 2 mbytes area 1 2 mbytes area 2 8 mbytes area 3 2 mbytes area 4 1.93 mbytes area 5 4 kbytes on-chip ram 4 kbytes * internal i/o re g isters (2) area 7 22 bytes area 6 23.75 kbytes internal i/o re g isters (1) 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes 2 mbytes absolute address 16 bits absolute address 8 bits (a) memory map when rdea = 1 note: * area 6 when the rame bit is cleared. (b) memory map when rdea = 0 reserved 39.75 kbytes figure 6.3 memory map in 16-mbyte mode (h8/3007) 6. bus controller rev.5.00 sep. 12, 2007 page 132 of 764 rej09b0396-0500 6.3.2 bus specifications the external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. the bus width and number of access states for on-ch ip memory and registers are fixed, and are not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. number of access states: two or three access states can be se lected with astcr. an area for which two-state access is selected functions as a two-state access space, and an area for which three-state access is selected func tions as a three-state access space. dram space is accessed in four states regardless of the astcr settings. when two-state access space is designated, wait insertion is disabled. number of program wait states: when three-state access space is designated in astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. when astcr is cleared to 0 for dram space, a program wait (t c1 ? t c2 wait) is not inserted. also, no program wait is inserted in burst rom space burst cycles. table 6.3 shows the bus specifications for each basic bus interface area. 6. bus controller rev.5.00 sep. 12, 2007 page 133 of 764 rej09b0396-0500 table 6.3 bus specificati ons for each area (basic bus interface) abwcr astcr wcrh/wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 0 0 ? ? 16 2 0 1 0 0 3 0 1 1 1 0 2 1 3 1 0 ? ? 8 2 0 1 0 0 3 0 1 1 1 0 2 1 3 6.3.3 memory interfaces the h8/3006 and h8/3007 memory interfaces compri se a basic bus interface that allows direct connection of rom, sram, and so on; a dram interface that allows direct connection of dram; and a burst rom interface that allows dir ect connection of burst rom. the interface can be selected independently for each area. an area for which the basic bus interface is designated functions as normal space, an area for which the dram interface is designated functions as dram space, and area 0 for which the burst rom interface is designated functions as burst rom space. 6.3.4 chip select signals for each of areas 0 to 7, the h8/3006 and h8/3007 can output a chip select signal ( cs 0 to cs 7 ) that goes low when the corresponding area is selected. figure 6.4 shows the output timing of a cs n signal. output of cs 0 to cs 3 : output of cs 0 to cs 3 is enabled or disabled in the data direction register (ddr) of the corresponding port. a reset leaves pin cs 0 in the output state and pins cs 1 to cs 3 in the input state. to output chip select signals cs 1 to cs 3 , the corresponding ddr bits must be set to 1. for details, see section 8, i/o ports. 6. bus controller rev.5.00 sep. 12, 2007 page 134 of 764 rej09b0396-0500 output of cs 4 to cs 7 : output of cs 4 to cs 7 is enabled or disabled in the chip select control register (cscr). a reset leaves pins cs 4 to cs 7 in the input state. to output chip select signals cs 4 to cs 7 , the corresponding cscr bits must be set to 1. for details, see section 8, i/o ports. address bus external address in area n cs n figure 6.4 cs n signal output timing (n = 0 to 7) when the on-chip ram and on-chip registers are accessed, cs 0 to cs 7 remain high. the cs n signals are decoded from the address signals. they can be used as chip select signals for sram and other devices. 6.4 basic bus interface 6.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 6.3). 6.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing extern al space, controls whether the upper data bus (d 15 to d 8 ) or lower data bus (d 7 to d 0 ) is used according to the bus specifications for the area being accessed (8-bit access area or 16-bit access area) and the data size. 6. bus controller rev.5.00 sep. 12, 2007 page 135 of 764 rej09b0396-0500 8-bit access areas: figure 6.5 illustrates data alignment control for 8-bit access space. with 8-bit access space, the upper data bus (d 15 to d 8 ) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. d 15 d 8 d 7 d 0 upper data bus lower data bus 1st bus cycle 2nd bus cycle 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle byte size word size lon g word size figure 6.5 access sizes and data alignment control (8-bit access area) 16-bit access areas: figure 6.6 illustrates data alignment control for 16-bit access areas. with 16-bit access areas, the upper data bus (d 15 to d 8 ) and lower data bus (d 7 to d 0 ) are used for accesses. the amount of data that can be accesse d at one time is one byte or one word, and a longword access is executed as two word accesses. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d 15 d 8 d 7 d 0 upper data bus lower data bus 1st bus cycle 2nd bus cycle byte size lon g word size even address odd address word size byte size figure 6.6 access sizes and data a lignment control (16-bit access area) 6. bus controller rev.5.00 sep. 12, 2007 page 136 of 764 rej09b0396-0500 6.4.3 valid strobes table 6.4 shows the data buses used, and the valid strobes, for the access spaces. in a read, the rd signal is valid for both the upper and the lower half of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. table 6.4 data buses used and valid strobes area access size read/write address valid strobe upper data bus (d 15 to d 8 ) lower data bus (d 7 to d 0 ) byte read ? rd valid invalid 8-bit access area write ? hwr undetermined data byte read even rd valid invalid odd invalid valid 16-bit access area write even hwr valid undetermined data odd lwr undetermined data valid word read ? rd valid valid write ? hwr , lwr valid valid notes: 1. undetermined data means that unpredictable data is output. 2. invalid means that the bus is in the input state and the input is ignored. 6.4.4 memory areas the initial state of each area is basic bus interface, three-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the following sections should be referred to for further details: 6.4, basic bus interface, 6.5, dram interface, 6.8, burst rom interface. area 0: when area 0 external space is accessed, the cs 0 signal can be output. either basic bus interface or burst rom interface can be selected for area 0. the size of area 0 is 128 kbytes in modes 1 and 2, and 2 mbytes in modes 3 and 4. areas 1 and 6: when area 1 and 6 external space is accessed, the cs 1 and cs 6 pin signals respectively can be output. only the basic bus interface can be used for areas 1 and 6. 6. bus controller rev.5.00 sep. 12, 2007 page 137 of 764 rej09b0396-0500 the size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 mbytes in modes 3 and 4. areas 2 to 5: when area 2 to 5 external space is accessed, signals cs 2 to cs 5 can be output. basic bus interface or dram interface can be select ed for areas 2 to 5. w ith the dram interface, signals cs 2 to cs 5 are used as ras signals. the size of areas 2 to 5 is 128 kbytes in modes 1 and 2, and 2 mbytes in modes 3 and 4. area 7: area 7 includes the on-chip ram and regist ers. the space excluding the on-chip ram and registers is external space. the on-chip ram is enabled when the ra me bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space . when area 7 external space is accessed, the cs 7 signal can be output. only the basic bus interface can be us ed for the area 7 memory interface. the size of area 7 is 128 kbytes in modes 1 and 2, and 2 mbytes in modes 3 and 4. 6. bus controller rev.5.00 sep. 12, 2007 page 138 of 764 rej09b0396-0500 6.4.5 basic bus control signal timing 8-bit, three-state-access areas: figure 6.7 shows the timing of bus control signals for an 8-bit, three-state-access area. the upper data bus (d 15 to d 8 ) is used in accesses to these areas. the lwr pin is always high. wait states can be inserted. bus cycle external address in area n valid invalid valid undetermined data hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 figure 6.7 bus control signal timi ng for 8-bit, three-state-access area 6. bus controller rev.5.00 sep. 12, 2007 page 139 of 764 rej09b0396-0500 8-bit, two-state-access areas: figure 6.8 shows the timing of bus control signals for an 8-bit, two-state-access area. the upper data bus (d 15 to d 8 ) is used in accesses to these areas. the lwr pin is always high. wait states cannot be inserted. bus cycle external address in area n valid invalid valid undetermined data hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 figure 6.8 bus control signal timing for 8-bit, two-state-access area 6. bus controller rev.5.00 sep. 12, 2007 page 140 of 764 rej09b0396-0500 16-bit, three-state-access areas: figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, three-state-access area. in these areas, the upper data bus (d 15 to d 8 ) is used in accesses to even addresses and the lower data bus (d 7 to d 0 ) in accesses to odd addresses. wait states can be inserted. bus cycle even external address in area n valid invalid valid hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 undetermined data figure 6.9 bus control signal timing for 16-bit, three-state-access area (1) (byte access to even address) 6. bus controller rev.5.00 sep. 12, 2007 page 141 of 764 rej09b0396-0500 bus cycle odd external address in area n valid invalid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 hi g h undetermined data figure 6.10 bus control signal timing for 16-bit, three-state-access area (2) (byte access to odd address) 6. bus controller rev.5.00 sep. 12, 2007 page 142 of 764 rej09b0396-0500 bus cycle external address in area n valid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 t 3 valid valid figure 6.11 bus control signal timing for 16-bit, three-state-access area (3) (word access) 6. bus controller rev.5.00 sep. 12, 2007 page 143 of 764 rej09b0396-0500 16-bit, two-state-access areas: figures 6.12 to 6.14 show the timing of bus control signals for a 16-bit, two-state-access area. in these areas, the upper data bus (d 15 to d 8 ) is used in accesses to even addresses and the lower data bus (d 7 to d 0 ) in accesses to odd addresses. wait states cannot be inserted. bus cycle even external address in area n valid invalid valid hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 undetermined data figure 6.12 bus control signal timing for 16-bit, two-state-access area (1) (byte access to even address) 6. bus controller rev.5.00 sep. 12, 2007 page 144 of 764 rej09b0396-0500 bus cycle odd external address in area n valid invalid valid hi g h address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 undetermined data figure 6.13 bus control signal timing for 16-bit, two-state-access area (2) (byte access to odd address) 6. bus controller rev.5.00 sep. 12, 2007 page 145 of 764 rej09b0396-0500 bus cycle external address in area n valid valid address bus cs n as rd d 15 to d 8 d 7 to d 0 hwr lwr d 15 to d 8 d 7 to d 0 read access write access note: n = 7 to 0 t 1 t 2 valid valid figure 6.14 bus control signal timing for 16-bit, two-state-access area (3) (word access) 6.4.6 wait control when accessing external space, the h8/3006 an d h8/3007 can extend the bus cycle by inserting one or more wait states (t w ). there are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the wait pin. program wait insertion: from 0 to 3 wait states can be in serted automatically between the t 2 state and t 3 state on an individual area basis in three-state access space, according to the settings of wcrh and wcrl. 6. bus controller rev.5.00 sep. 12, 2007 page 146 of 764 rej09b0396-0500 pin wait insertion: setting the waite bit in bcr to 1 enables wait insertion by means of the wait pin. when external space is accessed in this state, a program wait is first inserted. if the wait pin is low at the falling edge of in the last t 2 or t w state, another t w state is inserted. if the wait pin is held low, t w states are inserted until it goes high. this is useful when inserting four or more t w states, or when changing the number of t w states for different external devices. the waite bit setting applies to all areas. pi n waits cannot be inserted in dram space. figure 6.15 shows an example of the timing for insertion of one program wait state in 3-state space. wait address bus data bus read access write access data bus as rd t 1 t 2 t w t w t w t 3 hwr , lwr note: indicates the timing of wait pin sampling. inserted by program wait inserted by wait pin read data write data figure 6.15 example of wait state insertion timing 6. bus controller rev.5.00 sep. 12, 2007 page 147 of 764 rej09b0396-0500 6.5 dram interface 6.5.1 overview the h8/3006 and h8/3007 are provided with a dram interface with functions for dram control signal ( ras , ucas , lcas , we ) output, address multiplexing, and refreshing, that direct connection of dram. in the expanded modes, external address space areas 2 to 5 can be designated as dram space accessed via the dram interface. a data bus width of 8 or 16 bits can be selected for dram space by means of a setting in abwcr. when a 16-bit data bus width is selected, cas is used for byte access control. in the case of 16-bit organization dram, therefore, the 2-cas type can be connected. a fa st page mode is supported in addition to the normal read and write access modes. 6.5.2 dram space and ras output pin settings designation of areas 2 to 5 as dram space, and selection of the ras output pin for each area designated as dram space, is performed by setti ng bits dras2 to dras0 in drcra. table 6.5 shows the correspondence between the settings of bits dras2 to dras0 and the selected dram space and ras output pin. when an arbitrary value has been set in dras2 to dras0, a write of a different value other than 000 must not be performed. table 6.5 settings of bits dras2 to dras0 and correspondi ng dram space ( ras output pin) dras2 dras1 dras0 area 5 area 4 area 3 area 2 0 0 0 normal space normal space normal space normal space 1 normal space normal space normal space dram space ( cs 2 ) 1 0 normal space normal space dram space ( cs 3 ) dram space ( cs 2 ) 1 normal space normal space dram space ( cs 2 ) * 1 0 0 normal space dram space ( cs 4 ) dram space ( cs 3 ) dram space ( cs 2 ) 1 dram space ( cs 5 ) dram space ( cs 4 ) dram space ( cs 3 ) dram space ( cs 2 ) 1 0 dram space ( cs 4 ) * dram space ( cs 2 ) * 1 dram space ( cs 2 ) * note: * a single cs n pin serves as a common ras output pin for a number of areas. unused cs n pins can be used as input/output ports. 6. bus controller rev.5.00 sep. 12, 2007 page 148 of 764 rej09b0396-0500 6.5.3 address multiplexing when dram space is accessed, the row address and column address are multiplexed. the address multiplexing method is selected with bits mxc1 and mxc0 in drcrb according to the number of bits in the dram co lumn address. table 6.6 shows the correspondence between the settings of mxc1 and mxc0 and the address multiplexing method. table 6.6 settings of bits mxc1 and mxc0 and address multiplexing method drcrb column address address pins mxc1 mxc0 bits a 23 to a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 0 8 bits a 23 to a 13 a 20 * a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 row address 1 9 bits a 23 to a 13 a 12 a 20 * a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 1 0 10 bits a 23 to a 13 a 12 a 11 a 20 * a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 1 illegal setting ? ? ? ? ? ? ? ? ? ? ? ? ? ? column address ? ? ? a 23 to a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 note: * row address bit a 20 is not multiplexed in 1-mbyte mode. 6.5.4 data bus if the bit in abwcr corresponding to an area designa ted as dram space is set to 1, that area is designated as 8-bit dram space; if the bit is clear ed to 0, the area is designated as 16-bit dram space. in 16-bit dram space, 16-bit organization dram can be connected directly. in 8-bit dram space the upper half of the data bus, d 15 to d 8 , is enabled, while in 16-bit dram space both the upper and lower halves of the data bus, d 15 to d 0 , are enabled. access sizes and data alignment are the same as fo r the basic bus interface: see section 6.4.2, data size and data alignment. 6. bus controller rev.5.00 sep. 12, 2007 page 149 of 764 rej09b0396-0500 6.5.5 pins used for dram interface table 6.7 shows the pins used for dram interfacing and their functions. table 6.7 dram interface pins pin with dram designated name i/o function pb4 ucas upper column address strobe output upper column address strobe for dram space access (when csel = 0 in drcrb) pb5 lcas lower column address strobe output lower column address strobe for dram space access (when csel = 0 in drcrb) hwr ucas upper column address strobe output upper column address strobe for dram space access (when csel = 1 in drcrb) lwr lcas lower column address strobe output lower column address strobe for dram space access (when csel = 1 in drcrb) cs 2 ras 2 row address strobe 2 output row address strobe for dram space access cs 3 ras 3 row address strobe 3 output row address strobe for dram space access cs 4 ras 4 row address strobe 4 output row address strobe for dram space access cs 5 ras 5 row address strobe 5 output row address strobe for dram space access rd we write enable output write enable for dram space write access * p80 rfsh refresh output goes low in refresh cycle a 12 to a 0 a 12 to a 0 address output row address/ column address multiplexed output d 15 to d 0 d 15 to d 0 data i/o data input/output pins note: * fixed high in a read access. 6.5.6 basic timing figure 6.16 shows the basic access timing for dram space. the basic dram access timing is four states: one precharge cycle (t p ) state, one row address output cycle (t r ) state, and two column address output cycle (t c1 , t c2 ) states. unlike the basic bus inte rface, the corresponding bits in astcr control only enabling or disabling of wait insertion between t c1 and t c2 , and do not affect the number of access states. when the corresponding bit in astcr is cleared to 0, wait states cannot be inserted between t c1 and t c2 in the dram access cycle. 6. bus controller rev.5.00 sep. 12, 2007 page 150 of 764 rej09b0396-0500 if a dram read/write cycle is fo llowed by an access cycle for an external area other than dram space when hwr and lwr are selected as the ucas and lcas output pins, an idle cycle (ti) is inserted unconditionally immediat ely after the dram access cycle. see section 6.9, idle cycle, for details. a 23 to a 0 csn ( ras ) t p tr t c1 t c2 ( ucas / lcas ) pb4 /pb5 as rd ( we ) d 15 to d 0 rd ( we ) d 15 to d 0 ( ucas / lcas ) pb4 /pb5 row hi g h hi g h column read access write access note: n = 2 to 5 figure 6.16 basic access timing (csel = 0 in drcrb) 6. bus controller rev.5.00 sep. 12, 2007 page 151 of 764 rej09b0396-0500 6.5.7 precharge state control in the h8/3006 and h8/3007, provision is made for the dram ras precharge time by always inserting one ras precharge state (t p ) when dram space is accessed. this can be changed to two t p states by setting the tpc bit to 1 in drcrb. the optimum number of t p cycles should be set according to the dram connected and the op erating frequency of the h8/3006 and h8/3007 chip. figure 6.17 shows the timing when two t p states are inserted. when the tcp bit is set to 1, two t p states are also used for cas-before-ras refresh cycles. a 23 to a 0 csn ( ras ) as t p1 tr t c1 ( ucas / lcas ) pb4 /pb5 rd ( we ) d 15 to d 0 rd ( we ) d 15 to d 0 ( ucas / lcas ) pb4 /pb5 t c2 t p2 note: n = 2 to 5 row hi g h hi g h column read access write access figure 6.17 timing with two p recharge states (csel = 0 in drcrb) 6. bus controller rev.5.00 sep. 12, 2007 page 152 of 764 rej09b0396-0500 6.5.8 wait control in a dram access cycle, wait states can be inserted (1) between the t r state and t c1 state, and (2) between the t c1 state and t c2 state. insertion of t rw wait state between t r and t c1 : one t rw state can be inserted between t r and t c1 by setting the rcw bit to 1 in drcrb. insertion of t w wait state(s) between t c1 and t c2 : when the bit in astcr corresponding to an area designated as dram space is set to 1, from 0 to 3 t w states can be inserted between the t c1 state and t c2 state by means of settings in wcrh and wcrl. figure 6.18 shows an example of the timing for wait state insertion. the settings of the rcw bit in drcrb and of astcr, wcrh, and wcrl do not affect refresh cycles. wait states cannot be inserted in a dram space access cycle by means of the wait pin. t p tr t c1 t c2 ( ucas / lcas ) pb4 /pb5 rd ( we ) csn ( ras ) as d 15 to d 0 rd ( we ) d 15 to d 0 ( ucas / lcas ) pb4 /pb5 a 23 to a 0 trw tw tw write access read access read data write data note: n = 2 to 5 row column hi g h hi g h figure 6.18 example of wait state insertion timing (csel = 0) 6. bus controller rev.5.00 sep. 12, 2007 page 153 of 764 rej09b0396-0500 6.5.9 byte access control and cas output pin when an access is made to dram space designa ted as a 16-bit-access ar ea in abwcr, column address strobes ( ucas and lcas ) corresponding to the upper and lower halves of the external data bus are output. in the case of 16-bit organization dram, the 2-cas type can be connected. either pb4 and pb5, or hwr and lwr , can be used as the ucas and lcas output pins, the selection being made with the csel bit in drcrb. table 6.8 shows the csel bit settings and corresponding output pin selections. when an access is made to dram space designa ted as an 8-bit-access area in abwcr, only ucas is output. when the entire dram space is designated as 8-bit-access space and csel = 0, pb5 can be used as an input/output port. note that ras down mode cannot be used when a device other than dram is connected to external space and hwr and lwr are used as write strobes. in this case, also, an idle cycle (ti) is always inserted when an external access to ot her than dram space occurs after a dram space access. for details, see section 6.9, idle cycle. table 6.8 csel settings and ucas and lcas output pins csel ucas lcas 0 pb4 pb5 1 hwr lwr figure 6.19 shows the control timing. 6. bus controller rev.5.00 sep. 12, 2007 page 154 of 764 rej09b0396-0500 a 23 to a 0 csn ( ras ) t p tr t c1 t c2 pb4( ucas ) pb5( lcas ) rd ( we ) note: n = 2 to 5 byte control row column figure 6.19 control timing (upper- byte write access when csel = 0) 6.5.10 burst operation with dram, in addition to full access (normal acce ss) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row addre ss. this mode enables fast (burst) access of data by simply changing the column address afte r the row address has been output. burst access can be selected by setting the be bit to 1 in drcra. burst access (fast page mode) operation timing: figure 6.20 shows the operation timing for burst access. when there are consecutive access cycl es for dram space, the column address and cas signal output cycles (two states) continue as long as the row address is the same for consecutive access cycles. in burst access, too, th e bus cycle can be extended by inserting wait states between t c1 and t c2 . the wait state insertion method and timing are the same as for full access: see section 6.5.8, wait control, for details. the row address used for the comparison is determined by the bus width of the relevant area set in bits mxc1 and mxc0 in brcrb, and in abwcr. table 6.9 shows the compared row addresses corresponding to the various settings of bits mxc1 and mxc0, and abwcr. 6. bus controller rev.5.00 sep. 12, 2007 page 155 of 764 rej09b0396-0500 a 23 to a 0 cs n( ras ) as t p tr t c2 ( ucas / lcas ) pb4 /pb5 rd ( we ) d 15 to d 0 ( ucas / lcas ) pb4 /pb5 t c2 t c1 t c1 d 15 to d 0 rd ( we ) note: n = 2 to 5 read access write access row column 1 column 2 hi g h hi g h figure 6.20 operation timing in fast page mode 6. bus controller rev.5.00 sep. 12, 2007 page 156 of 764 rej09b0396-0500 table 6.9 correspondence between settings of mxc1 and mxc0 bi ts and abwcr, and row address compared in burst access drcrb abwcr operating mode mxc1 mxc0 abwn bus width compared row address 0 0 0 16 bits a19 to a9 modes 1 and 2 (1-mbyte) 1 8 bits a19 to a8 1 0 16 bits a19 to a10 1 8 bits a19 to a9 1 0 0 16 bits a19 to a11 1 8 bits a19 to a10 1 ? ? illegal setting 0 0 0 16 bits a23 to a9 modes 3 and 4 (16-mbyte) 1 8 bits a23 to a8 1 0 16 bits a23 to a10 1 8 bits a23 to a9 1 0 0 16 bits a23 to a11 1 8 bits a23 to a10 1 ? ? illegal setting note: n = 2 to 5 ras down mode and ras up mode: with dram provided with fast page mode, as long as accesses are to the same row address, burst operati on can be continued without interruption even if accesses are not consecutive by holding the ras signal low. ? ras down mode to select ras down mode, set the be and rd m bits to 1 in drcra. if access to dram space is interrupted and another space is accessed, the ras signal is held low during the access to the other space, and burst access is perf ormed if the row address of the next dram space access is the same as the row address of the previous dram space access. figure 6.21 shows an example of the timing in ras down mode. 6. bus controller rev.5.00 sep. 12, 2007 page 157 of 764 rej09b0396-0500 a 23 to a 0 csn ( ras ) t p tr t c2 ( ucas / lcas ) pb4/pb5 d 15 to d 0 t 2 t c1 t 1 t c2 t c1 as note: n = 2 to 5 dram access dram access external space access figure 6.21 example of operation timing in ras down mode (csel = 0) when ras down mode is selected, the conditions for an asserted ras n signal to return to the high level are as shown below. the timing in these cases is shown in figure 6.22. ? when dram space with a different row address is accessed ? immediately before a cas- before-ras refresh cycle ? when the be bit or rdm bit is cleared to 0 in drcra ? immediately before releas e of the external bus 6. bus controller rev.5.00 sep. 12, 2007 page 158 of 764 rej09b0396-0500 r as n r as n r as n r as n note: n = 2 to 5 dram access cycle cbr refresh cycle drcra write cycle external bus released hi g h-impedance (a) access to dram space with a different row address (b) cas-before-ras refresh cycle (c) be bit or rdm bit cleared to 0 in drcra (d) external bus released figure 6.22 ras n negation timing when ras down mode is selected 6. bus controller rev.5.00 sep. 12, 2007 page 159 of 764 rej09b0396-0500 when ras down mode is selected, the cas-before-ras refresh function provided with this dram interface must always be used as the dram refreshing method. when a refresh operation is performed, the ras signal goes high immediately beforehand. the refresh interval setting must be made so that the maximum dram ras pulse width specification is observed. when the self-refresh function is used, the rdm bit must be cleared to 0, and ras up mode selected, before executing a sleep instruction in order to enter software standby mode. select ras down mode again after exiting software standby mode. note that ras down mode cannot be used when hwr and lwr are selected for ucas and lcas , a device other than dram is c onnected to external space, and hwr and lwr are used as write strobes. ? ras up mode to select ras up mode, clear the rdm bit to 0 in drcra. each time access to dram space is interrupted and another space is accessed, the ras signal returns to the high level. burst operation is only performed if dram space is continuous. figure 6.23 shows an example of the timing in ras up mode. a 23 to a 0 csn ( ras ) as t p tr t c2 d 15 to d 0 t 2 t c1 t 1 t c2 t c1 pb4/pb5 ( ucas / lcas ) note: n = 2 to 5 dram access dram access external space access figure 6.23 example of operation timing in ras up mode 6. bus controller rev.5.00 sep. 12, 2007 page 160 of 764 rej09b0396-0500 6.5.11 refresh control the h8/3006 and h8/3007 are provided with a cas-before-ras (cbr) function and self-refresh function as dram refresh control functions. cas-before-ras (cbr) refreshing: to select cbr refreshing, set the rcyce bit to 1 in drcrb. with cbr refreshing, rtcnt counts up using the input clock selected by bits cks2 to cks0 in rtmcsr, and a refresh request is generated when the count matches the value set in rtcor (compare match). at the same time, rtcnt is reset and starts counting up again from h'00. refreshing is thus repeated at fixed intervals determined by rtcor and bits cks2 to cks0. a refresh cycle is executed after this refresh reque st has been accepted and the dram interface has acquired the bus. set a value in bits cks2 to cks0 in rtcor that will meet the refresh interval specification for the dram used. when ras down mode is used, set the refresh interval so that the maximum ras pulse width specification is met. rtcnt starts counting up when bits cks2 to cks0 are set. rtcnt and rtcor settings should therefore be completed before setting bits cks2 to cks0. also note that a repeat refresh request generate d during a bus request, or a refresh request during refresh cycle execution, will be ignored. rtcnt operation is shown in figure 6.24, compare match timing in figure 6.25, and cbr refresh timing in figures 6.26 and 6.27. rtcnt rtcor h'00 refresh request figure 6.24 rtcnt operation 6. bus controller rev.5.00 sep. 12, 2007 page 161 of 764 rej09b0396-0500 n n h'00 rtcnt rtcor refresh request si g nal and cmf bit settin g si g nal figure 6.25 compare match timing t rp t r1 t r2 cs n ( ras ) ( ucas / lcas ) pb4/pb5 rd ( we ) rfsh as address bus area 2 start address hi g h hi g h figure 6.26 cbr refresh timing (csel = 0, tpc = 0, rlw = 0) the basic cbs refresh cycle timing comprise s three states: one ras precharge cycle (t rp ) state, and two ras output cycle (t r1 , t r2 ) states. either one or two stat es can be selected for the ras precharge cycle. when the tpc bit is set to 1 in drcrb, ras signal output is delayed by one cycle. this does not affect the timing of ucas and lcas output. 6. bus controller rev.5.00 sep. 12, 2007 page 162 of 764 rej09b0396-0500 use the rlw bit in drcrb to adjust the ras signal width. a single refresh wait state (t rw ) can be inserted between the t r1 state and t r2 state by setting the rlw bit to 1. the rlw bit setting is valid only for cbr refresh cycles, and does not affect dram read/write cycles. the number of states in the cbr refresh cy cle is not affected by the settings in astcr, wcrh, or wcrl, or by the state of the wait pin. figure 6.27 shows the timing when the tpc bit and rlw bit are both set to 1. t rp1 t rp2 t r1 t rw rd ( we ) cs n ( ras ) ( ucas / lcas ) pb4/pb5 t r2 rfsh as address bus area 2 start address hi g h hi g h figure 6.27 cbr refresh timing (csel = 0, tpc = 1, rlw = 1) dram must be refreshed immediately after poweri ng on in order to stabilize its internal state. when using the h8/3006 and h8/3007 cas-before-ras refresh function, therefore, a dram stabilization period should be provided by means of interrupts by another timer module, or by counting the number of times bit 7 (cmf) of rtmcsr is set, for instance, immediately after bits dras2 to dras0 have been set in drcra. 6. bus controller rev.5.00 sep. 12, 2007 page 163 of 764 rej09b0396-0500 self-refreshing: a self-refresh mode (battery backup mode) is provided for dram as a kind of standby mode. in this mode, refresh timing and refresh addresses are generated within the dram. the h8/3006 and h8/3007 have a function that places the dram in self-refresh mode when the chip enters software standby mode. to use the self-refresh function, set the srfmd b it to 1 in drcra. when a sleep instruction is subsequently executed in order to enter software standby mode, the cas and ras signals are output and the dram enters self-refresh mode, as shown in figure 6.28. when the chip exits software standby mode, cas and ras outputs go high. the following conditions must be observed when the self-refresh function is used: ? when burst access is selected, ras up mode mu st be selected before executing a sleep instruction in order to enter software standby mode. therefore, if ras down mode has been selected, the rdm bit in drcra must be clear ed to 0 and ras up mode selected before executing the sleep instruction. select ras down mode again after exiting software standby mode. ? the instruction immediat ely following a sleep instruction mu st not be located in an area designated as dram space. the self-refresh function will not work proper ly unless the above conditions are observed. cs n ( ras ) address bus pb4 ( ucas ) pb5 ( lcas ) rd ( we ) rfsh software standby mode oscillation stabilization time hi g h-impedance figure 6.28 self-refresh timing (csel = 0) 6. bus controller rev.5.00 sep. 12, 2007 page 164 of 764 rej09b0396-0500 refresh signal ( rfsh ): a refresh signal ( rfsh ) that transmits a refresh cycle off-chip can be output by setting the rfshe bit to 1 in drcra. rfsh output timing is shown in figures 6.26, 6.27, and 6.28. 6.5.12 examples of use examples of dram connection and program setup procedures are shown below. when the dram interface is used, check the dram device characteristics and choose the most appropriate method of use for that device. 6. bus controller rev.5.00 sep. 12, 2007 page 165 of 764 rej09b0396-0500 connection examples ? figure 6.29 shows typical interconnections when using two 2-cas type 16-mbit drams using a 16-bit organization, and the corresponding address map. the drams used in this example are of the 10-bit row address 10-bit column address type. up to four drams can be connected by designating areas 2 to 5 as dram space. cs2 ( ras2 ) cs3 ( ras3 ) rd ( we ) a10-a1 d15-d0 a9-a0 d15-d0 pb4 ( ucas ) pb5( lcas ) ras we ucas lcas a9-a0 d15-d0 ras we ucas lcas no.1 no.2 oe oe dram (no. 1) h'400000 h'5ffffe h'600000 h'7ffffe h'800000 h'9ffffe h'a00000 h'bffffe dram (no. 2) normal normal cs2 ( ras2 ) cs3 ( ras3 ) cs4 cs5 pb4 ( ucas ) pb5 ( lcas ) 15 0 7 8 h8/3006 and h8/3007 2-cas 16-mbit dram 10-bit row address 10-bit column address 16-bit or g anization (a) interconnections (example) (b) address map area 2 area 3 area 4 area 5 figure 6.29 interconnections and add ress map for 2-cas 16-mbit drams with 16-bit organization 6. bus controller rev.5.00 sep. 12, 2007 page 166 of 764 rej09b0396-0500 ? figure 6.30 shows typical interconnections when using two 16-mbit drams using a 8-bit organization, and the corresponding address map. the drams used in this example are of the 11-bit row address 10-bit column address type. the cs2 pin is used as a common ras output pin for area 2 and area 3. when the dram address space spans a number of contiguous areas, as in this example, th e appropriate setting of bits dras2 to dras0 enables a single cs pin to be used as the common ras output pin for a number of areas, and makes it possible to directly connect large-capacity dram with address space that spans a maximum of four areas. any unused cs pins (in this example, the cs 3 pin) can be used as input/output ports. cs2 ( ras2 ) rd ( we ) a21, a10-a1 d15-d8 d7-d0 a10-a0 d7-d0 pb4 ( ucas ) pb5 ( lcas ) ras we cas a10-a0 d7-d0 ras we cas no.1 no.2 oe oe dram (no.1) h'400000 h'5ffffe h'600000 h'7ffffe h'800000 h'9ffffe h'a00000 h'bffffe dram (no.2) cs2 ( ras2 ) cs4 cs5 pb4 ( ucas ) pb5 ( lcas ) 15 0 7 8 h8/3006 and h8/3007 2-cas 16-mbit dram 11-bit row address 10-bit column address 8-bit or g anization (a) interconnections (example) (b) address map 16-mbyte mode area 2 area 3 area 4 area 5 normal normal figure 6.30 interconnections and ad dress map for 16-mbit drams with 8-bit organization 6. bus controller rev.5.00 sep. 12, 2007 page 167 of 764 rej09b0396-0500 ? figure 6.31 shows typical interconnections when using two 4-mbit drams, and the corresponding address map. the drams used in this example are of the 9-bit row address 9-bit column address type. in this example, upper address decoding allows multiple drams to be connected to a single area. the rfsh pin is used in this case, since both drams must be refreshed simultaneously. however, note that ras down mode cannot be used in this interconnection example. cs2 ( ras2 ) rd ( we ) a9-a1 d15-d0 a8-a0 d15-d0 pb4 ( ucas ) pb5 ( lcas ) ras we ucas lcas a8-a0 d15-d0 ras we ucas lcas no.1 no.2 oe oe dram (no.1) h'400000 h'47fffe h'480000 h'4ffffe h'500000 h'5ffffe dram (no.2) not used (a) interconnections (example) cs2 ( ras2 ) pb4 ( ucas ) pb5 ( lcas ) 15 0 7 8 area 2 16-mbyte mode (b) address map h8/3006 and h8/3007 2-cas 4-mbit dram 9-bit row address 9-bit column address 16-bit or g anization rfsh a19 figure 6.31 interconnections and add ress map for 2-cas 4-mbit drams with 16-bit organization 6. bus controller rev.5.00 sep. 12, 2007 page 168 of 764 rej09b0396-0500 example of program setup procedure: figure 6.32 shows an example of the program setup procedure. set abwcr set rtcor set bits cks2 to cks0 in rtmcsr set drcrb set drcra wait for dram stabilization time dram can be accessed figure 6.32 example of setup pro cedure when using dram interface 6.5.13 usage notes note the following points when using the dram refresh function. ? refresh cycles will not be exec uted when the external bus re leased state, software standby mode, or a bus cycle is extended by means of wa it state insertion. refreshing must therefore be performed by other means in these cases. ? if a refresh request is generated internally while th e external bus is released, the first request is retained and a single refresh cycle will be ex ecuted after the bus-released state is cleared. figure 6.33 shows the bus cycle in this case. ? when a bus cycle is extended by means of wait stat e insertion, the first request is retained in the same way as when the external bus has been released. in the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the back and strobe states may be indeterminate after the transition to software standby mode (see figure 6.34). when software standby mode is used, the brle bit should be cleared to 0 in brcr before executing the sleep instruction. 6. bus controller rev.5.00 sep. 12, 2007 page 169 of 764 rej09b0396-0500 similar contention in a transition to self-refresh mode may prevent dependable strobe waveform output. this can also be avoided by clearing the brlw bit to 0 in brcr. ? immediately after self-refreshing is cleared, ex ternal bus release is possible during a given period until the start of a cpu cycle. attention must be paid to the ras state to ensure that the specification for the ras precharge time immediately after self-refreshing is met. rfsh refresh request back external bus released refresh cycle cpu cycle refresh cycle figure 6.33 bus-released state and refresh cycles breq back software standby mode address bus strobe figure 6.34 bus-released state and software standby mode 6. bus controller rev.5.00 sep. 12, 2007 page 170 of 764 rej09b0396-0500 @sp ras cas oscillation stabilization time on exit from software standby mode cpu internal cycle (period in which external bus can be released) cpu cycle address bus figure 6.35 self-refresh clearing 6.6 interval timer 6.6.1 operation when dram is not connected to the h8/3006 and h8/3007 chip, the refresh timer can be used as an interval timer by clearing bits dras2 to dras0 in drcra to 0. after setting rtcor, selection a clock source with bits cks2 to cks0 in rtmcsr, and set the cmie bit to 1. timing of setting of compare match flag and clearing by compare match: the cmf flag in rtmcsr is set to 1 by a compare match output when the rtcor and rtcnt values match. the compare match signal is generated in the last state in which the values match (when rtcnt is updated from the matching value to a new value). accordingly, when rtcnt and rtcor match, the compare match signal is not generate d until the next counter clock pulse. figure 6.36 shows the timing. 6. bus controller rev.5.00 sep. 12, 2007 page 171 of 764 rej09b0396-0500 n n h'00 rtcnt cmf rtcor compare match si g nal figure 6.36 timing of cmf flag setting operation in pow er-down state: the interval timer operates in sleep mode. it does not operate in hardware standby mode. in software standby mode, rtcnt and rtmcsr bits 7 and 6 are initialized, but rtmcsr bits 5 to 3 and rtcor retain their settings prior to the transition to software standby mode. contention between rtcnt write and co unter clear: if a counter clear signal occurs in the t 3 state of an rtcnt write cycle, clearing of th e counter takes priority and the write is not performed. see figure 6.37. h'00 rtcnt address bus internal write si g nal counter clear si g nal t 1 t 2 t 3 n rtcnt address figure 6.37 contention be tween rtcnt write and clear 6. bus controller rev.5.00 sep. 12, 2007 page 172 of 764 rej09b0396-0500 contention between rtcnt write and increment: if an increment puls e occurs in the t 3 state of an rtcnt write cycle, writing takes priority and rtcnt is not incremented. see figure 6.38. m rtcnt t 1 t 2 t 3 n address bus rtcnt address internal write si g nal rtcnt input clock counter write data figure 6.38 contention betw een rtcnt write and increment contention between rtcor write and compare match: if a compare match occurs in the t 3 state of an rtcor write cycle, writing takes priority and the compare match signal is inhibited. see figure 6.39. 6. bus controller rev.5.00 sep. 12, 2007 page 173 of 764 rej09b0396-0500 m rtcor compare match si g nal t 1 t 2 t 3 n n+1 n rtcnt internal write si g nal address bus rtcor address rtcor write data inhibited figure 6.39 contention between rtcor write and compare match rtcnt operation at internal clock source switchover: switching internal clock sources may cause rtcnt to increment, depending on the switchover timing. table 6.10 shows the relation between the time of the switchove r (by writing to bits cks2 to cks0) and the operation of rtcnt. the rtcnt input clock is generated from the internal clock source by detecting the falling edge of the internal clock. if a switchover is made from a high clock source to a low clock source, as in case no. 3 in table 6.10, the switchover will be re garded as a falling edge, an rtcnt clock pulse will be generated, and rtcnt will be incremented. 6. bus controller rev.5.00 sep. 12, 2007 page 174 of 764 rej09b0396-0500 table 6.10 internal clock sw itchover and rtcnt operation n n+1 no. 1 n n+1 2 n+2 cks2 to cks0 write timing rtcnt operation low low switchover * 1 low high switchover * 2 old clock source new clock source rtcnt clock rtcnt old clock source new clock source rtcnt clock rtcnt cks bits rewritten cks bits rewritten 6. bus controller rev.5.00 sep. 12, 2007 page 175 of 764 rej09b0396-0500 n n+1 no. 3 n n+1 rtcnt 4 n+2 n+2 * 4 cks2 to cks0 write timing rtcnt operation high low switchover * 3 high high switchover * 4 old clock source new clock source rtcnt clock rtcnt old clock source new clock source rtcnt clock cks bits rewritten cks bits rewritten notes: 1. including switchovers from a low clock so urce to the halted state, and from the halted state to a low clock source. 2. including switchover from the halted state to a high clock source. 3. including switchover from a high clock source to the halted state. 4. the switchover is regarded as a falling edge, causing rtcnt to increment. 6.7 interrupt sources compare match interrupts (cmi) can be generated wh en the refresh timer is used as an interval timer. compare match interrupt requests are masked/unmasked with the cmie bit in rtmcsr. 6. bus controller rev.5.00 sep. 12, 2007 page 176 of 764 rej09b0396-0500 6.8 burst rom interface 6.8.1 overview with the h8/3006 and h8/3007, external space area 0 can be designated as burst rom space, and burst rom space interfacing can be performed. the burst rom interface enables rom with burst access capability to be accessed at high speed. area 0 is designated as burst rom space by means of the brome bit in bcr. continuous burst access of a maximum or four or eight words can be performed on external space area 0. two or three states can be selected for burst access. 6.8.2 basic timing the number of states in the ini tial cycle (full access) and a burst cycle of the burst rom interface is determined by the setting of the ast0 bit in as tcr. when the ast0 bit is set to 1, wait states can also be inserted in the initial cycle. wait states cannot be inserted in a burst cycle. burst access of up to four words is performed when the brsts0 bit is cleared to 0 in bcr, and burst access of up to eight words when the brsts0 bit is set to 1. the number of burst access states is two when the brsts1 b it is cleared to 0, and three when the brsts1 bit is set to 1. the basic access timing for burst rom space is shown in figure 6.40. 6. bus controller rev.5.00 sep. 12, 2007 page 177 of 764 rej09b0396-0500 t 1 t 2 t 3 t 1 t 2 t 1 t 2 rd as cs 0 full access burst access address bus only lower address chan g es read data read data read data data bus figure 6.40 example of burst rom access timing 6.8.3 wait control as with the basic bus interface, either program wait insertion or pin wait insertion using the wait pin can be used in the initial cycle (full access) of the burst rom interface. wait states cannot be inserted in a burst cycle. 6. bus controller rev.5.00 sep. 12, 2007 page 178 of 764 rej09b0396-0500 6.9 idle cycle 6.9.1 operation when the h8/3006 and h8/3007 chip accesses external space, it can insert a 1-state idle cycle (t i ) between bus cycles in the following cases: (1) wh en read accesses between different areas occur consecutively, (2) when a write cycle occurs immedi ately after a read cycle, and (3) when external address space other than dram space is accesse d immediately after a dram space access. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, which has a long output floating time, and high-speed memo ry, i/o interfaces, and so on. the icis1 and icis0 bits in bcr both have an initial value of 1, so that an idle cycle is inserted in the initial state. if there are no data collisions, the icis bits can be cleared. consecutive reads betw een different areas: if consecutive reads between different areas occur while the icis1 bit is set to 1 in bcr, an idle cycle is inserted at the start of the second read cycle. figure 6.41 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an id le cycle is not inserted, and a collision occurs in cycle b between the read data from rom and that from sram. in (b ), an idle cycle is inserted, and a data collision is prevented. t 1 t 2 t 3 rd t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 address bus data bus rd address bus data bus bus cycle a bus cycle b bus cycle a bus cycle b data collision lon g buffer-off time (a) idle cycle not inserted (b) idle cycle inserted figure 6.41 example of idle cycle operation (1) (icis1 = 1) write after read: if an external write occurs after an external read while the icis0 bit is set to 1 in bcr, an idle cycle is inserted at the start of the write cycle. figure 6.42 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating tim e, and bus cycle b is a cpu write cycle. 6. bus controller rev.5.00 sep. 12, 2007 page 179 of 764 rej09b0396-0500 in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 t 2 t 3 rd address bus data bus t 1 t 2 t 1 t 2 t 3 t i t 2 t 1 hwr rd address bus data bus hwr bus cycle a bus cycle b bus cycle a bus cycle b lon g buffer-off time data collision (a) idle cycle not inserted (b) idle cycle inserted figure 6.42 example of idle cycle operation (2) (icis0 = 1) external address space access imme diately after dram space access: if a dram space access is followed by a non-dram external access when hwr and lwr have been selected as the ucas and lcas output pins by means of the csel bit in drcrb, a ti cycle is inserted regardless of the settings of bits icis0 and icis1 in bcr. figure 6.43 shows an example of the operation. this is done to prevent simultaneous changing of the hwr and lwr signals used as ucas and lcas in dram space and cs n for the space in the next cycle, and so avoid an erroneous write to the external device in the next cycle. a t i cycle is not inserted when pb4 a nd pb5 have been selected as the ucas and lcas output pins. in the case of consecutive dram space access prech arge cycles (tp), the icis0 and icis1 bit settings are invalid. in the case of consecutive read s between different areas, for example, if the second access is a dram access, only a t p cycle is inserted, and a t i cycle is not. the timing in this case is shown in figure 6.44. 6. bus controller rev.5.00 sep. 12, 2007 page 180 of 764 rej09b0396-0500 address bus simultaneous chan g e of hwr / lwr and csn t p t r t c1 t c2 bus cycle a (dram access cycle) hwr / lwr ( ucas / lcas ) t 1 t 2 bus cycle b csn t p t r t c1 t c2 t 1 t i t 2 address bus hwr / lwr ( ucas / lcas ) csn bus cycle a (dram access cycle) bus cycle b (a) idle cycle not inserted (b) idle cycle inserted figure 6.43 example of idle cycle operation (3) ( hwr / lwr used as ucas / lcas ) address bus t 1 t 2 t 3 address bus ucas / lcas rd t p t c1 t r t c2 external read dram space read figure 6.44 example of id le cycle operation (4) (con secutive precharge cycles) usage notes: when non-insertion of idle cycles is set, the rise (negation) of rd and the fall (assertion) of csn may occur simultaneously. an example of the operation is shown in figure 6.45. if consecutive reads between differen t external areas occur while the icis1 bit is cleared to 0 in bcr, or if a write cycle to a di fferent external area occurs after an external read while the icis0 bit is cleared to 0, the rd negation in the first read cycle and the csn assertion in the following bus cycle will occur simultaneously. therefore, depending on the output delay time of each signal, it is possible that the low-level output of rd in the preceding read cycl e and the low-level output of csn in the following bus cycle will overlap. 6. bus controller rev.5.00 sep. 12, 2007 page 181 of 764 rej09b0396-0500 a setting whereby idle cycle insertion is not performed can be made only when rd and csn do not change simultaneously, or when it does not matter if they do. address bus t 1 t 2 t 3 bus cycle a rd t 1 t 2 (a) idle cycle not inserted t 1 t 2 t 3 t i t 2 (b) idle cycle inserted t 1 simultaneous chan g e of rd and csn possibility of mutual overlap csn address bus rd csn bus cycle b bus cycle a bus cycle b figure 6.45 example of idle cycle operation (5) 6.9.2 pin states in idle cycle table 6.11 shows the pin states in an idle cycle. table 6.11 pin states in idle cycle pins pin state a 23 to a 0 next cycle address value d 15 to d 0 high impedance cs n high * ucas , lcas high as high rd high hwr high lwr high note: * remains low in dram space ras down mode. 6. bus controller rev.5.00 sep. 12, 2007 page 182 of 764 rej09b0396-0500 6.10 bus arbiter the bus controller has a built-in bus arbiter that arbitrates between different bus masters. there are four bus masters: the cpu, dma controller (d mac), dram interface, and an external bus master. when a bus master has the bus right it can carry out read, write, or refresh access. each bus master uses a bus request signal to request the bus right. at fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can the operate using the bus. the bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master. when two or more bus masters request the bus, the highest-priority bus master receives an acknowl edge signal. the bus master that receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. the bus master priority order is: (high) external bus master > dram interface > dmac > cpu (low) the bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request from a bus master with higher priority than the current bus master. each bus master has certain times at which it can release the bus to a higher-priority bus master. 6.10.1 operation cpu: the cpu is the lowest-priority bus master. if the dmac, dram interface, or an external bus master requests the bus while the cpu has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. the bus right is transferred at the following times: ? the bus right is transferred at the boundary of a bus cycle. if word data is accessed by two consecutive byte accesses, however, the bus right is not transferred between the two byte accesses. ? if another bus master requests the bus while the cpu is performing internal operations, such as executing a multiply or divide instruction, the bus right is transferred immediately. the cpu continues its internal operations. ? if another bus master requests the bus while the cpu is in sleep mode, the bus right is transferred immediately. 6. bus controller rev.5.00 sep. 12, 2007 page 183 of 764 rej09b0396-0500 dmac: when the dmac receives an activation requ est, it requests the bus right from the bus arbiter. if the dmac is bus master and the dram in terface or an external bus master requests the bus, the bus arbiter transfers the bus right from th e dmac to the bus master that requested the bus. the bus right is transferred at the following times. the bus right is transferred when the dmac fini shes transferring one byte or one word. a dmac transfer cycle consists of a read cycle and a write cycle. the bus right is not transferred between the read cycle and the write cycle. there is a priority order among the dmac cha nnels. for details see section 7.4.9, multiple- channel operation. dram interface: the dram interface requests the bus right from the bus arbiter when a refresh cycle request is issued, and releases the bus at th e end of the refresh cycle. for details see section 6.5, dram interface. external bus master: when the brle bit is set to 1 in brcr, the bus can be released to an external bus master. the external bus master has highest priority, and requests the bus right from the bus arbiter y driving the breq signal low. once the external bus master acquires the bus, it keeps the bus until the breq signal goes high. while the bus is released to an external bus master, the h8/3006 and h8/3007 chip holds the address bus, data bus, bus control signals ( as , rd , hwr , and lwr ), and chip select signals ( cs n: n = 7 to 0) in the high-impedance state, and holds the back pin in the low output state. the bus arbiter samples the breq pin at the rise of the system clock ( ). if breq is low, the bus is released to the external bus mast er at the appropriate opportunity. the breq signal should be held low until the back signal goes low. when the breq pin is high in two consecutive samples, the back pin is driven high to end the bus-release cycle. figure 6.46 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state access ar ea. there is a minimum interval of three states from when the breq signal goes low until the bus is released. 6. bus controller rev.5.00 sep. 12, 2007 page 184 of 764 rej09b0396-0500 rd back (1) (2) (3) (4) (5) (6) breq hwr , lwr t 0 t 1 t 2 as data bus address bus cpu cycles cpu cycles external bus released hi g h address minimum 3 cycles hi g h-impedance hi g h-impedance hi g h-impedance hi g h-impedance hi g h-impedance figure 6.46 example of external bus master operation in the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the back and strobe states may be indeterminate after the transition to software standby mode (see figure 6.34). when software standby mode is used, the brle bit should be cleared to 0 in brcr before executing the sleep instruction. 6. bus controller rev.5.00 sep. 12, 2007 page 185 of 764 rej09b0396-0500 6.11 register and pin input timing 6.11.1 register write timing abwcr, astcr, wcrh, and wcrl write timing: data written to abwcr, astcr, wcrh, and wcrl takes effect starting from the next bus cycle. figure 6.47 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. t 1 t 2 t 3 t 1 t 2 t 3 t 1 t 2 address bus 3-state access to area 0 2-state access to area 0 astcr address figure 6.47 astcr write timing ddr and cscr write timing: data written to ddr or cscr for the port corresponding to the cs n pin to switch between cs n output and generic input takes effect starting from the t 3 state of the ddr write cycle. figure 6. 48 shows the timing when the cs 1 pin is changed from generic input to cs 1 output. t 1 t 2 t 3 cs 1 address bus hi g h-impedance p8ddr address figure 6.48 ddr write timing 6. bus controller rev.5.00 sep. 12, 2007 page 186 of 764 rej09b0396-0500 brcr write timing: data written to brcr to switch between a 23 , a 22 , a 21 , or a 20 output and generic input or output takes effect starting from the t 3 state of the brcr write cycle. figure 6.49 shows the timing when a pin is changed from generic input to a 23 , a 22 , a 21 , or a 20 output. t 1 t 2 t 3 pa 7 to pa 4 ( a 23 to a 20 ) address bus brcr address hi g h-impedance figure 6.49 brcr write timing 6.11.2 breq pin input timing after driving the breq pin low, hold it low until back goes low. if breq returns to the high level before back goes lows, the bus arbiter may operate incorrectly. to terminate the external-b us-released state, hold the breq signal high for at least three states. if breq is high for too short an interval, th e bus arbiter may operate incorrectly. 7. dma controller rev.5.00 sep. 12, 2007 page 187 of 764 rej09b0396-0500 section 7 dma controller 7.1 overview the h8/3006 and h8/3007 have an on-chip dma controller (dmac) that can transfer data on up to four channels. when the dma controller is not used, it can be independently halted to conserve power. for details see section 19.6, module standby function. 7.1.1 features dmac features are listed below. ? selection of short address mode or full address mode short address mode ? 8-bit source address and 24-bit destination address, or vice versa ? maximum four channels available ? selection of i/o mode, idle mode, or repeat mode full address mode ? 24-bit source and destination addresses ? maximum two channels available ? selection of normal mode or block transfer mode ? directly addressable 16-mbyte address space ? selection of byte or word transfer ? activation by internal interrupts, external requests, or auto-request (depending on transfer mode) ? 16-bit integrated timer unit (itu) compare match/input capture interrupts ( 3) ? serial communication interfac e (sci channel 0) transmit- data-empty/receive-data-full interrupts ? external requests ? auto-request ? a/d converter conversion-end interrupt 7. dma controller rev.5.00 sep. 12, 2007 page 188 of 764 rej09b0396-0500 7.1.2 block diagram figure 7.1 shows a dmac block diagram. imia0 imia1 imia2 adi txi0 rxi0 dreq 0 dreq 1 tend 0 tend 1 dend0a dend0b dend1a dend1b dtcr0a dtcr0b dtcr1a dtcr1b control lo g ic data buffer address buffer arithmetic-lo g ic unit mar0a mar0b mar1a mar1b ioar0a ioar0b ioar1a ioar1b etcr0a etcr0b etcr1a etcr1b internal address bus internal interrupts interrupt si g nals internal data bus module data bus le g end: dtcr: mar: ioar: etcr: data transfer control re g ister memory address re g ister i/o address re g ister execute transfer count re g ister channel 0a channel 0b channel 1a channel 1b channel 0 channel 1 figure 7.1 block diagram of dmac 7.1.3 functional overview table 7.1 gives an overview of the dmac functions. 7. dma controller rev.5.00 sep. 12, 2007 page 189 of 764 rej09b0396-0500 table 7.1 dmac functional overview address reg. length transfer mode activation source destina- tion short address mode i/o mode ? transfers one byte or one word per request ? increments or decrements the memory address by 1 or 2 ? executes 1 to 65,536 transfers ? compare match/input capture a interrupts from 16-bit timer channels 0 to 2 ? transmit-data-empty interrupt from sci channel 0 24 8 idle mode ? transfers one byte or one word per request ? holds the memory address fixed ? conversion-end interrupt from a/d converter ? receive-data-full interrupt from sci channel 0 8 24 ? executes 1 to 65,536 transfers repeat mode ? transfers one byte or one word per request ? increments or decrements the memory address by 1 or 2 ? executes a specified number (1 to 255) of transfers, then returns to the initial state and continues ? external request 24 8 full address mode normal mode ? auto-request ? retains the transfer request internally ? executes a specified number(1 to 65,536) of transfers continuously ? selection of burst mode or cycle- steal mode ? external request ? transfers one byte or one word per request ? executes 1 to 65,536 transfers ? auto-request ? external request 24 24 block transfer ? transfers one block of a specified size per request ? executes 1 to 65,536 transfers ? allows either the source or destination to be a fixed block area ? block size can be 1 to 255 bytes or words ? compare match/ input capture a interrupts from 16-bit timer channels 0 to 2 ? external request ? conversion-end interrupt from a/d converter 24 24 7. dma controller rev.5.00 sep. 12, 2007 page 190 of 764 rej09b0396-0500 7.1.4 pin configuration table 7.2 lists the dmac pins. table 7.2 dmac pins channel name abbrevia- tion input/ output function 0 dma request 0 dreq 0 input external request for dmac channel 0 transfer end 0 tend 0 output transfer end on dmac channel 0 1 dma request 1 dreq 1 input external request for dmac channel 1 transfer end 1 tend 1 output transfer end on dmac channel 1 note: external requests cannot be made to channel a in short address mode. 7.1.5 register configuration table 7.3 lists the dmac registers. table 7.3 dmac registers channel address * name abbreviation r/w initial value 0 h'fff20 memory address register 0ar mar0ar r/w undetermined h'fff21 memory address register 0ae mar0ae r/w undetermined h'fff22 memory address register 0ah mar0ah r/w undetermined h'fff23 memory address register 0al mar0al r/w undetermined h'fff26 i/o address register 0a ioar0a r/w undetermined h'fff24 execute transfer count register 0ah etcr0ah r/w undetermined h'fff25 execute transfer count register 0al etcr0al r/w undetermined h'fff27 data transfer control register 0a dtcr0a r/w h'00 h'fff28 memory address register 0br mar0br r/w undetermined h'fff29 memory address register 0be mar0be r/w undetermined h'fff2a memory address register 0bh mar0bh r/w undetermined h'fff2b memory address register 0bl mar0bl r/w undetermined h'fff2e i/o address register 0b ioar0b r/w undetermined h'fff2c execute transfer count register 0bh etcr0bh r/w undetermined h'fff2d execute transfer count register 0bl etcr0bl r/w undetermined h'fff2f data transfer control register 0b dtcr0b r/w h'00 7. dma controller rev.5.00 sep. 12, 2007 page 191 of 764 rej09b0396-0500 channel address * name abbreviation r/w initial value 1 h'fff30 memory address register 1ar mar1ar r/w undetermined h'fff31 memory address register 1ae mar1ae r/w undetermined h'fff32 memory address register 1ah mar1ah r/w undetermined h'fff33 memory address register 1al mar1al r/w undetermined h'fff36 i/o address register 1a ioar1a r/w undetermined h'fff34 execute transfer count register 1ah etcr1ah r/w undetermined h'fff35 execute transfer count register 1al etcr1al r/w undetermined h'fff37 data transfer control register 1a dtcr1a r/w h'00 h'fff38 memory address register 1br mar1br r/w undetermined h'fff39 memory address register 1be mar1be r/w undetermined h'fff3a memory address register 1bh mar1bh r/w undetermined h'fff3b memory address register 1bl mar1bl r/w undetermined h'fff3e i/o address register 1b ioar1b r/w undetermined h'fff3c execute transfer count register 1bh etcr1bh r/w undetermined h'fff3d execute transfer count register 1bl etcr1bl r/w undetermined h'fff3f data transfer control register 1b dtcr1b r/w h'00 note: * the lower 20 bits of the address are indicated. 7.2 register descriptions (1 ) (short address mode) in short address mode, transfers can be carried out independently on channels a and b. short address mode is selected by bits dts2a and dts1a in data transfer control register a (dtcra) as indicated in table 7.4. table 7.4 selection of short and full address modes channel bit 2 dts2a bit 1 dts1a description 0 1 1 dmac channel 0 operates as one channel in full address mode other than above dmac channels 0a and 0b operate as two independent channels in short address mode 1 1 1 dmac channel 1 operates as one channel in full address mode other than above dmac channels 1a and 1b operate as two independent channels in short address mode 7. dma controller rev.5.00 sep. 12, 2007 page 192 of 764 rej09b0396-0500 7.2.1 memory address registers (mar) a memory address register (mar) is a 32-bit readab le/writable register that specifies a source or destination address. the transfer direction is determined automatically from the activation source. an mar consists of four 8-bit registers designated marr, mare, marh, and marl. all bits of marr are reserved; they cannot be modified and are always read as 1. bit initial value read/write 31 1 ? source or destination address 30 1 ? 29 1 ? 28 1 ? 27 1 ? 26 1 ? 25 1 ? 24 1 ? 23 r/w 22 r/w 21 r/w 20 r/w 19 r/w 18 r/w 17 r/w 16 r/w 15 r/w 14 r/w 13 r/w 12 r/w 11 undetermined r/w 10 r/w 9 r/w 8 r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 r/w marr mare marh marl an mar functions as a source or destination address register depending on how the dmac is activated: as a destination address register if ac tivation is by a receive-data-full interrupt from the serial communication interface (sci) (channel 0) or by a conversion-end interrupt from the a/d converter, and as a source address register otherwise. the mar value is incremented or decremented each time one byt e or word is transferred, automatically updating the source or destination me mory address. for details, see section 7.3.4, data transfer control registers (dtcr). the mars are not initialized by a reset or in standby mode. 7.2.2 i/o address registers (ioar) an i/o address register (ioar) is an 8-bit read able/writable register that specifies a source or destination address. the ioar value is the lower 8 bits of the address. the upper 16 address bits are all 1 (h'ffff). bit initial value read/write 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 0 r/w 2 r/w 1 r/w source or destination address undetermined an ioar functions as a source or destination address register depending on how the dmac is activated: as a source address regi ster if activation is by a receive-data-full interrupt from the sci 7. dma controller rev.5.00 sep. 12, 2007 page 193 of 764 rej09b0396-0500 (channel 0) or by a conversion-end interrupt from the a/d converter, and as a destination address register otherwise. the ioar value is held fixed. it is not incremen ted or decremented when a transfer is executed. the ioars are not initialized by a reset or in standby mode. 7.2.3 execute transfer count registers (etcr) an execute transfer count register (etcr) is a 16- bit readable/writable regi ster that specifies the number of transfers to be executed. these registers function in one way in i/o mode and idle mode, and another way in repeat mode. i/o mode and idle mode bit initial value read/write 14 r/w 12 r/w 10 r/w 8 r/w 6 r/w 0 r/w 4 r/w 2 r/w transfer counter undetermined 15 r/w 13 r/w 11 r/w 9 r/w 7 r/w 1 r/w 5 r/w 3 r/w in i/o mode and idle mode, etcr functions as a 16-bit counter. the count is decremented by 1 each time one transfer is ex ecuted. the transfer ends when the count reaches h'0000. 7. dma controller rev.5.00 sep. 12, 2007 page 194 of 764 rej09b0396-0500 repeat mode bit initial value read/write 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 0 r/w 2 r/w 1 r/w undetermined transfer counter etcrh bit initial value read/write 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 0 r/w 2 r/w 1 r/w undetermined initial count etcrl in repeat mode, etcrh functions as an 8-bit transfer counter and etcrl holds the initial transfer count. etcrh is decremented by 1 each time one transfer is executed. when etcrh reaches h'00, the value in etcrl is reloaded into etcrh and the same operation is repeated. the etcrs are not initialized by a reset or in standby mode. 7. dma controller rev.5.00 sep. 12, 2007 page 195 of 764 rej09b0396-0500 7.2.4 data transfer control registers (dtcr) a data transfer control register (dtcr) is an 8- bit readable/writable register that controls the operation of one dmac channel. bit initial value read/write 7 dte 0 r/w 6 dtsz 0 r/w 5 dtid 0 r/w 4 rpe 0 r/w 3 dtie 0 r/w 0 dts0 0 r/w 2 dts2 0 r/w 1 dts1 0 r/w data transfer enable enables or disables data transfer data transfer interrupt enable enables or disables the cpu interrupt at the end of the transfer data transfer sele c t these bits select the data transfer activation source data transfer size selects byte or word size data transfer in c rement/de c rement selects whether to increment or decrement the memory address re g ister repeat enable selects repeat mode the dtcrs are initialized to h'00 by a reset and in standby mode. bit 7 ? data transfer enable (dte): enables or disables data tran sfer on a channel. when the dte bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when activated as specified by bits dts2 to dts0. when dte is 0, the channel is disabled and does not accept transfer requests. dte is set to 1 by readi ng the register when dte is 0, then writing 1. bit 7 dte description 0 data transfer is disabled. in i/o mode or idle mode, dte is cleared to 0 (initial value) when the specified number of transfers have been completed 1 data transfer is enabled if dtie is set to 1, a cpu interrupt is requested when dte is cleared to 0. 7. dma controller rev.5.00 sep. 12, 2007 page 196 of 764 rej09b0396-0500 bit 6 ? data transfer size (dtsz): selects the data size of each transfer. bit 6 dtsz description 0 byte-size transfer (initial value) 1 word-size transfer bit 5 ? data transfer increment/decrement (dtid): selects whether to increment or decrement the memory address regi ster (mar) after a data transfer in i/o mode or repeat mode. bit 5 dtid description 0 mar is incremented after each data transfer ? if dtsz = 0, mar is incremented by 1 after each transfer ? if dtsz = 1, mar is incremented by 2 after each transfer 1 mar is decremented after each data transfer ? if dtsz = 0, mar is decremented by 1 after each transfer ? if dtsz = 1, mar is decremented by 2 after each transfer mar is not incremented or decremented in idle mode. bit 4 ? repeat enable (rpe): selects whether to transfer data in i/o mode, idle mode, or repeat mode. bit 4 rpe bit 3 dtie description 0 0 i/o mode (initial value) 1 1 0 repeat mode 1 idle mode operations in these modes are described in sections 7.4.2, i/o mode, 7.4.3, idle mode, and 7.4.4, repeat mode. 7. dma controller rev.5.00 sep. 12, 2007 page 197 of 764 rej09b0396-0500 bit 3 ? data transfer interrupt enable (dtie): enables or disables the cpu interrupt (dend) requested when the dte bit is cleared to 0. bit 3 dtie description 0 the dend interrupt requested by dte is disabled (initial value) 1 the dend interrupt requested by dte is enabled bits 2 to 0 ? data transfer select (dts2 to dts0): these bits select the data transfer activation source. some of the selectable sources differ between channels a and b.* note: * see section 7.3.4, data transfer control registers (dtcr). bit 2 dts2 bit 1 dts1 bit 0 dts0 description 0 0 0 compare match/input capture a interrupt from 16-bit timer channel 0 (initial value) 1 compare match/input capture a interrupt from 16-bit timer channel 1 1 0 compare match/input capture a interrupt from 16-bit timer channel 2 1 conversion-end interrupt from a/d converter 1 0 0 transmit-data-empty interrupt from sci channel 0 1 receive-data-full interrupt from sci channel 0 1 0 falling edge of dreq input (channel b) transfer in full address mode (channel a) 1 low level of dreq input (channel b) transfer in full address mode (channel a) the same internal interrupt can be selected as an activation source for two or more channels at once. in that case the channels ar e activated in a priority order, highest-priority channel first. for the priority order, see section 7.4.9, multiple-channel operation. when a channel is enabled (dte = 1), its sel ected dmac activation source cannot generate a cpu interrupt. 7. dma controller rev.5.00 sep. 12, 2007 page 198 of 764 rej09b0396-0500 7.3 register descriptions (2) (full address mode) in full address mode the a and b channels operate together. full address mode is selected as indicated in table 7.4. 7.3.1 memory address registers (mar) a memory address register (mar) is a 32-bit readable/writable register. mara functions as the source address register of the transfer, an d marb as the destination address register. an mar consists of four 8-bit registers designated marr, mare, marh, and marl. all bits of marr are reserved; they cannot be modified and are always read as 1. (write is invalid.) bit initial value read/write 31 1 ? source or destination address 30 1 ? 29 1 ? 28 1 ? 27 1 ? 26 1 ? 25 1 ? 24 1 ? 23 r/w 22 r/w 21 r/w 20 r/w 19 r/w 18 r/w 17 r/w 16 r/w 15 r/w 14 r/w 13 r/w 12 r/w 11 r/w 10 r/w 9 r/w 8 r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 r/w marr mare marh marl undetermined the mar value is incremented or decremented each time one byt e or word is transferred, automatically updating the source or destination me mory address. for details, see section 7.3.4, data transfer control registers (dtcr). the mars are not initialized by a reset or in standby mode. 7.3.2 i/o address registers (ioar) the i/o address registers (ioars) are not used in full address mode. 7. dma controller rev.5.00 sep. 12, 2007 page 199 of 764 rej09b0396-0500 7.3.3 execute transfer count registers (etcr) an execute transfer count register (etcr) is a 16- bit readable/writable regi ster that specifies the number of transfers to be executed. the functions of these registers differ between normal mode and block transfer mode. normal mode ? etcra bit initial value read/write 14 r/w 12 r/w 10 r/w 8 r/w 6 r/w 0 r/w 4 r/w 2 r/w transfer counter undetermined 15 r/w 13 r/w 11 r/w 9 r/w 7 r/w 1 r/w 5 r/w 3 r/w ? etcrb: is not used in normal mode. in normal mode etcra functions as a 16-bit transfer counter. the count is decremented by 1 each time one transfer is execut ed. the transfer ends when the count reaches h'0000. etcrb is not used. block transfer mode ? etcra bit initial value read/write 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 0 r/w 2 r/w 1 r/w undetermined block size counter etcrah bit initial value read/write 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 0 r/w 2 r/w 1 r/w undetermined initial block size etcral 7. dma controller rev.5.00 sep. 12, 2007 page 200 of 764 rej09b0396-0500 ? etcrb bit initial value read/write 14 r/w 12 r/w 10 r/w 8 r/w 6 r/w 0 r/w 4 r/w 2 r/w block transfer counter undetermined 15 r/w 13 r/w 11 r/w 9 r/w 7 r/w 1 r/w 5 r/w 3 r/w in block transfer mode, etcrah functions as an 8-bit block size counter. etcral holds the initial block size. etcrah is decremented by 1 each time one byte or word is transferred. when the count reaches h'00, etcrah is reloaded from etcral. blocks consisting of an arbitrary number of bytes or words can be transferred repeatedly by setting the same initial block size value in etcrah and etcral. in block transfer mode etcrb functions as a 16-bit block transfer counter. etcrb is decremented by 1 each time one block is transferre d. the transfer ends when the count reaches h'0000. the etcrs are not initialized by a reset or in standby mode. 7. dma controller rev.5.00 sep. 12, 2007 page 201 of 764 rej09b0396-0500 7.3.4 data transfer control registers (dtcr) the data transfer control registers (dtcrs) are 8- bit readable/writable registers that control the operation of the dmac channels. a channel operate s in full address mode when bits dts2a and dts1a are both set to 1 in dtcra. dtcra and dt crb have different functions in full address mode. dtcra bit initial value read/write 7 dte 0 r/w 6 dtsz 0 r/w 5 said 0 r/w 4 saide 0 r/w 3 dtie 0 r/w 0 dts0a 0 r/w 2 dts2a 0 r/w 1 dts1a 0 r/w data transfer enable enables or disables data transfer enables or disables the cpu interrupt at the end of the transfer data transfer size selects byte or word size sour c e address in c rement/de c rement data transfer sele c t 2a and 1a these bits must both be set to 1 data transfer interrupt enable sour c e address in c rement/ de c rement enable these bits select whether the source address re g ister (mara) is incremented, decremented, or held fixed durin g the data transfer selects block transfer mode data transfer sele c t 0a dtcra is initialized to h'00 by a reset and in standby mode. 7. dma controller rev.5.00 sep. 12, 2007 page 202 of 764 rej09b0396-0500 bit 7 ? data transfer enable (dte): together with the dtme bit in dtcrb, this bit enables or disables data transfer on the channel. when the dtme and dte bits are both set to 1, the channel is enabled. if auto-request is specified, da ta transfer begins immediately. otherwise, the channel waits for transfers to be requested. when the specified number of transfers have been completed, the dte bit is automatically cleared to 0. when dte is 0, the channel is disabled and does not accept transfer requests. dte is set to 1 by reading the register when dte is 0, then writing 1. bit 7 dte description 0 data transfer is disabled (dte is cleared to 0 when the specified number (initial value) of transfers have been completed) 1 data transfer is enabled if dtie is set to 1, a cpu interrupt is requested when dte is cleared to 0. bit 6 ? data transfer size (dtsz): selects the data size of each transfer. bit 6 dtsz description 0 byte-size transfer (initial value) 1 word-size transfer bit 5 ? source address increment/decrement (said) and, bit 4 ? source address increment/decrement enable (saide): these bits select whether the source address register (mara) is incremented, decremented, or held fixed during the data transfer. bit 5 said bit 4 saide description 0 0 mara is held fixed (initial value) 1 mara is incremented after each data transfer ? if dtsz = 0, mara is incremented by 1 after each transfer ? if dtsz = 1, mara is incremented by 2 after each transfer 1 0 mara is held fixed 1 mara is decremented after each data transfer ? if dtsz = 0, mara is decremented by 1 after each transfer ? if dtsz = 1, mara is decremented by 2 after each transfer 7. dma controller rev.5.00 sep. 12, 2007 page 203 of 764 rej09b0396-0500 bit 3 ? data transfer interrupt enable (dtie): enables or disables the cpu interrupt (dend) requested when the dte bit is cleared to 0. bit 3 dtie description 0 the dend interrupt requested by dte is disabled (initial value) 1 the dend interrupt requested by dte is enabled bits 2 and 1 ? data transfer select 2a and 1a (dts2a, dts1a): a channel operates in full address mode when dts2a and dts1a are both set to 1. bit 0 ? data transfer select 0a (dts0a): selects normal mode or block transfer mode. bit 0 dts0a description 0 normal mode (initial value) 1 block transfer mode operations in these modes are described in s ections 7.4.5, normal mode, and 7.4.6, block transfer mode. 7. dma controller rev.5.00 sep. 12, 2007 page 204 of 764 rej09b0396-0500 dtcrb bit initial value read/write 7 dtme 0 r/w 6 ? 0 r/w 5 daid 0 r/w 4 daide 0 r/w 3 tms 0 r/w 0 dts0b 0 r/w 2 dts2b 0 r/w 1 dts1b 0 r/w data transfer master enable enables or disables data transfer, to g ether with the dte bit, and is cleared to 0 by an interrupt reserved bit destination address in c rement/de c rement data transfer sele c t 2b to 0b these bits select the data transfer activation source transfer mode sele c t destination address in c rement/de c rement enable these bits select whether the destination address re g ister (marb) is incremented, decremented, or held fixed durin g the data transfer selects whether the block area is the source or destination in block transfer mode dtcrb is initialized to h'00 by a reset and in standby mode. bit 7 ? data transfer master enable (dtme): together with the dte bit in dtcra, this bit enables or disables data transfer . when the dtme and dte bits are both set to 1, the channel is enabled. when an nmi interrupt occurs dtme is cl eared to 0, suspending th e transfer so that the cpu can use the bus. the suspended transfer resume s when dtme is set to 1 again. for further information on operation in block transfer mode, see section 7.6.6, nmi interrupts and block transfer mode. dtme is set to 1 by reading the register while dtme = 0, then writing 1. bit 7 dtme description 0 data transfer is disabled (dtme is cleared to 0 when an nmi interrupt (initial value) occurs) 1 data transfer is enabled 7. dma controller rev.5.00 sep. 12, 2007 page 205 of 764 rej09b0396-0500 bit 6 ? reserved: although reserved, this bit can be written and read. bit 5 ? destination address incremen t/decrement (daid) and, bit 4 ? destination address incremen t/decrement enable (daide): these bits select whether the destination address register (marb) is incremented, decremented, or held fixed during the data transfer. bit 5 daid bit 4 daide description 0 0 marb is held fixed (initial value) 1 marb is incremented after each data transfer ? if dtsz = 0, marb is incremented by 1 after each data transfer ? if dtsz = 1, marb is incremented by 2 after each data transfer 1 0 marb is held fixed 1 marb is decremented after each data transfer ? if dtsz = 0, marb is decremented by 1 after each data transfer ? if dtsz = 1, marb is decremented by 2 after each data transfer bit 3 ? transfer mode select (tms): selects whether the source or destination is the block area in block transfer mode. bit 3 tms description 0 destination is the block area in block transfer mode (initial value) 1 source is the block area in block transfer mode 7. dma controller rev.5.00 sep. 12, 2007 page 206 of 764 rej09b0396-0500 bits 2 to 0 ? data transfer select 2b to 0b (dts2b, dts1b, dts0b): these bits select the data transfer activation source. the selectable activation sources differ between normal mode and block transfer mode. normal mode bit 2 dts2b bit 1 dts1b bit 0 dts0b description 0 0 0 auto-request (burst mode) (initial value) 1 cannot be used 1 0 auto-request (cycle-steal mode) 1 cannot be used 1 0 0 cannot be used 1 cannot be used 1 0 falling edge of dreq 1 low level input at dreq block transfer mode bit 2 dts2b bit 1 dts1b bit 0 dts0b description 0 0 0 compare match/input capture a interrupt from 16-bit timer channel 0 (initial value) 1 compare match/input capture a interrupt from 16-bit timer channel 1 1 0 compare match/input capture a interrupt from 16-bit timer channel 2 1 conversion-end interrupt from a/d converter 1 0 0 cannot be used 1 cannot be used 1 0 falling edge of dreq 1 cannot be used the same internal interrupt can be selected to activate two or more channels. the channels are activated in a priority order, highest priority first. for the priority order, see section 7.4.9, multiple-channel operation. 7. dma controller rev.5.00 sep. 12, 2007 page 207 of 764 rej09b0396-0500 7.4 operation 7.4.1 overview table 7.5 summarizes the dmac modes. table 7.5 dmac modes transfer mode activation notes short address mode compare match/input capture a interrupt from 16-bit timer channels 0 to 2 i/o mode idle mode repeat mode transmit-data-empty and receive-data-full interrupts from sci channel 0 ? up to four channels can operate independently ? only the b channels support external requests conversion-end interrupt from a/d converter external request normal mode auto-request full address mode external request block transfer mode compare match/input capture a interrupt from itu channels 0 to 2 conversion-end interrupt from a/d converter external request ? a and b channels are paired; up to two channels are available ? burst mode transfer or cycle-steal mode transfer can be selected for autorequests. a summary of operations in these modes follows. i/o mode: one byte or word is transferred per request. a designated number of these transfers are executed. a cpu interrupt can be requested at completion of the designated number of transfers. one 24-bit address and one 8-bit address are speci fied. the transfer direction is determined automatically from the activation source. idle mode: one byte or word is transferred per request. a designated number of these transfers are executed. a cpu interrupt can be requested at completion of the designated number of transfers. one 24-bit address and one 8-bit address are specified. the addresses are held fixed. the transfer direction is determined automatically from the activation source. 7. dma controller rev.5.00 sep. 12, 2007 page 208 of 764 rej09b0396-0500 repeat mode: one byte or word is transferred per reques t. a designated number of these transfers are executed. when the designated number of transfers are completed, the initial address and counter value are restored and operation continues. no cpu interrupt is requested. one 24-bit address and one 8-bit address are specified. the tr ansfer direction is determined automatically from the activation source. normal mode ? auto-request the dmac is activated by register setup alone, and continues executing transfers until the designated number of transfers have been completed. a cpu interrupt can be requested at completion of the transfers. both addresses are 24-bit addresses. ? cycle-steal mode the bus is released to another bus master after each byte or word is transferred. ? burst mode unless requested by a higher-priority bus master, the bus is not released until the designated number of transfers have been completed. ? external request one byte or word is transferred per request. a designated number of these transfers are executed. a cpu interrupt can be requested at completion of the designated number of transfers. both addresses are 24-bit addresses. block transfer mode: one block of a specified size is transferred per request. a designated number of block transfers are executed. at the end of each block transfer, one address is restored to its initial value. when the designated number of blocks have been transferred, a cpu interrupt can be requested. both addresses are 24-bit addresses. 7. dma controller rev.5.00 sep. 12, 2007 page 209 of 764 rej09b0396-0500 7.4.2 i/o mode i/o mode can be selected independently for each channel. one byte or word is transferred at each transfer re quest in i/o mode. a designated number of these transfers are executed. one addre ss is specified in the memory ad dress register (mar), the other in the i/o address register (ioar). the direction of transfer is determined automatically from the activation source. the transfer is from the address specified in ioar to th e address specified in mar if activated by an sci channel 0 receive-dat a-full interrupt or an a/d converter conversion end interrupt, and from the address specified in ma r to the address specified in ioar otherwise. table 7.6 indicates the register functions in i/o mode. table 7.6 register functions in i/o mode function register activated by sci0 receive- data-full interrupt or a/d converter conversion end interrupt other activation initial setting operation 23 0 mar destination address register source address register destination or source address incremented or decremented once per transfer all 1s ioar 23 0 7 source address register destination address register source or destination address held fixed 15 0 etcr transfer counter number of transfers decremented once per transfer until h'0000 is reached and transfer ends legend: mar: memory address register ioar: i/o address register etcr: execute transfer count register mar and ioar specify the source and destination addresses. mar specifies a 24-bit source or destination address, which is incremented or de cremented as each byte or word is transferred. 7. dma controller rev.5.00 sep. 12, 2007 page 210 of 764 rej09b0396-0500 ioar specifies the lower 8 bits of a fixed address. the upper 16 bits are all 1s. ioar is not incremented or decremented. figure 7.2 illustrates how i/o mode operates. address t address b transfer le g end: l = initial settin g of mar n = initial settin g of etcr address t = l address b = l + ( ? 1) ? (2 ? n ? 1) dtid ioar 1 byte or word is transferred per request dtsz figure 7.2 operation in i/o mode the transfer count is specified as a 16-bit value in etcr. the etcr value is decremented by 1 at each transfer. when the etcr value reaches h'0000, the dte bit is cleared and the transfer ends. if the dtie bit is set to 1, a cpu interrupt is requested at this time. the maximum transfer count is 65,536, obtained by setting etcr to h'0000. 7. dma controller rev.5.00 sep. 12, 2007 page 211 of 764 rej09b0396-0500 transfers can be requested (activated) by compare match/input capture a interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupt s from sci channel 0, conversion-end interrupts from the a/d converter, and external request signals. for the detailed settings see section 7.2.4, data transfer control registers (dtcr). figure 7.3 shows a sample setup procedure for i/o mode. set source and destination addresses set transfer count read dtcr set dtcr i/o mode i/o mode setup 1 2 3 4 1. 2. 3. 4. set the source and destination addresses in mar and ioar. the transfer direction is determined automatically from the activation source. set the transfer count in etcr. read dtcr while the dte bit is cleared to 0. set the dtcr bits as follows. select the dmac activation source with bits dts2 to dts0. set or clear the dtie bit to enable or disable the cpu interrupt at the end of the transfer. clear the rpe bit to 0 to select i/o mode. select mar increment or decrement with the dtid bit. select byte size or word size with the dtsz bit. set the dte bit to 1 to enable the transfer. ? ? ? ? ? ? figure 7.3 i/o mode setup procedure (example) 7.4.3 idle mode idle mode can be selected independently for each channel. one byte or word is transferred at each transfer request in idle mode. a designated number of these transfers are executed. one address is specified in the memo ry address register (mar), the other in the i/o address register (ioar). the direction of transfer is determined automatically from the activation source. the transfer is from the address specified in ioar to the address specified in mar if activated by an sci channel 0 receive-data-full interrupt or an a/d converter conversion end interrupt, and from the address specified in mar to the address specified in ioar otherwise. 7. dma controller rev.5.00 sep. 12, 2007 page 212 of 764 rej09b0396-0500 table 7.7 indicates the register functions in idle mode. table 7.7 register functions in idle mode function register activated by sci0 receive- data-full interrupt or a/d converter conversion end interrupt other activation initial setting operation 23 0 mar destination address register source address register destination or source address held fixed all 1s ioar 23 0 7 source address register destination address register source or destination address held fixed 15 0 etcr transfer counter number of transfers decremented once per transfer until h'0000 is reached and transfer ends legend: mar: memory address register ioar: i/o address register etcr: execute transfer count register mar and ioar specify the source and destination addresses. mar specifies a 24-bit source or destination address. ioar specifies the lower 8 bits of a fixed address. the upper 16 bits are all 1s. mar and ioar are not incremented or decremented. figure 7.4 illustrates how idle mode operates. 7. dma controller rev.5.00 sep. 12, 2007 page 213 of 764 rej09b0396-0500 transfer 1 byte or word is transferred per request ioar mar figure 7.4 operation in idle mode the transfer count is specified as a 16-bit value in etcr. the etcr value is decremented by 1 at each transfer. when the etcr value reaches h'0000, the dte bit is cleared, the transfer ends, and a cpu interrupt is requested. the maximum transfer count is 65,536, obtained by setting etcr to h'0000. transfers can be requested (activated) by compare match/input capture a interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupt s from sci channel 0, conversion-end interrupts from the a/d converter, and external request signals. for the detailed settings see section 7.3.4, data transfer control registers (dtcr). figure 7.5 shows a sample setup procedure for idle mode. 7. dma controller rev.5.00 sep. 12, 2007 page 214 of 764 rej09b0396-0500 set source and destination addresses set transfer count read dtcr set dtcr idle mode idle mode setup 1 2 3 4 1. 2. 3. 4. set the source and destination addresses in mar and ioar. the transfer direction is deter- mined automatically from the activation source. set the transfer count in etcr. read dtcr while the dte bit is cleared to 0. set the dtcr bits as follows. select the dmac activation source with bits dts2 to dts0. set the dtie and rpe bits to 1 to select idle mode. select byte size or word size with the dtsz bit. set the dte bit to 1 to enable the transfer. ? ? ? ? figure 7.5 idle mode setup procedure (example) 7.4.4 repeat mode repeat mode is useful for cyclically transferri ng a bit pattern from a table to the programmable timing pattern controller (tpc) in synchronization, for example, with 16-bit timer compare match. repeat mode can be selected for each channel independently. one byte or word is transferred per request in repeat mode, as in i/o mode. a designated number of these transfers are executed. one address is specified in the memory address register (mar), the other in the i/o address register (ioar). at the end of the designated number of transfers, mar and etcrh are restored to their original values and operation continues. the direction of transfer is determined automatically from the activation source. the transfer is from the address specified in ioar to the addre ss specified in mar if activated by an sci channel 0 receive-data- full interrupt or an a/d converter conversion end interrupt, and from the address specified in mar to the address specified in ioar otherwise. table 7.8 indicates the register functions in repeat mode. 7. dma controller rev.5.00 sep. 12, 2007 page 215 of 764 rej09b0396-0500 table 7.8 register functions in repeat mode function register activated by sci0 receive- data-full interrupt or a/d converter conversion end interrupt other activation initial setting operation 23 0 mar destination address register source address register transfer destination or transfer source start address incremented or decremented at each transfer until etcrh reaches h'0000, then restored to initial value all 1s ioar 23 0 7 source address register destination address register source or destination address held fixed transfer counter number of transfers decremented once per transfer until h'0000 is reached, then reloaded from etcrl 70 etcrh 70 etcrl initial transfer count number of transfers held fixed legend: mar: memory address register ioar: i/o address register etcr: execute transfer count register in repeat mode etcrh is used as the transfer counter while etcrl holds the initial transfer count. etcrh is decremented by 1 at each transfer until it reaches h'00, th en is reloaded from etcrl. mar is also restored to its initial value, which is calculated from the dtsz and dtid bits in dtcr. specifically, mar is restored as follows: mar mar ? ( ? 1) dtid ? 2 dtsz ? etcrl etcrh and etcrl should be initially set to the same value. 7. dma controller rev.5.00 sep. 12, 2007 page 216 of 764 rej09b0396-0500 in repeat mode transfers continue until the cpu clears the dte bit to 0. after dte is cleared to 0, if the cpu sets dte to 1 again, transfers resu me from the state at which dte was cleared. no cpu interrupt is requested. as in i/o mode, mar and ioar specify the sour ce and destination addresses. mar specifies a 24-bit source or destination address. ioar specifies the lower 8 bits of a fixed address. the upper 16 bits are all 1s. ioar is not incremented or decremented. figure 7.6 illustrates how repeat mode operates. address t address b transfer 1 byte or word is transferred per request le g end: l = initial settin g of mar n = initial settin g of etcrh and etcrl address t = l address b = l + ( ? 1) ? (2 ? n ? 1) dtid dtsz ioar figure 7.6 operation in repeat mode the transfer count is specified as an 8-bit value in etcrh and etcrl. the maximum transfer count is 255, obtained by setting both etcrh and etcrl to h'ff. transfers can be requested (activated) by compare match/input capture a interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrup ts from sci channel 0, conversion-end interrupts from the a/d converter, and external request signals. 7. dma controller rev.5.00 sep. 12, 2007 page 217 of 764 rej09b0396-0500 for the detailed settings see section 7.2.4, data transfer control registers (dtcr). figure 7.7 shows a sample setup procedure for repeat mode. set source and destination addresses set transfer count read dtcr set dtcr repeat mode repeat mode 1 2 3 4 1. 2. 3. 4. set the source and destination addresses in mar and ioar. the transfer direction is determined automatically from the activation source. set the transfer count in both etcrh and etcrl. read dtcr while the dte bit is cleared to 0. select byte size or word size with the dtsz bit. set the dte bit to 1 to enable the transfer. ? ? ? ? ? select the dmac activation source with bits dts2 to dts0. clear the dtie bit to 0 and set the rpe bit to 1 to select repeat mode. select mar increment or decrement with the dtid bit. set the dtcr bits as follows. figure 7.7 repeat mode setup procedure (example) 7. dma controller rev.5.00 sep. 12, 2007 page 218 of 764 rej09b0396-0500 7.4.5 normal mode in normal mode, the a and b channels are combined . one byte or word is transferred per request. a designated number of these transfers are ex ecuted. addresses are specified in mara and marb. table 7.9 indicates the register functions in i/o mode. table 7.9 register functions in normal mode register function initial setting operation 23 0 mara source address register transfer source start address incremented or decremented once per transfer, or held fixed 23 0 marb destination address register transfer destination start address incremented or decremented once per transfer, or held fixed 15 0 etcra transfer counter number of transfers decremented once per transfer legend: mara: memory address register a marb: memory address register b etcra: execute transfer count register a the source and destination addresses are both 24-bit addresses. mara specifies the source address. marb specifies the destination address. mara and marb can be independently incremented, decr emented, or held fixed as data is transferred. the transfer count is specified as a 16-bit value in etcra. the etcra value is decremented by 1 at each transfer. when the etcra value reaches h'0000, the dte b it is cleared and the transfer ends. if the dtie bit is set to 1, a cpu interrupt is requested at this time. the maximum transfer count is 65,536, obtained by setting etcra to h'0000. 7. dma controller rev.5.00 sep. 12, 2007 page 219 of 764 rej09b0396-0500 figure 7.8 illustrates how normal mode operates. address t address b transfer le g end: l l n t b t b said daid address t address b a b a a b b = initial settin g of mara = initial settin g of marb = initial settin g of etcra = l = l + saide ? ( ? 1) ? (2 ? n ? 1) = l = l + daide ? ( ? 1) ? (2 ? n ? 1) a a b b dtsz dtsz a a b b figure 7.8 operation in normal mode transfers can be requested (activated) by an extern al request or auto-reque st. an auto-requested transfer is activated by the register settings alone . the designated number of transfers are executed automatically. either cycl e-steal or burst mode can be select ed. in cycle-steal mode, the dmac releases the bus temporarily after each transfer. in burst mode, the dmac keeps the bus until the transfers are completed, unless there is a bus request from a higher-priority bus master. for the detailed settings see section 7.3.4, data transfer control registers (dtcr). 7. dma controller rev.5.00 sep. 12, 2007 page 220 of 764 rej09b0396-0500 figure 7.9 shows a sample setup procedure for normal mode. 1. 2. 3. 4. 5. 6. 7. 8. 9. set the initial source address in mara. set the initial destination address in marb. set the transfer count in etcra. set the dtcrb bits as follows. set the dtcra bits as follows. read dtcrb with dtme cleared to 0. normal mode normal mode set initial source address set initial destination address set transfer count set dtcrb (1) set dtcra (1) read dtcrb set dtcrb (2) read dtcra set dtcra (2) 1 2 3 4 5 6 7 8 9 ? ? ? ? ? ? ? ? clear the dtme bit to 0. set the daid and daide bits to select whether marb is incremented, decremented, or held fixed. select the dmac activation source with bits dts2b to dts0b. clear the dte bit to 0. select byte or word size with the dtsz bit. set the said and saide bits to select whether mara is incremented, decremented, or held fixed. set or clear the dtie bit to enable or disable the cpu interrupt at the end of the transfer. clear the dts0a bit to 0 and set the dts2a and dts1a bits to 1 to select normal mode. set the dtme bit to 1 in dtcrb. read dtcra with dte cleared to 0. set the dte bit to 1 in dtcra to enable the transfer. note: carry out settin g s 1 to 9 with the dend interrupt masked in the cpu. if an nmi interrupt occurs durin g the setup procedure, it may clear the dtme bit to 0, in which case the transfer will not start. figure 7.9 normal mode setup procedure (example) 7. dma controller rev.5.00 sep. 12, 2007 page 221 of 764 rej09b0396-0500 7.4.6 block transfer mode in block transfer mode, the a and b channels are combined. one block of a specified size is transferred per request. a designated number of block transfers are executed. addresses are specified in mara and marb. the block area ad dress can be either held fixed or cycled. table 7.10 indicates the register functions in block transfer mode. table 7.10 register functions in block transfer mode register function initial setting operation source address register transfer source start address incremented or decremented once per transfer, or held fixed destination address register transfer destination start address incremented or decremented once per transfer, or held fixed block size counter block size decremented once per transfer until h'00 is reached, then reloaded from etcrl initial block size block size held fixed block transfer counter number of block transfers decremented once per block transfer until h'0000 is reached and the transfer ends legend: mara: memory address register a marb: memory address register b etcra: execute transfer count register a etcrb: execute transfer count register b 23 0 mara 70 etcrah 70 etcral 23 0 marb 15 0 etcrb the source and destination addresses are both 24-bit addresses. mara specifies the source address. marb specifies the destination address. mara and marb can be independently incremented, decremented, or held fixed as data is transferred. one of these registers operates as a block area register: even if it is incremented or decremented, it is restored to its initial value at the end of each block transfer. the tms bit in dtcrb selects whether the block area is the source or destination. 7. dma controller rev.5.00 sep. 12, 2007 page 222 of 764 rej09b0396-0500 if m (1 to 255) is the size of the block transferred at each request and n (1 to 65,536) is the number of blocks to be transferred, then et crah and etcral should initially be set to m and etcrb should initially be set to n. figure 7.10 illustrates how block transfer mode operates. in this figure, bit tms is cleared to 0, meaning the block area is the destination. t b transfer le g end: l l m n t b t b address t m bytes or words are transferred per request address b a a block 1 block n b b block area block 2 = initial settin g of mara = initial settin g of marb = initial settin g of etcrah and etcral = initial settin g of etcrb = l = l + saide ? ( ? 1) ? (2 ? m ? 1) = l = l + daide ? ( ? 1) ? (2 ? m ? 1) a a b b a b a a b b said daid dtsz dtsz figure 7.10 operation in block transfer mode 7. dma controller rev.5.00 sep. 12, 2007 page 223 of 764 rej09b0396-0500 when activated by a transfer request, the dmac executes a burst transfer. during the transfer mara and marb are updated according to the dtcr settings, and etcrah is decremented. when etcrah reaches h'00, it is reloaded fr om etcral to restore the initial value. the memory address register of the block area is also restored to its initial value, and etcrb is decremented. if etcrb is not h'0000, the dmac then waits for the next transfer request. etcrah and etcral should be initially set to the same value. the above operation is repeated until etcrb reach es h'0000, at which point the dte bit is cleared to 0 and the transfer ends. if the dtie bit is set to 1, a cpu interrupt is requested at this time. figure 7.11 shows examples of a block transfer with byte data size when the block area is the destination. in (a), the block area address is cycled . in (b), the block area address is held fixed. transfers can be requested (activated) by compare match/input capture a interrupts from 16-bit timer channels 0 to 2, by a conversion-end interrupt from the a/d converter, and by external request signals. for the detailed settings see section 7.3.4, data transfer control registers (dtcr). 7. dma controller rev.5.00 sep. 12, 2007 page 224 of 764 rej09b0396-0500 start (dte = dtme = 1) transfer requested? get bus mara = mara + 1 read from mara address write to marb address marb = marb + 1 etcrah = etcrah ? 1 etcrah = h'00 release bus clear dte to 0 and end transfer etcrah = etcral marb = marb eetcral etcrb = etcrb ? 1 etcrb = h'0000 start (dte = dtme = 1) transfer requested? get bus mara = mara + 1 read from mara address write to marb address etcrah = etcrah ? 1 etcrah = h'00 release bus clear dte to 0 and end transfer etcrb = etcrb ? 1 etcrb = h'0000 etcrah = etcral no no no ye s ye s ye s no no no ye s ye s ye s a. dtsz = tms = 0 said = daid = 0 saide = daide = 1 b. dtsz = tms = 0 said = 0 saide = 1 daide = 0 figure 7.11 block transfer mode flowcharts 7. dma controller rev.5.00 sep. 12, 2007 page 225 of 764 rej09b0396-0500 figure 7.12 shows a sample setup procedure for block transfer mode. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. block transfer mode 1 2 3 4 5 6 7 8 9 10 set source address set destination address set block transfer count set block size set dtcrb (1) set dtcra (1) read dtcrb set dtcrb (2) read dtcra set dtcra (2) block transfer mode set the source address in mara. set the destination address in marb. set the block transfer count in etcrb. set the block size (number of bytes or words) in both etcrah and etcral. set the dtcrb bits as follows. set the dtcra bits as follows. ? ? ? ? ? ? ? ? ? clear the dtme bit to 0. set the daid and daide bits to select whether marb is incremented, decremented, or held fixed. set or clear the tms bit to make the block area the source or destination. select the dmac activation source with bits dts2b to dts0b. clear the dte to 0. select byte size or word size with the dtsz bit. set the said and saide bits to select whether mara is incremented, decremented, or held fixed. set or clear the dtie bit to enable or disable the cpu interrupt at the end of the transfer. set bits dts2a to dts0a all to 1 to select block transfer mode. read dtcrb with dtme cleared to 0. set the dtme bit to 1 in dtcrb. read dtcra with dte cleared to 0. set the dte bit to 1 in dtcra to enable the transfer. note: carry out settin g s 1 to 10 with the dend interrupt masked in the cpu. if an nmi interrupt occurs durin g the setup procedure, it may clear the dtme bit to 0, in which case the transfer will not start. figure 7.12 block transfer mode setup procedure (example) 7. dma controller rev.5.00 sep. 12, 2007 page 226 of 764 rej09b0396-0500 7.4.7 dmac activation the dmac can be activated by an internal interrupt, external request, or auto-request. the available activation sources differ depending on the transfer mode and channel as indicated in table 7.11. table 7.11 dmac activation sources short address mode channels channels full address mode activation source 0a and 1a 0b and 1b normal block internal imia0 yes yes no yes interrupts imia1 yes yes no yes imia2 yes yes no yes adi yes yes no yes txi0 yes yes no no rxi0 yes yes no no external requests falling edge of dreq no yes yes yes low input at dreq no yes yes no auto-request no no yes no activation by internal interrupts: when an interrupt request is selected as a dmac activation source and the dte bit is set to 1, that interrupt request is not sent to the cpu. it is not possible for an interrupt request to activate the dmac and simultaneously generate a cpu interrupt. when the dmac is activated by an interrupt request, the interrupt request flag is cleared automatically. if the same interrupt is selected to activate two or more channels, the interrupt request flag is cleared when the highest-priority channel is activated, but the transfer request is held pending on the other channels in the dmac, which are activated in their priority order. activation by external request: if an external request ( dreq pin) is selected as an activation source, the dreq pin becomes an input pin and the corresponding tend pin becomes an output pin, regardless of the port data direction register (ddr) settings. the dreq input can be level- sensitive or edge-sensitive. 7. dma controller rev.5.00 sep. 12, 2007 page 227 of 764 rej09b0396-0500 in short address mode and normal mode, an external request operates as follows. if edge sensing is selected, one byte or word is transferred each time a high-to-low transition of the dreq input is detected. if the next edge is input before the transfer is completed, the next transfer may not be executed. if level sensing is selected, the transfer continues while dreq is low, until the transfer is completed. the bus is released temporarily after each byte or word has been transferred, however. if the dreq input goes high during a transfer, the transfer is suspended after the current byte or word has been transferred. when dreq goes low, the request is held internally until one byte or word has been transferred. the tend signal goes low during the last write cycle. in block transfer mode, an external request operates as follows. only edge-sensitive transfer requests are possible in block transfer mode. each time a high-to-low transition of the dreq input is detected, a block of the specified size is transferred. the tend signal goes low during the last write cycle in each block. activation by auto-request: the transfer starts as soon as enabled by register setup, and continues until completed. cycle-steal mode or burst mode can be selected. in cycle-steal mode, the dmac releases the bus temporarily after transferring each byte or word. normally, dmac cycles a lternate with cpu cycles. in burst mode, the dmac keeps the bus until the transfer is completed, unless there is a higher- priority bus request. if there is a higher-priority bus request, the bus is released after the current byte or word has been transferred. 7.4.8 dmac bus cycle figure 7.13 shows an example of the timing of the basic dmac bus cycle. this example shows a word-size transfer from a 16-bit two-state access ar ea to an 8-bit three-st ate access area. when the dmac gets the bus from the cpu, after one dead cycle (t d ), it reads from the source address and writes to the destination address. during these read and write operations the bus is not released even if there is another bus request. dmac cycles comply with bus controller settings in the same way as cpu cycles. 7. dma controller rev.5.00 sep. 12, 2007 page 228 of 764 rej09b0396-0500 rd hwr lwr t 1 t 2 t 1 t 2 t d t 1 t 2 t 1 t 2 t 3 t 1 t 2 t 3 t 1 t 2 t 1 t 2 cpu cycle dmac cycle (1 word transfer) cpu cycle source address destination address address bus figure 7.13 dma transfer bus timing (example) figure 7.14 shows the timing when the dmac is activated by low input at a dreq pin. this example shows a word-size transfer from a 16-b it two-state access area to another 16-bit two-state access area. the dmac continue s the transfer while the dreq pin is held low. dreq rd hwr tend t 1 t 2 t 3 t d t 1 t 2 t 1 t 2 t 1 t 2 t d t 1 t 2 t 1 t 2 t 1 t 2 lwr , cpu cycle dmac cycle cpu cycle dmac cycle (last transfer cycle) cpu cycle source address destination address source address destination address address bus figure 7.14 bus timing of dma transfer requested by low dreq input 7. dma controller rev.5.00 sep. 12, 2007 page 229 of 764 rej09b0396-0500 figure 7.15 shows an auto-requested burst-mode tr ansfer. this example show s a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 rd , cpu cycle dmac cycle source address destination address cpu cycle t d address bus hwr lwr figure 7.15 burst dma bus timing when the dmac is activated from a dreq pin there is a minimum interval of four states from when the transfer is requested un til the dmac starts operating*. the dreq pin is not sampled during the time between the transfer request and the start of the transfer. in short address mode and normal mode, the pin is next sampled at the end of the read cycle. in block transfer mode, the pin is next sampled at the end of one block transfer. note: * the minimum response time is also four states when the dmac is activated by an internal module interrupt. 7. dma controller rev.5.00 sep. 12, 2007 page 230 of 764 rej09b0396-0500 figure 7.16 shows the timing when the dmac is activated by the falling edge of dreq in normal mode. dreq rd hwr t 2 t 1 t 2 t 1 t 2 t d t 1 t 2 t 1 t 2 t 1 t 2 t d t 1 t 2 lwr , cpu cycle dmac cycle cpu cycle dmac cycle minimum 4 states next samplin g point address bus figure 7.16 timing of dmac activation by falling edge of dreq in normal mode 7. dma controller rev.5.00 sep. 12, 2007 page 231 of 764 rej09b0396-0500 figure 7.17 shows the timing when the dmac is activated by level-sensitive low dreq input in normal mode. dreq rd hwr lwr , t 2 t 1 t 2 t 1 t 2 t d t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 cpu cycle dmac cycle cpu cycle minimum 4 states next samplin g point address bus figure 7.17 timing of dmac activation by low dreq level in normal mode 7. dma controller rev.5.00 sep. 12, 2007 page 232 of 764 rej09b0396-0500 figure 7.18 shows the timing when the dmac is activated by the falling edge of dreq in block transfer mode. dreq rd hwr tend t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t d t 1 t 2 dmac cycle dmac cycle cpu cycle next samplin g minimum 4 states end of 1 block transfer lwr , address bus figure 7.18 timing of dmac activation by falling edge of dreq in block transfer mode 7. dma controller rev.5.00 sep. 12, 2007 page 233 of 764 rej09b0396-0500 7.4.9 multiple-channel operation the dmac channel priority order is: channel 0 > channel 1 and channel a > channel b. table 7.12 shows the complete priority order. table 7.12 channel priority order short address mode full address mode priority channel 0a channel 0 high channel 0b channel 1a channel 1 channel 1b low if transfers are requested on two or more channels simultaneously, or if a transfer on one channel is requested during a transfer on another channel, the dmac operates as follows. ? when a transfer is requested, the dmac requests the bus right. when it gets the bus right, it starts a transfer on the highest-p riority channel at that time. ? once a transfer starts on one channel, requests to other channels are held pending until that channel releases the bus. ? after each transfer in short address mode, and each externally-requested or cycle-steal transfer in normal mode, the dmac releases the bus and returns to step 1. after releasing the bus, if there is a transfer request for another channel, the dmac requests the bus again. ? after completion of a burst-mode transfer, or after transfer of one block in block transfer mode, the dmac releases the bus and returns to step 1. if there is a transfer request for a higher-priority channel or a bus request from a higher-priority bus master, however, the dmac releases the bus after completing the tr ansfer of the current byte or word. after releasing the bus, if there is a transfer reques t for another channel, the dmac requests the bus again. figure 7.19 shows the timing when channel 0a is set up for i/o mode and channel 1 for burst mode, and a transfer request for channel 0a is received while channel 1 is active. 7. dma controller rev.5.00 sep. 12, 2007 page 234 of 764 rej09b0396-0500 rd t 1 t 2 t 1 t 2 t d t 1 t 2 t 1 t 2 t 1 t 2 t d t 1 t 2 t 1 t 2 , dmac cycle (channel 1) cpu cycle dmac cycle (channel 0a) cpu cycle dmac cycle (channel 1) address bus hwr lwr figure 7.19 timing of multiple-channel operations 7.4.10 external bus requests, dram interface, and dmac during a dmac transfer, if the bus right is requested by an external bus request signal ( breq ) or by the dram interface (refresh cycle), the dmac re leases the bus after completing the transfer of the current byte or word. if there is a transfer request at this point, the dmac requests the bus right again. figure 7.20 shows an example of the timing of insertion of a refresh cycle during a burst transfer on channel 0. rd hwr t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t 1 t 2 t d t 1 t 2 t 1 t 2 t 1 t 2 dmac cycle (channel 0) dmac cycle (channel 0) refresh cycle address bus figure 7.20 bus timing of dram interface and dmac 7. dma controller rev.5.00 sep. 12, 2007 page 235 of 764 rej09b0396-0500 7.4.11 nmi interrupts and dmac nmi interrupts do not affect dmac operations in short address mode. if an nmi interrupt occurs during a transfer in full address mode, the dmac suspends operations. in full address mode, a channel is enabled when its dte and dtme bits are both set to 1. nmi input clears the dtme bit to 0. after transferring the current byte or word, the dmac releases the bus to the cpu. in normal mode, the suspended transfer resumes when the cpu sets the dtme bit to 1 again. check that the dte bit is set to 1 and the dtme bit is cleared to 0 before setting the dtme bit to 1. figure 7.21 shows the procedure for resuming a dmac transfer in normal mode on channel 0 after the transfer was halted by nmi input. resumin g dmac transfer in normal mode dte = 1 dtme = 0 set dtme to 1 dma transfer continues end 1. 2. check that dte = 1 and dtme = 0. read dtcrb while dtme = 0, then write 1 in the dtme bit. 2 no ye s 1 figure 7.21 procedure for resuming a dmac transfer halted by nmi (example) for information about nmi interrupts in block transfer mode, see section 7.6.6, nmi interrupts and block transfer mode. 7. dma controller rev.5.00 sep. 12, 2007 page 236 of 764 rej09b0396-0500 7.4.12 aborting a dmac transfer when the dte bit in an active ch annel is cleared to 0, the dm ac halts after transferring the current byte or word. the dmac starts again when the dte bit is set to 1. in full address mode, the dtme bit can be used for the same purpose. figure 7.22 shows the procedure for aborting a dmac transfer by software. dmac transfer abort set dtcr dmac transfer aborted 1 1. clear the dte bit to 0 in dtcr. to a vo i d g eneratin g an interrupt when abortin g a dma transfer, clear the dtie bit to 0 simultaneously. figure 7.22 procedure for aborting a dmac transfer 7. dma controller rev.5.00 sep. 12, 2007 page 237 of 764 rej09b0396-0500 7.4.13 exiting full address mode figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels. to set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode. exitin g full address mode halt the channel initialize dtcrb initialize dtcra initialized and halted 1 2 3 1. 2. 3. clear the dte bit to 0 in dtcra, or wait for the transfer to end and the dte bit to be cleared to 0. clear all dtcrb bits to 0. clear all dtcra bits to 0. figure 7.23 procedure for exiting full address mode (example) 7. dma controller rev.5.00 sep. 12, 2007 page 238 of 764 rej09b0396-0500 7.4.14 dmac states in reset state, standby modes, and sleep mode when the chip is reset or enters hardware standby mode or software standby mode, the dmac is initialized and halts. dmac operations continue in sleep mode. figure 7.24 shows the timing of a cycle-steal transfer in sleep mode. address bus rd hwr 2 t d t t 2 1 t 2 t d t 1 t 2 t 1 t 2 t 1 t cpu cycle dmac cycle dmac cycle sleep mode d t figure 7.24 timing of cycle- steal transfer in sleep mode 7.5 interrupts the dmac generates only dma-end interrupts. table 7.13 lists the interrupts and their priority. table 7.13 dmac interrupts description interrupt short address mode full address mode interrupt priority dend0a end of transfer on channel 0a end of transfer on channel 0 high dend0b end of transfer on channel 0b ? dend1a end of transfer on channel 1a end of transfer on channel 1 dend1b end of transfer on channel 1b ? low 7. dma controller rev.5.00 sep. 12, 2007 page 239 of 764 rej09b0396-0500 each interrupt is enabled or disabled by the dtie bit in the corresponding data transfer control register (dtcr). separate interrupt signals are sent to the interrupt controller. the interrupt priority order among channels is ch annel 0 > channel 1 and channel a > channel b. figure 7.25 shows the dma-end interrupt logic. an interrupt is requested whenever dte = 0 and dtie = 1. dte dtie dma-end interrupt figure 7.25 dma-end interrupt logic the dma-end interrupt for the b channels (dendb) is unavailable in full address mode. the dtme bit does not affect interrupt operations. 7.6 usage notes 7.6.1 note on word data transfer word data cannot be accessed starting at an odd addr ess. when word-size transfer is selected, set even values in the memory and i/o address registers (mar and ioar). 7.6.2 dmac self-access the dmac itself cannot be accessed during a dmac cycle. dmac registers cannot be specified as source or destination addresses. 7. dma controller rev.5.00 sep. 12, 2007 page 240 of 764 rej09b0396-0500 7.6.3 longword access to memory address registers a memory address register can be accessed as longword data at the marr address. example mov.l #lbl, er0 mov.l er0, @marr four byte accesses are performed. note that the cpu may release the bus between the second byte (mare) and third byte (marh). memory address registers should be written and read only when the dmac is halted. 7.6.4 note on full address mode setup full address mode is controlled by two registers: dtcra and dtcrb. care must be taken to prevent the b channel from operating in short address mode during the register setup. the enable bits (dte and dtme) should not be set to 1 until the end of the setup procedure. 7. dma controller rev.5.00 sep. 12, 2007 page 241 of 764 rej09b0396-0500 7.6.5 note on activating dmac by internal interrupts when using an internal interrupt to activate the dmac, make sure that the interrupt selected as the activating source does not occur during the inte rval after it has been selected but before the dmac has been enabled. the on-chip supporting module that will generate the interrupt should not be activated until the dmac has been enabled. if the dmac must be enabled while the on- chip supporting module is active, follow the procedure in figure 7.26. enabling of dmac selected interrupt requested ? interrupt hand- ling by cpu clear selected interrupt's enable bit to 0 enable dmac set selected interrupt's enable bit to 1 1 2 3 4 1. 2. 3. 4. while the dte bit is cleared to 0, interrupt requests are sent to the cpu. clear the interrupt enable bit to 0 in the interrupt-generating on-chip supporting module. enable the dmac. enable the dmac-activating interrupt. dmac operates ye s no figure 7.26 procedure for enabling dmac while on-chip supporting module is operating (example) if the dte bit is set to 1 but the dtme bit is cl eared to 0, the dmac is halted and the selected activating source cannot generate a cpu interrupt. if the dmac is halted by an nmi interrupt, for example, the selected activating source cannot generate cpu interrupts. to terminate dmac operations in this state, clear the dte bit to 0 to allow cpu interrupts to be requested. to continue dmac operations, carry out steps 2 and 4 in figure 7.26 before and after setting the dtme bit to 1. 7. dma controller rev.5.00 sep. 12, 2007 page 242 of 764 rej09b0396-0500 when an itu interrupt activates the dmac, make sure the next interrupt does not occur before the dma transfer ends. if one 16-bit timer interrupt activates two or more channels, make sure the next interrupt does not occur before the dma transfers end on all the activated channels. if the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests. 7.6.6 nmi interrupts and block transfer mode if an nmi interrupt occurs in block transfer mode, the dmac operates as follows. ? when the nmi interrupt occurs, the dmac finish es transferring the current byte or word, then clears the dtme bit to 0 and halts. the halt may occur in the middle of a block. it is possible to find whether a transfer was halted in the middle of a block by checking the block size counter. if the block size counter doe s not have its initial va lue, the transfer was halted in the middle of a block. ? if the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. the activation request is not held pending. ? while the dte bit is set to 1 and the dtme bit is cleared to 0, the dmac is halted and does not accept activating interrupt requests. if an ac tivating interrupt occurs in this state, the dmac does not operate and does not hold the transfer request pending internally. neither is a cpu interrupt requested. for this reason, before setting the dtme bit to 1, first clear the enable bit of the activating interrupt to 0. then, after setting the dtme bit to 1, set the interrupt enable bit to 1 again. see section 7.6.5, note on activating dmac by internal interrupts. ? when the dtme bit is set to 1, the dmac waits for the next transfer request. if it was halted in the middle of a block transfer, the rest of the block is transferred when the next transfer request occurs. otherwise, the next block is transferred when the next transfer request occurs. 7.6.7 memory and i/o address register values table 7.14 indicates the address ranges that can be specified in the memory and i/o address registers (mar and ioar). table 7.14 address ranges specifiable in mar and ioar 1-mbyte mode 16-mbyte mode mar h'00000 to h'fffff (0 to 1048575) h'000000 to h'ffffff (0 to 16777215) ioar h'fff00 to h'fffff (1048320 to 1048575) h'ffff00 to h'ffffff (16776960 to 16777215) 7. dma controller rev.5.00 sep. 12, 2007 page 243 of 764 rej09b0396-0500 mar bits 23 to 20 are ignored in 1-mbyte mode. 7.6.8 bus cycle when transfer is aborted when a transfer is aborted by clearing the dte b it or suspended by an nmi that clears the dtme bit, if this halts a channel for which the dmac has a transfer request pending internally, a dead cycle may occur. this dead cycle does not update the halted channel's address register or counter value. figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on channel 0 is aborted by clearing the dte bit in channel 0. address bus rd hwr , lwr cpu cycle dmac cycle cpu cycle dmac cycle cpu cycle dte bit is cleared t 1 t 2 t d t 1 t 2 t 1 t 2 t 1 t 2 t 3 t d t d t 1 t 2 figure 7.27 bus timing at abort of dma transfer in cycle-steal mode 7.6.9 transfer requests by a/d converter when the a/d converter is set to scan mode and conversion is performed on more than one channel, the a/d converter generates a transfer request when all conversions are completed. the converted data is stored in the appropriate addr registers. block transfer mode and full address mode should therefore be used to transfer all the conversion results at one time. 7. dma controller rev.5.00 sep. 12, 2007 page 244 of 764 rej09b0396-0500 8. i/o ports rev.5.00 sep. 12, 2007 page 245 of 764 rej09b0396-0500 section 8 i/o ports 8.1 overview the h8/3006 and h8/3007 have 6 input/output ports (ports 4, 6, 8, 9, a, and b) and one input-only port (port 7). table 8.1 summarizes the port functions. the pins in each port are multiplexed as shown in table 8.1. each port has a data direction register (ddr) for selecting input or output, and a data register (dr) for storing output data. in addition to these registers, port 4 has an input pull-up mos control register (pcr) for switching input pull-up transistors on and off. ports 4, 6, and 8 can drive one ttl load and a 90- pf capacitive load . ports 9, a, and b can drive one ttl load and a 30-pf capacitive load. ports 4, 6 and 8 to b can drive a darlington transistor pair. pins p8 2 to p8 0 , pa 7 to pa 0 have schmitt-trigger input circuits. for block diagrams of the ports see appendix c, i/o port block diagrams. 8. i/o ports rev.5.00 sep. 12, 2007 page 246 of 764 rej09b0396-0500 table 8.1 port functions port description pins mode 1 mode 2 mode 3 mode 4 port 4 ? 8-bit i/o port ? built-in input pull-up transistors p4 7 to p4 0 / d 7 to d 0 data input/output (d 7 to d 0 ) and 8-bit generic input/ output 8-bit bus mode: generic input/output 16-bit bus mode: data input/output port 6 ? 4-bit i/o port p6 7 / clock output ( ) and generic input p6 2 / back p6 1 / breq p6 0 / wait bus control signal input/output ( back , breq , wait ) and 3-bit generic input/output port 7 ? 8-bit i/o port p7 7 /an 7 /da 1 p7 6 /an 6 /da 0 analog input (an 7 , an 6 ) to a/d converter, analog output (da 1 , da 0 ) from d/a converter, and generic input p7 5 to p7 0 / an 5 to an 0 analog input (an 5 to an 0 ) to a/d converter, and generic input port 8 p8 4 / cs 0 ddr = 0: generic input ddr = 1 (reset value): cs 0 output ? 5-bit i/o port ? p8 2 to p8 0 have schmitt inputs p8 3 / irq 3 / cs 1 / adtrg irq 3 input, cs 1 output, external trigger input ( adtrg ) to a/d converter, and generic input ddr = 0 (reset value): generic input ddr = 1: cs 1 output p8 2 / irq 2 / cs 2 p8 1 / irq 1 / cs 3 irq 2 and irq 1 input, cs 2 and cs 3 output, and generic input ddr = 0 (reset value): generic input ddr = 1: cs 2 and cs 3 output p8 0 / irq 0 / rfsh irq 0 input, rfsh output, and generic input/output port 9 ? 6-bit i/o port p9 5 / irq 5 /sck 1 p9 4 / irq 4 /sck 0 p9 3 /rxd 1 p9 2 /rxd 0 p9 1 /txd 1 p9 0 /txd 0 input and output (sck 1 , sck 0 , rxd 1 , rxd 0 , txd 1 , txd 0 ) for serial communication interfaces 1 and 0 (sci1/0), irq 5 and irq 4 input, and 6-bit generic input/output 8. i/o ports rev.5.00 sep. 12, 2007 page 247 of 764 rej09b0396-0500 port description pins mode 1 mode 2 mode 3 mode 4 port a ? 8-bit i/o port ? schmitt inputs pa 7 /tp 7 /tiocb 2 / a 20 output (tp 7 ) from pro- grammable timing pattern controller (tpc), input or output (tiocb 2 ) for 16-bit timer and generic input/output address output (a 20 ) pa 6 /tp 6 /tioca 2 / a 21 pa 5 /tp 5 /tiocb 1 / a 22 pa 4 /tp 4 /tioca 1 / a 23 tpc output (tp 6 to tp 4 ), 16-bit timer input and output (tioca 2 , tiocb 1 , tioca 1 ), and generic input/output tpc output (tp 6 to tp 4 ), 16-bit timer input and output (tioca 2 , tiocb 1 , tioca 1 ), address output (a 23 to a 21 ), and generic input/output pa 3 /tp 3 /tiocb 0 / tclkd pa 2 /tp 2 /tioca 0 / tclkc pa 1 /tp 1 /tclkb/ tend 1 pa 0 /tp 0 /tclka/ tend 0 tpc output (tp 3 to tp 0 ), 16-bit timer input and output (tiocb 0 , tioca 0 , tclkd, tclkc, tclkb, tclka), 8-bit timer input (tclkd, tclkc, tclkb, tclka), output ( tend 1 , tend 0 ) from dma controller (dmac), and generic input/output port b ? 8-bit i/o port pb 7 /tp 15 /rxd 2 pb 6 /tp 14 /txd 2 pb 5 /tp 13 /sck 2 / lcas pb 4 /tp 12 / ucas tpc output (tp 15 to tp 12 ), sci2 input and output (sck 2 , rxd 2 , txd 2 ), dram interface output ( lcas , ucas ), and generic input/output pb 3 /tp 11 /tmio 3 / dreq 1 / cs 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 0 /tp 8 /tmo 0 / cs 7 tpc output (tp 11 to tp 8 ), 8-bit timer input and output (tmio 3 , tmo 2 , tmio 1 , tmo 0 ), dmac input ( dreq 1 , dreq 0 ), cs 7 to cs 4 output, and generic input/output 8. i/o ports rev.5.00 sep. 12, 2007 page 248 of 764 rej09b0396-0500 8.2 port 4 8.2.1 overview port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.1. when the bus width control regist er (abwcr) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. when at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus. port 4 has software-programmable built-in pull-up transistors. pins in port 4 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. port 4 p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d p4 /d 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 p4 (input/output)/d 7 (input/output) p4 (input/output)/d 6 (input/output) p4 (input/output)/d 5 (input/output) p4 (input/output)/d 4 (input/output) p4 (input/output)/d 3 (input/output) p4 (input/output)/d 2 (input/output) p4 (input/output)/d 1 (input/output) p4 (input/output)/d 0 (input/output) 7 6 5 4 3 2 1 0 port 4 pins modes 1 to 4 figure 8.1 port 4 pin configuration 8. i/o ports rev.5.00 sep. 12, 2007 page 249 of 764 rej09b0396-0500 8.2.2 register configuration table 8.2 summarizes the registers of port 4. table 8.2 port 4 registers address * name abbreviation r/w initial value h'ee003 port 4 data direction register p4ddr w h'00 h'fffd3 port 4 data register p4dr r/w h'00 h'ee03e port 4 input pull-up mos control register p4pcr r/w h'00 note: * lower 20 bits of the address in advanced mode. port 4 data directio n register (p4ddr): p4ddr is an 8-bit write-onl y register that can select input or output for each pin in port 4. bit initial value read/write 7 p4 ddr 0 w port 4 data dire c tion 7 to 0 these bits select input or output for port 4 pins 7 6 p4 ddr 0 w 6 5 p4 ddr 0 w 5 4 p4 ddr 0 w 4 3 p4 ddr 0 w 3 2 p4 ddr 0 w 2 1 p4 ddr 0 w 1 0 p4 ddr 0 w 0 when all areas are designated as 8-bit-access ar eas by the bus controlle r's bus width control register (abwcr), selecting 8-bit bus mode, port 4 functions as an input/output port. in this case, a pin in port 4 becomes an output port if the corresponding p4ddr bit is set to 1, and an input port if this bit is cleared to 0. when at least one area is designated as a 16-b it-access area, selecting 16-bit bus mode, port 4 functions as part of the data bus, regardless of the p4ddr settings. p4ddr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. abwcr and p4ddr are not initialized in software standby mode. when port 4 functions as a generic input/output port, if a p4ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. 8. i/o ports rev.5.00 sep. 12, 2007 page 250 of 764 rej09b0396-0500 port 4 data register (p4dr): p4dr is an 8-bit readable/writable register that stores output data for port 4. when port 4 functions as an output port, the value of this register is output. when a bit in p4ddr is set to 1, if port 4 is read the value of the corresponding p4dr bit is returned. when a bit in p4ddr is cleared to 0, if port 4 is read the corresponding pin level is read. bit initial value read/write 7 p4 0 r/w port 4 data 7 to 0 these bits store data for port 4 pins 7 6 p4 0 r/w 6 5 p4 0 r/w 5 4 p4 0 r/w 4 3 p4 0 r/w 3 2 p4 0 r/w 2 1 p4 0 r/w 1 0 p4 0 r/w 0 p4dr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. port 4 input pull-up mos control register (p4pcr): p4pcr is an 8-bit readable/writable register that controls the mos input pull-up transistors in port 4. bit initial value read/write 7 p4 pcr 0 r/w port 4 input pull-up c ontrol 7 to 0 these bits control input pull-up transistors built into port 4 7 6 p4 pcr 0 r/w 6 5 p4 pcr 0 r/w 5 4 p4 pcr 0 r/w 4 3 p4 pcr 0 r/w 3 2 p4 pcr 0 r/w 2 1 p4 pcr 0 r/w 1 0 p4 pcr 0 r/w 0 in 8-bit bus mode when a p4ddr bit is cleared to 0 (selecting generic input), if the corresponding p4pcr bit is set to 1, the input pull-up transistor is turned on. p4pcr is initialized to h'00 by a reset and in hard ware standby mode. in software standby mode it retains its previous setting. table 8.3 summarizes the states of the input pull-ups in each operating mode. 8. i/o ports rev.5.00 sep. 12, 2007 page 251 of 764 rej09b0396-0500 table 8.3 input pull-up transistor states (port 4) mode reset hardware standby mode software standby mode other modes 8-bit bus mode off off on/off on/off 16-bit bus mode off off legend: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p4pcr = 1 and p4ddr = 0. otherwise, it is off. 8.3 port 6 8.3.1 overview port 6 is an 4-bit input/output port that is also used for input and output of bus control signals ( back , breq , wait ) and for clock ( ) output. the port 6 pin configuration is shown in figure 8.2. the pin in port 6 functions are p6 7 (generic input)/ , p6 2 / back , p6 1 / breq , and p6 0 / wait . see table 8.5 for the selection of the pin functions. see section 19, power-down state, for clock output pin. see section 6, bus controller, for bus control i/o pin ( back , breq and wait ). pins in port 6 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. 8. i/o ports rev.5.00 sep. 12, 2007 page 252 of 764 rej09b0396-0500 port 6 p6 7 / p6 2 / back p6 1 / breq p6 0 / wait port 6 pins p6 7 (input)/ (output) p6 2 (input/output)/ back (output) p6 1 (input/output)/ breq (input) p6 0 (input/output)/ wait (input) figure 8.2 port 6 pin configuration 8.3.2 register configuration table 8.4 summarizes the registers of port 6. table 8.4 port 6 registers address * name abbreviation r/w initial value h'ee005 port 6 data direction register p6ddr w h'80 h'fffd5 port 6 data register p6dr r/w h'80 note: * lower 20 bits of the address in advanced mode. port 6 data directio n register (p6ddr): p6ddr is an 8-bit write-onl y register that can select input or output for each pin in port 6. bits 7 to 3 are reserved. bit 7 is fixed at 1, and cannot be modified. bit initial value read/write 7 ? 1 ? 6 p6 6 ddr 0 w 5 p6 5 ddr 0 w 4 p6 4 ddr 0 w 3 p6 3 ddr 0 w 2 p6 2 ddr 0 w 1 p6 1 ddr 0 w 0 p6 0 ddr 0 w port 6 data direction 2 to 0 these bits select input or output for port 6 pins reserved bit 8. i/o ports rev.5.00 sep. 12, 2007 page 253 of 764 rej09b0396-0500 p6 7 functions as the clock output pin ( ) or an input port. p6 7 is the clock input pin ( ) if the pstop bit in mstcrh is cleared to 0 (initial value), and an input port if this bit is set to 1. when p6 2 to p6 0 function as input/output ports, the pin becomes an output port if the corresponding p6ddr bit is set to 1, and an input port if this bit is cleared to 0. p6ddr is a write-only register. its value cannot be read. all bits return 1 when read. p6ddr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode, it retains its previous setting. when port 6 functions as a generic input/output port, if a p6ddr bit is set to 1, the corresponding pin maintains its output state in software standby mode. port 6 data register (p6dr): p6dr is an 8-bit readable/writable register that stores output data for port 6. when port 6 functions as an output port, the value of this register is output. bit initial value read/write note: * determined by pin p6 7 . 7 p6 7 * r 6 p6 6 0 r/w 5 p6 5 0 r/w 4 p6 4 0 r/w 3 p6 3 0 r/w 2 p6 2 0 r/w 1 p6 1 0 r/w 0 p6 0 0 r/w data 7, 2 to 0 for port 6 pins bits storin g data for port 6 pins reserved bit bit 7 returns 1 if read when the pstop bit in mstcrh is 0, and returns the logic level of pin p6 7 if read when the pstop bit is 1. this bit cannot be modified. bits 6 to 3 are reserved; they can be read and written to, but cannot be used as ports. the p6dr value is returned if p6dr is read while the corresponding bit (p6 6 ddr to p6 3 ddr) in p6ddr is set to 1, and an undefined value is returned if p6dr is read while the corresponding bit is cleared to 0. for bits 2 to 0, the pin logic level is returned if the bit is read while the corresponding bit in p6ddr is cleared to 0, and the p6 dr value is returned if the bit is read while the corresponding bit in p6ddr is set to 1. p6dr is initialized to h'80 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 8. i/o ports rev.5.00 sep. 12, 2007 page 254 of 764 rej09b0396-0500 table 8.5 port 6 pin functions pin pin functions and selection method p6 7 / bit pstop in mstcrh selects the pin function as follows. pstop 0 1 pin function output p6 7 input p6 2 / back bit brle in brcr and bit p6 2 ddr select the pin function as follows. brle 0 1 p6 2 ddr 0 1 ? pin function p6 2 input p6 2 output back output p6 1 / breq bit brle in brcr and bit p6 1 ddr select the pin function as follows. brle 0 1 p6 1 ddr 0 1 ? pin function p6 1 input p6 1 output breq input p6 0 / wait bit waite in bcr and bit p6 0 ddr select the pin function as follows. waite 0 1 p6 0 ddr 0 1 0 * pin function p6 0 input p6 0 output wait input note: * do not set bit p6 0 ddr to 1. 8. i/o ports rev.5.00 sep. 12, 2007 page 255 of 764 rej09b0396-0500 8.4 port 7 8.4.1 overview port 7 is an 8-bit input-only port that is also used for analog input to the a/d converter and analog output from the d/a converter. the pin functions are the same in all operating modes. figure 8.3 shows the pin configuration of port 7. see section 15, a/d converter, for details of the a/d converter analog input pins, and section 16, d/a converter, for details of the d/a converter analog output pins. port 7 p7 (input)/an (input)/da (output) p7 (input)/an (input)/da (output) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) p7 (input)/an (input) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port 7 pins 1 0 figure 8.3 port 7 pin configuration 8.4.2 register configuration table 8.6 summarizes the port 7 register. port 7 is an input-only port, and so has no data direction register. table 8.6 port 7 data register address * name abbreviation r/w initial value h'fffd6 port 7 data register p7dr r undetermined note: * lower 20 bits of the address in advanced mode. 8. i/o ports rev.5.00 sep. 12, 2007 page 256 of 764 rej09b0396-0500 port 7 data register (p7dr) bit initial value read/write 0 p7 ? r * note: * 0 1 p7 ? r * 1 2 p7 ? r * 2 3 p7 ? r * 3 4 p7 ? r * 4 5 p7 ? r * 5 6 p7 ? r * 6 7 p7 ? r * 7 70 determined by pins p7 to p7 . when port 7 is read, the pin logic levels are always read. p7dr cannot be modified. 8.5 port 8 8.5.1 overview port 8 is a 5-bit input/output port that is also used for cs 3 to cs 0 output, rfsh output, irq 3 to irq 0 input, and a/d converter adtrg input. figure 8.4 shows the pin configuration of port 8. see table 8.8 for the selection of pin functions. see section 15, a/d converter, for a description of the a/d converter's adtrg input pin. the irq 3 to irq 0 functions are selected by ier settings, regardless of whether the pin is used for input or output. caution is therefore required. for details see section 5, interrupt controller. when dram is connected to areas 2 to 5, the cs 3 and cs 2 output pins function as ras output pins for each area. for details see section 6.5, dram interface. pins in port 8 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. pins p8 2 to p8 0 have schmitt-trigger inputs. 8. i/o ports rev.5.00 sep. 12, 2007 page 257 of 764 rej09b0396-0500 port 8 p8 / p8 / / p8 / / p8 / / p8 / / 4 3 2 1 0 0 1 2 3 port 8 pins pin fun c tions in modes 1 to 4 cs cs cs cs rfsh 3 2 1 irq / adtrg irq irq irq 0 p8 (input)/ (output) p8 (input)/ (output)/ (input) / adtrg (input) p8 (input)/ (output)/ (input) p8 (input/output)/ cs 3 (output)/ irq 1 (input) p8 (input/output)/ (output)/ (input) 4 3 2 1 0 0 1 2 cs cs cs rfsh 3 2 irq irq irq 0 figure 8.4 port 8 pin configuration 8.5.2 register configuration table 8.7 summarizes the registers of port 8. table 8.7 port 8 registers initial value address * name abbreviation r/w mode 1 to 4 h'ee007 port 8 data direction register p8ddr w h'f0 h'fffd7 port 8 data register p8dr r/w h'e0 note: * lower 20 bits of the address in advanced mode. port 8 data directio n register (p8ddr): p8ddr is an 8-bit write-onl y register that can select input or output for each pin in port 8. bits 7 to 5 are reserved. they are fixed at 1, and cannot be modified. 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 p8 4 ddr 1 w 3 p8 3 ddr 0 w 2 p8 2 ddr 0 w 1 p8 1 ddr 0 w 0 p8 0 ddr 0 w reserved bits port 8 data direction 4 to 0 these bits select input or output for port 8 pins bit initial value read/write modes 1 to 4 8. i/o ports rev.5.00 sep. 12, 2007 page 258 of 764 rej09b0396-0500 when bits in p8ddr bit are set to 1, p8 4 to p8 1 become cs 0 to cs 3 output pins. when bits in p8ddr are cleared to 0, the corresponding pins become input ports. following a reset p8 4 functions as the cs 0 output, while the other three pins are input ports. when the refresh enable bit (rfshe) in drcra is set to 1, p8 0 is used for rfsh output. when rfshe is cleared to 0, p8 0 becomes an input/output port according to the p8ddr setting. for details see table 8.8. p8ddr is a write-only register. its value cannot be read. all bits return 1 when read. p8ddr is initialized to h'f0 by a reset and in hardware standby mode. in software standby mode p8ddr retains its previous setting. therefore, when port 8 functions as an input/output port, if a transition is made to software standby mode while a p8ddr bit is set to 1, the corresponding pin maintains its output state. port 8 data register (p8dr): p8dr is an 8-bit readable/writable register that stores output data for port 8. when a bit in p8ddr is set to 1, if port 8 is read the value of the corresponding p8dr bit is returned. when a bit in p8ddr is cleared to 0, if port 8 is read the corresponding pin level is read. bits 7 to 5 are reserved. they cannot be modified and always are read as 1. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 p8 0 r/w 4 3 p8 0 r/w 3 2 p8 0 r/w 2 1 p8 0 r/w 1 0 p8 0 r/w 0 reserved bits port 8 data 4 to 0 these bits store data for port 8 pins p8dr is initialized to h'e0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 8. i/o ports rev.5.00 sep. 12, 2007 page 259 of 764 rej09b0396-0500 table 8.8 port 8 pin functions pin pin functions and selection method p8 4 / cs 0 bit p8 4 ddr selects the pin function as follows. p8 4 ddr 0 1 pin function p8 4 input cs 0 output p8 3 / cs 1 / irq 3 / adtrg bit p8 3 ddr selects the pin function as follows p8 3 ddr 0 1 pin function p8 3 input cs 1 output irq 3 input adtrg input p8 2 / cs 2 / irq 2 the dram interface settings by bits dras2 to dras0 in drcra, and bit p8 2 ddr, select the pin function as follows. dram interface settings (1) in table below (2) in table below p8 2 ddr 0 1 ? pin function p8 2 input cs 2 output cs 2 output * irq 3 input note: * cs 2 is output as ras 2 . dram interface setting (1) (2) dras2 0 1 dras1 0 1 0 1 dras0 0 1 0 1 0 1 0 1 8. i/o ports rev.5.00 sep. 12, 2007 page 260 of 764 rej09b0396-0500 pin pin functions and selection method p8 1 / cs 3 / irq 1 the dram interface settings by bits dras2 to dras0 in drcra, and bit p8 1 ddr, select the pin function as follows. dram interface settings (1) in table below (2) in table below (3) in table below p8 1 ddr 0 1 0 1 ? pin function p8 1 input cs 3 output p8 1 input p8 1 output cs 3 output * irq 1 input note: * cs 3 is output as ras 3 . dram interface setting (1) (3) (2) (3) (2) dras2 0 1 dras1 0 1 0 1 dras0 0 1 0 1 0 1 0 1 p8 0 / rfsh / irq 0 bit rfshe in drcra and bit p8 0 ddr select the pin function as follows. if areas 2 to 5 are not designated as dram space, do not set bit rfshe in drcra to 1. rfshe 0 1 p8 0 ddr 0 1 ? pin function p8 0 input p8 0 output rfsh output irq 0 input 8. i/o ports rev.5.00 sep. 12, 2007 page 261 of 764 rej09b0396-0500 8.6 port 9 8.6.1 overview port 9 is a 6-bit input/output port that is also used for input and output (txd 0 , txd 1 , rxd 0 , rxd 1 , sck 0 , sck 1 ) by serial communication in terface channels 0 and 1 (sci0 and sci1), and for irq 5 and irq 4 input. see table 8.10 for the selection of pin functions. the irq 5 and irq 4 functions are selected by ier settings, regardless of whether the pin is used for input or output. caution is therefore required. for details see section 5.3.1, external interrupts. port 9 has the same set of pin functions in all operating modes. figure 8.5 shows the pin configuration of port 9. pins in port 9 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. port 9 p9 (input/output)/sck p9 (input/output)/sck p9 (input/output)/rxd (input) p9 (input/output)/rxd (input) p9 (input/output)/txd (output) p9 (input/output)/txd (output) 5 4 3 2 1 0 port 9 pins 1 0 (input/output)/ irq (input) (input/output)/ irq (input) 5 4 1 0 1 0 figure 8.5 port 9 pin configuration 8. i/o ports rev.5.00 sep. 12, 2007 page 262 of 764 rej09b0396-0500 8.6.2 register configuration table 8.9 summarizes the registers of port 9. table 8.9 port 9 registers address * name abbreviation r/w initial value h'ee008 port 9 data direction register p9ddr w h'c0 h'fffd8 port 9 data register p9dr r/w h'c0 note: * lower 20 bits of the address in advanced mode. port 9 data directio n register (p9ddr): p9ddr is an 8-bit write-onl y register that can select input or output for each pin in port 9. bits 7 and 6 are reserved. they cannot be modified and always read as 1. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 p9 ddr 0 w 5 4 p9 ddr 0 w 4 3 p9 ddr 0 w 3 2 p9 ddr 0 w 2 1 p9 ddr 0 w 1 0 p9 ddr 0 w 0 reserved bits port 9 data dire c tion 5 to 0 these bits select input or output for port 9 pins when a pin in port 9 becomes an output port if the corresponding p9ddr bit is set to 1, and an input port if this bit is cleared to 0. p9ddr is a write-only register. its value cannot be read. all bits return 1 when read. p9ddr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. when transition is made to software standby mode while a p9ddr bit is set to 1, the corresponding pin maintains its output state. port 9 data register (p9dr): p9dr is an 8-bit readable/writable register that stores output data for port 9. when port 9 functions as an output port, the value of this register is output. when a bit in p9ddr is set to 1, if port 9 is read the value of the corresponding p9dr bit is returned. when a bit in p9ddr is cleared to 0, if port 9 is read the corresponding pin level is read. 8. i/o ports rev.5.00 sep. 12, 2007 page 263 of 764 rej09b0396-0500 bits 7 and 6 are reserved. they cannot be modified and are always read as 1. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 p9 0 r/w 4 p9 0 r/w 4 3 p9 0 r/w 3 2 p9 0 r/w 2 1 p9 0 r/w 1 0 p9 0 r/w 0 reserved bits port 9 data 5 to 0 these bits store data for port 9 pins 5 p9dr is initialized to h'c0 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. table 8.10 port 9 pin functions pin pin functions and selection method p9 5 /sck 1 / irq 5 bit c/ a in smr of sci1, bits cke0 and cke1 in scr, and bit p9 5 ddr select the pin function as follows. cke1 0 1 c/ a 0 1 ? cke0 0 1 ? ? p9 5 ddr 0 1 ? ? ? pin function p9 5 input p9 5 output sck 1 output sck 1 output sck 1 input irq 5 input p9 4 /sck 0 / irq 4 bit c/ a in smr of sci0, bits cke0 and cke1 in scr, and bit p9 4 ddr select the pin function as follows. cke1 0 1 c/ a 0 1 ? cke0 0 1 ? ? p9 4 ddr 0 1 ? ? ? pin function p9 4 input p9 4 output sck 0 output sck 0 output sck 0 input irq 4 input 8. i/o ports rev.5.00 sep. 12, 2007 page 264 of 764 rej09b0396-0500 pin pin functions and selection method p9 3 /rxd 1 bit re in scr of sci1, bit smif in scmr, and bit p9 3 ddr select the pin function as follows. smif 0 1 re 0 1 ? p9 3 ddr 0 1 ? ? pin function p9 3 input p9 3 output rxd 1 input rxd 1 input p9 2 /rxd 0 bit re in scr of sci0, bit smif in scmr, and bit p9 2 ddr select the pin function as follows. smif 0 1 re 0 1 ? p9 2 ddr 0 1 ? ? pin function p9 2 input p9 2 output rxd 0 input rxd 0 input p9 1 /txd 1 bit te in scr of sci1, bit smif in scmr, and bit p9 1 ddr select the pin function as follows. smif 0 1 te 0 1 ? p9 1 ddr 0 1 ? ? pin function p9 1 input p9 1 output txd 1 output txd 1 output * note: * functions as the txd 1 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high- impedance. p9 0 /txd 0 bit te in scr of sci0, bit smif in scmr, and bit p9 0 ddr select the pin function as follows. smif 0 1 te 0 1 ? p9 0 ddr 0 1 ? ? pin function p9 0 input p9 0 output txd 0 output txd 0 output * note: * functions as the txd 0 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high- impedance. 8. i/o ports rev.5.00 sep. 12, 2007 page 265 of 764 rej09b0396-0500 8.7 port a 8.7.1 overview port a is an 8-bit input/output port that is also used for output (tp 7 to tp 0 ) from the programmable timing pattern controller (tpc), input and output, (tiocb 2 , tioca 2 , tiocb 1 , tioca 1 , tiocb 0 , tioca 0 , tclkd, tclkc, tclkb, tclka) by the 16-bit timer, input (tclkd, tclkc, tclkb, tclka) to the 8-bit timer, output ( tend 1 , tend 0 ) from the dma controller (dmac), and address output (a 23 to a 20 ). a reset or hardware standby transition leaves port a as an input port, except that in modes 3 and 4, one pin is always used for a 20 output. see table 8.12 to 8.14 for the selection of pin functions. usage of pins for tpc, 16-bit timer, 8-bit timer, and dmac input and output is described in the sections on those modules. for output of address bits a 23 to a 21 in modes 3 and 4, see section 6.2.4, bus release control register (brcr). pins not assigned to any of these functions are available for generic input/output. figure 8.6 shows the pin configuration of port a. pins in port a can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. port a has schmitt-trigger inputs. 8. i/o ports rev.5.00 sep. 12, 2007 page 266 of 764 rej09b0396-0500 port a pa /tp /tiocb /a pa /tp /tioca /a 21 pa /tp /tiocb /a 22 pa /tp /tioca /a 23 pa /tp /tiocb /tclkd pa /tp /tioca /tclkc pa /tp / tend /tclkb pa /tp / tend /tclka 7 6 5 4 3 2 1 0 port a pins 7 6 5 4 3 2 1 0 2 2 1 1 1 0 0 0 pa (input/output)/tp (output)/tiocb (input/output) pa (input/output)/tp (output)/tioca (input/output) pa (input/output)/tp (output)/tiocb (input/output) pa (input/output)/tp (output)/tioca (input/output) 7 6 5 4 3 2 1 0 pin fun c tions in modes 1 and 2 pa (input/output)/tp (output)/tiocb (input/output)/tclkd (input) pa (input/output)/tp (output)/tioca (input/output)/tclkc (input) pa (input/output)/tp (output)/ tend (output)/tclkb (input) pa (input/output)/tp (output)/ tend (output)/tclka (input) 7 6 5 4 3 2 1 0 2 2 1 1 0 0 1 0 a (output) 20 pa (input/output)/tp (output)/tioca (input/output)/a (output) pa (input/output)/tp (output)/tiocb (input/output)/a (output) pa (input/output)/tp (output)/tioca (input/output)/a (output) 6 5 4 3 2 1 0 pin fun c tions in modes 3 and 4 6 5 4 3 2 1 0 2 1 1 0 0 pa (input/output)/tp (output)/ tend (output)/tclka (input) pa (input/output)/tp (output)/tiocb (input/output)/tclkd (input) pa (input/output)/tp (output)/tioca (input/output)/tclkc (input) pa (input/output)/tp (output)/ tend (output)/tclkb (input) 1 0 20 21 22 23 figure 8.6 port a pin configuration 8. i/o ports rev.5.00 sep. 12, 2007 page 267 of 764 rej09b0396-0500 8.7.2 register configuration table 8.11 summarizes the registers of port a. table 8.11 port a registers initial value address * name abbreviation r/w modes 1, 2 modes 3, 4 h'ee009 port a data direction register paddr w h'00 h'80 h'fffd9 port a data register padr r/w h'00 h'00 note: * lower 20 bits of the address in advanced mode. port a data direct ion register (paddr): paddr is an 8-bit write-only register that can select input or output for each pin in port a. when pins are used for tpc output, the corresponding paddr bits must also be set. 7 pa ddr 1 ? 0 w port a data direction 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 0 w 6 5 pa ddr 0 w 0 w 5 4 pa ddr 0 w 0 w 4 3 pa ddr 0 w 0 w 3 2 pa ddr 0 w 0 w 2 1 pa ddr 0 w 0 w 1 0 pa ddr 0 w 0 w 0 bit modes 3, 4, initial value read/write initial value read/write modes 1, 2 a pin in port a becomes an output port if the corresponding paddr bit is set to 1, and an input port if this bit is cleared to 0. in modes 3 and 4, pa 7 ddr is fixed at 1 and pa 7 functions as an address output pin. paddr is a write-only register. its value cannot be read. all bits return 1 when read. paddr is initialized to h'00 (modes 1 and 2) or h'80 (modes 3 and 4) by a reset and in hardware standby mode. in software standby mode it retains it previous setting. therefore, if a transition is made to software standby mode while a paddr bit is set to 1, the corresponding pin maintains its output state. 8. i/o ports rev.5.00 sep. 12, 2007 page 268 of 764 rej09b0396-0500 port a data register (padr): padr is an 8-bit readable/writa ble register that stores output data for port a. when port a functions as an output port, the value of this register is output. when a bit in paddr is set to 1, if port a is read th e value of the corresponding padr bit is returned. when a bit in paddr is cleared to 0, if port a is read the corresponding pin level is read. bit initial value read/write 0 pa 0 r/w 0 1 pa 0 r/w 1 2 pa 0 r/w 2 3 pa 0 r/w 3 4 pa 0 r/w 4 5 pa 0 r/w 5 6 pa 0 r/w 6 7 pa 0 r/w 7 port a data 7 to 0 these bits store data for port a pins padr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. table 8.12 port a pin functions (modes 1, 2) pin pin functions and selection method pa 7 /tp 7 / tiocb 2 bit pwm2 in tmdr, bits iob2 to iob0 in tior2, bit nder7 in ndera, and bit pa 7 ddr select the pin function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below pa 7 ddr ? 0 1 1 nder7 ? ? 0 1 pin function tiocb 2 output pa 7 input pa 7 output tp 7 output tiocb 2 input * note: * tiocb 2 input when iob2 = 1 and pwm2 = 0. 16-bit timer channel 2 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? 8. i/o ports rev.5.00 sep. 12, 2007 page 269 of 764 rej09b0396-0500 pin pin functions and selection method pa 6 /tp 6 / tioca 2 bit pwm2 in tmdr, bits ioa2 to ioa0 in tior2, bit nder6 in ndera, and bit pa 6 ddr select the pin function as follows. 16-bit timer channel 2 settings (1) in table below (2) in table below pa 6 ddr ? 0 1 1 nder6 ? ? 0 1 pin function tioca 2 output pa 6 input pa 6 output tp 6 output tioca 2 input * note: * tioca 2 input when ioa2 = 1. 16-bit timer channel 2 settings (2) (1) (2) (1) pwm2 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? pa 5 /tp 5 / tiocb 1 bit pwm1 in tmdr, bits iob2 to iob0 in tior1, bit nder5 in ndera, and bit pa 5 ddr select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below pa 5 ddr ? 0 1 1 nder5 ? ? 0 1 pin function tiocb 1 output pa 5 input pa 5 output tp 5 output tiocb 1 input * note: * tiocb 1 input when iob2 = 1 and pwm1 = 0. 16-bit timer channel 1 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? 8. i/o ports rev.5.00 sep. 12, 2007 page 270 of 764 rej09b0396-0500 pin pin functions and selection method pa 4 /tp 4 / tioca 1 bit pwm1 in tmdr, bits ioa2 to ioa0 in tior1, bit nder4 in ndera, and bit pa 4 ddr select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below pa 4 ddr ? 0 1 1 nder4 ? ? 0 1 pin function tioca 1 output pa 4 input pa 4 output tp 4 output tioca 1 input * note: * tioca 1 input when ioa2 = 1. 16-bit timer channel 1 settings (2) (1) (2) (1) pwm1 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 8. i/o ports rev.5.00 sep. 12, 2007 page 271 of 764 rej09b0396-0500 table 8.13 port a pin functions (modes 3, 4) pin pin functions and selection method pa 7 /tp 7 / always used as a 20 output. tiocb 2 / a 20 pin function a 20 output pa 6 /tp 6 / tioca 2 /a 21 bit pwm2 in tmdr, bits ioa2 to ioa0 in tior2, bit nder6 in ndera, bit a21e in brcr, and bit pa 6 ddr select the pin function as follows. a21e 1 0 16-bit timer channel 2 settings (1) in table below (2) in table below ? pa 6 ddr ? 0 1 1 ? nder6 ? ? 0 1 ? pin function tioca 2 output pa 6 input pa 6 output tp 6 output a 21 output tioca 2 input * note: * tioca 2 input when ioa2 = 1. 16-bit timer channel 2 settings (2) (1) (2) (1) pwm2 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 8. i/o ports rev.5.00 sep. 12, 2007 page 272 of 764 rej09b0396-0500 pin pin functions and selection method pa 5 /tp 5 / tiocb 1 /a 22 bit pwm1 in tmdr, bits iob2 to iob0 in tior1, bit nder5 in ndera, bit a22e in brcr, and bit pa 5 ddr select the pin function as follows. a22e 1 0 16-bit timer channel 1 settings (1) in table below (2) in table below ? pa 5 ddr ? 0 1 1 ? nder5 ? ? 0 1 ? pin function tiocb 1 output pa 5 input pa 5 output tp 5 output a 22 output tiocb 1 input * note: * tiocb 1 input when iob2 = 1 and pwm1 = 0. 16-bit timer channel 1 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? 8. i/o ports rev.5.00 sep. 12, 2007 page 273 of 764 rej09b0396-0500 pin pin functions and selection method pa 4 /tp 4 / tioca 1 /a 23 bit pwm1 in tmdr, bits ioa2 to ioa0 in tior1, bit nder4 in ndera, bit a23e in brcr, and bit pa 4 ddr select the pin function as follows. a23e 1 0 16-bit timer channel 1 settings (1) in table below (2) in table below ? pa 4 ddr ? 0 1 1 ? nder4 ? ? 0 1 ? pin function tioca 1 output pa 4 input pa 4 output tp 4 output a 23 output tioca 1 input * note: * tioca 1 input when ioa2 = 1. 16-bit timer channel 1 settings (2) (1) (2) (1) pwm1 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 8. i/o ports rev.5.00 sep. 12, 2007 page 274 of 764 rej09b0396-0500 table 8.14 port a pin functions (modes 1 to 4) pin pin functions and selection method pa 3 /tp 3 / tiocb 0 / tclkd bit pwm0 in tmdr, bits iob2 to iob0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr2 of the 8-bit timer, bit nder3 in ndera, and bit pa 3 ddr select the pin function as follows. 16-bit timer channel 0 settings (1) in table below (2) in table below pa 3 ddr ? 0 1 1 nder3 ? ? 0 1 pin function tiocb 0 output pa 3 input pa 3 output tp 3 output tiocb 0 input * 1 tclkd input * 2 notes: 1. tiocb0 input when iob2 = 1 and pwm0 = 0. 2. tclkd input when tpsc2 = tpsc1 = tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr2 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) (2) iob2 0 1 iob1 0 0 1 ? iob0 0 1 ? ? 8-bit timer channel 0 settings (4) (3) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? 8. i/o ports rev.5.00 sep. 12, 2007 page 275 of 764 rej09b0396-0500 pin pin functions and selection method pa 2 /tp 2 / tioca 0 / tclkc bit pwm0 in tmdr, bits ioa2 to ioa0 in tior0, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr0 of the 8-bit timer, bit nder2 in ndera, and bit pa 2 ddr select the pin function as follows. 16-bit timer channel 0 settings (1) in table below (2) in table below pa 2 ddr ? 0 1 1 nder2 ? ? 0 1 pin function tioca 0 output pa 2 input pa 2 output tp 2 output tioca 0 input * 1 tclkc input * 2 notes: 1. tioca0 input when ioa2 = 1. 2. tclkc input when tpsc2 = tpsc1 = 1 and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr0 are as shown in (3) in the table below. 16-bit timer channel 0 settings (2) (1) (2) (1) pwm0 0 1 ioa2 0 1 ? ioa1 0 0 1 ? ? ioa0 0 1 ? ? ? 8-bit timer channel 0 settings (4) (3) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? 8. i/o ports rev.5.00 sep. 12, 2007 page 276 of 764 rej09b0396-0500 pin pin functions and selection method pa 1 /tp 1 / tclkb/ tend 1 bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr3 of the 8-bit timer, bit nder1 in ndera, and bit pa 1 ddr select the pin function as follows. pa 1 ddr 0 1 1 nder1 ? 0 1 pin function pa 1 input pa 1 output tp 1 output tclkb input * 1 tend 1 output * 2 notes: 1. tclkb input when mdf = 1 in tmdr, or tpsc2 = 1, tpsc1 = 0, and tpsc0 = 1 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr3 are as shown in (1) in the table below. 2. when an external request is specified as a dmac activation source, tend 1 output regardless of bits pa 1 ddr and nder1. 8-bit timer channel 3 settings (2) (1) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? 8. i/o ports rev.5.00 sep. 12, 2007 page 277 of 764 rej09b0396-0500 pin pin functions and selection method pa 0 /tp 0 / tclka/ tend 0 bit mdf in tmdr, bits tpsc2 to tpsc0 in 16tcr2 to 16tcr0 of the 16-bit timer, bits cks2 to cks0 in 8tcr1 of the 8-bit timer, bit nder0 in ndera, and bit pa 0 ddr select the pin function as follows. pa 0 ddr 0 1 nder0 ? 0 1 pin function pa 0 input pa 0 output tp 0 output tclka input * 1 tend 0 output * 2 notes: 1. tclka input when mdf = 1 in tmdr, or tpsc2 = 1, tpsc1 = 0 and tpsc0 = 0 in any of 16tcr2 to 16tcr0, or bits cks2 to cks0 in 8tcr0 are as shown in (1) in the table below. 2. when an external request is specified as a dmac activation source, tend 0 output regardless of bits pa 0 ddr and nder0. 8-bit timer channel 1 settings (2) (1) cks2 0 1 cks1 ? 0 1 cks0 ? 0 1 ? 8.8 port b 8.8.1 overview port b is an 8-bit input/output port that is also used for output (tp 15 to tp 8 ) from the programmable timing pattern controller (tpc), input/output (tmio 3 , tmo 2 , tmio 1 , tmo 0 ) by the 8-bit timer, cs 7 to cs 4 output, input ( dreq 1 , dreq 0 ) to the dma controller (dmac), input and output (txd 2 , rxd 2 , sck 2 ) by serial communication interface channel 2 (sci2), and output ( ucas , lcas ) by the dram interface. see table 8.16 for the selection of pin functions. a reset or hardware standby transition leaves port b as an input port. for output of cs 7 to cs 4 in modes 1 to 4, see section 6.3.4, chip select signals. pins not assigned to any of these functions are available for generic input/output. when dram is connected to areas 2 to 5, the cs 4 and cs 5 output pins function as ras output pins for each area. for details see section 6.5, dram interface. figure 8.7 shows the pin configuration of port b. pins in port b can drive one ttl load and a 30-pf capacitive load. they can also drive darlington transistor pair. 8. i/o ports rev.5.00 sep. 12, 2007 page 278 of 764 rej09b0396-0500 port b pb 7 /tp /rxd 2 15 pb 6 /tp /txd 2 14 pb 5 /tp /sck 2 / lcas 13 pb 4 /tp / ucas 12 pb 3 /tp /tmio 3 / dreq 1 / cs 4 11 pb 2 /tp /tmo 2 / cs 5 10 pb 1 /tp /tmio 1 / dreq 0 / cs 6 9 pb 0 /tp /tmo 0 / cs 7 8 port b pins pb pin states in modes 1 to 4 7 (input/output)/tp 15 (output) /rxd 2 (input) pb 6 (input/output)/tp 14 (output) /txd 2 (output) pb 5 (input/output)/tp 13 (output) /sck 2 (input/output) / lcas (output) pb 4 (input/output)/tp 12 (output) / ucas (output) pb 3 (input/output)/tp 11 (output) /tmio 3 (input/output) / dreq 1 (input) cs 4 (output) pb 2 (input/output)/tp 10 (output) /tmo 2 (output) / cs 5 (output) pb 1 (input/output)/tp 9 (output) /tmio 1 (input/output) / dreq 0 (input) / cs 6 (output) pb 0 (input/output)/tp 8 (output) /tmo 0 (output) / cs 7 (output) figure 8.7 port b pin configuration 8.8.2 register configuration table 8.15 summarizes the registers of port b. table 8.15 port b registers address * name abbreviation r/w initial value h'ee00a port b data direction register pbddr w h'00 h'fffda port b data register pbdr r/w h'00 note: * lower 20 bits of the address in advanced mode. 8. i/o ports rev.5.00 sep. 12, 2007 page 279 of 764 rej09b0396-0500 port b data directio n register (pbddr): pbddr is an 8-bit write-only register that can select input or output for each pin in port b. when pins are used for tpc output, the corresponding pbddr bits must also be set. bit initial value read/write 7 pb ddr 0 w port b data dire c tion 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 when a pin in port b becomes an output port if the corresponding pbddr bit is set to 1, and an input port if this bit is cleared to 0. pbddr is a write-only register. its value cannot be read. all bits return 1 when read. pbddr is initialized to h'00 by a reset and in ha rdware standby mode. in software standby mode it retains its previous setting. when transition is made to software standby mode while a pbddr bit is set to 1, the corresponding pin maintains its output state. port b data register (pbdr): pbdr is an 8-bit readable/writable register that stores output data for pins port b. when port b functions as an output port, the value of this register is output. when a bit in pbddr is set to 1, if port b is read the value of the corresponding pbdr bit is returned. when a bit in pbddr is cleared to 0, if port b is read the corresponding pin level is read. bit initial value read/write 0 pb 0 r/w 0 1 pb 0 r/w 1 2 pb 0 r/w 2 3 pb 0 r/w 3 4 pb 0 r/w 4 5 pb 0 r/w 5 6 pb 0 r/w 6 7 pb 0 r/w 7 port b data 7 to 0 these bits store data for port b pins pbdr is initialized to h'00 by a reset and in hardware standby mode. in software standby mode it retains its previous setting. 8. i/o ports rev.5.00 sep. 12, 2007 page 280 of 764 rej09b0396-0500 table 8.16 port b pin functions pin pin functions and selection method pb 7 /tp 15 / rxd 2 bit re in scr of sci2, bit smif in scmr, bit nder15 in nderb, and bit pb 7 ddr select the pin function as follows. smif 0 1 re 0 1 ? pb 7 ddr 0 1 1 ? ? nder15 ? 0 1 ? ? pin function pb 7 input pb 7 output tp 15 output rxd 2 input rxd 2 input pb 6 /tp 14 / txd 2 bit te in scr of sci2, bit smif in scmr, bit nder14 in nderb, and bit pb 6 ddr select the pin function as follows. smif 0 1 te 0 1 ? pb 6 ddr 0 1 1 ? ? nder14 ? 0 1 ? ? pin function pb 6 input pb 6 output tp 14 output txd 2 output txd 2 output * note: * functions as the txd 2 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high-impedance. pb 5 /tp 13 / sck 2 / lcas bit c/ a in smr of sci2, bits cke0 and cke1 in scr, bit nder13 in nderb, and bit pb 5 ddr select the pin function as follows. cke1 0 1 c/ a 0 1 ? cke0 0 1 ? ? pb 5 ddr 0 1 1 ? ? ? nder13 ? 0 1 ? ? ? pin function pb 5 input pb 5 output tp 13 output sck 2 output sck 2 output sck 2 input lcas output * note: * lcas output depending on bits dras2 to dras0 in drcra and bit csel in drcrb, and regardless of bits c/ a , cke0 and cke1, nder13, and pb 5 ddr. for details, see section 6, bus controller. 8. i/o ports rev.5.00 sep. 12, 2007 page 281 of 764 rej09b0396-0500 pin pin functions and selection method bit nder12 in nderb and bit pb 4 ddr select the pin function as follows. pb 4 /tp 12 / ucas pb 4 ddr 0 1 1 nder12 ? 0 1 pin function pb 4 input pb 4 output tp 12 output ucas output * note: * ucas output depending on bits dr as2 to dras0 in drcra and bit csel in drcrb, and regardless of bits nder12 and pb 4 ddr. for details, see section 6, bus controller. pb 3 /tp 11 / tmio 3 / dreq 1 / cs 4 the dram interface settings by bits dras2 to dras0 in drcra, bits ois3/2 and os1/0 in 8tcsr3, bits cclr1 and cclr0 in 8tcr3, bit cs4e in cscr, bit nder11 in nderb, and bit pb 3 ddr select the pin function as follows. dram interface settings (1) in table below (2) in table below ois3/2 and os1/0 all 0 not all 0 ? cs4e 0 1 ? ? pb 3 ddr 0 1 1 ? ? ? nder11 ? 0 1 ? ? ? pin function pb 3 input pb 3 output tp 11 output cs 4 output tmio 3 output cs 4 output * 3 tmio 3 input * 1 dreq 1 input * 2 notes: 1. tmio3 input when cclr1 = cclr0 = 1. 2. when an external request is specified as a dmac activation source, dreq1 input regardless of bits ois3 and ois2, os1 and os0, cclr1 and cclr0, cs4e, nder11, and pb3ddr. 3. cs4 is output as ras 4 . dram interface settings (1) (2) (1) dras2 0 1 dras1 0 1 0 1 dras0 0 1 0 1 0 1 0 1 8. i/o ports rev.5.00 sep. 12, 2007 page 282 of 764 rej09b0396-0500 pin pin functions and selection method pb 2 /tp 10 / tmo 2 / cs 5 the dram interface settings by bits dras2 to dras0 in drcra, bits ois3/2 and os1/0 in 8tcsr2, bit cs5e in cscr, bit nder10 in nderb, and bit pb 2 ddr select the pin function as follows. dram interface settings (1) in table below (2) in table below ois3/2 and os1/0 all 0 not all 0 ? cs5e 0 1 ? ? pb 2 ddr 0 1 1 ? ? ? nder10 ? 0 1 ? ? ? pin function pb 2 input pb 2 output tp 10 output cs 5 output tmo 2 output cs 5 output * note: * cs 5 is output as ras 5 . dram interface settings (1) (2) (1) dras2 0 1 dras1 0 1 0 1 dras0 0 1 0 1 0 1 0 1 pb 1 /tp 9 / tmio 1 / dreq 0 / cs 6 bits ois3/2 and os1/0 in 8tcsr1, bits cclr1 and cclr0 in 8tcr0, bit cs6e in cscr, bit nder9 in nderb, and bit pb 1 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs6e 0 1 ? pb 1 ddr 0 1 1 ? ? nder9 ? 0 1 ? ? pin function pb 1 input pb 1 output tp 9 output cs 6 output tmio 1 output tmio 1 input * 1 dreq 0 input * 2 notes: 1. tmio1 input when cclr1 = cclr0 = 1. 2. dreq0 input when an external request is specified as a dmac activation source, regardless of bits ois3/2, os1/0, cclr1/0, cs6e, nder9, pb 1 ddr. 8. i/o ports rev.5.00 sep. 12, 2007 page 283 of 764 rej09b0396-0500 pin pin functions and selection method pb 0 /tp 8 / tmo 0 / cs 7 bits ois3/2 and os1/0 in 8tcsr0, bit cs7e in cscr, bit nder8 in nderb, and bit pb 0 ddr select the pin function as follows. ois3/2 and os1/0 all 0 not all 0 cs7e 0 1 ? pb 0 ddr 0 1 1 ? ? nder8 ? 0 1 ? ? pin function pb 0 input pb 0 output tp 8 output cs 7 output tmo 0 output 8. i/o ports rev.5.00 sep. 12, 2007 page 284 of 764 rej09b0396-0500 9. 16-bit timer rev.5.00 sep. 12, 2007 page 285 of 764 rej09b0396-0500 section 9 16-bit timer 9.1 overview the h8/3006 and h8/3007 have built- in 16-bit timer module with three 16-bit counter channels. 9.1.1 features 16-bit timer features are listed below. ? capability to process up to 6 pulse outputs or 6 pulse inputs ? six general registers (grs, two per channel) with independently-assignable output compare or input capture functions ? selection of eight counter clock sources for each channel: internal clocks: , /2, /4, /8 external clocks: tclka, tclkb, tclkc, tclkd ? five operating modes selectable in all channels: ? waveform output by compare match selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) ? input capture function rising edge, falling edge, or both edges (selectable) ? counter clearing function counters can be cleared by compare match or input capture ? synchronization two or more timer counters (16tcnts) can be preset simultaneously, or cleared simultaneously by compare match or input capture. counter synchronization enables synchronous register input and output. ? pwm mode pwm output can be provided with an arbitrary duty cycle. with synchronization, up to three-phase pwm output is possible ? phase counting mode selectable in channel 2 two-phase encoder output can be counted automatically. ? high-speed access via internal 16-bit bus the 16tcnts and grs can be accessed at high speed via a 16-bit bus. ? any initial timer output value can be set 9. 16-bit timer rev.5.00 sep. 12, 2007 page 286 of 764 rej09b0396-0500 ? nine interrupt sources each channel has two compare match/input capture interrupts and an overflow interrupt. all interrupts can be requested independently. ? output triggering of programmable timing pattern controller (tpc) compare match/input capture signals from channels 0 to 2 can be used as tpc output triggers. table 9.1 summarizes the 16-bit timer functions. table 9.1 16-bit timer functions item channel 0 channel 1 channel 2 clock sources internal clocks: , /2, /4, /8 external clocks: tclka, tclkb, tclkc, tclkd, selectable independently general registers (output compare/input capture registers) gra0, grb0 gra1, grb1 gra2, grb2 input/output pins tioca 0 , tiocb 0 tioca 1 , tiocb 1 tioca 2 , tiocb 2 counter clearing function gra0/grb0 compare match or input capture gra1/grb1 compare match or input capture gra2/grb2 compare match or input capture initial output value setting function available available available 0 available available available 1 available available available compare match output toggle available available not available input capture function available available available synchronization available available available pwm mode available available available phase counting mode not available not available available interrupt sources three sources ? compare match/input capture a0 ? compare match/input capture b0 ? overflow three sources ? compare match/input capture a1 ? compare match/input capture b1 ? overflow three sources ? compare match/input capture a2 ? compare match/input capture b2 ? overflow 9. 16-bit timer rev.5.00 sep. 12, 2007 page 287 of 764 rej09b0396-0500 9.1.2 block diagrams 16-bit timer block diagram (overall): figure 9.1 is a block diagram of the 16-bit timer. 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 module data bus bus interface internal data bus imia0 to imia2 imib0 to imib2 ovi0 to ovi2 tclka to tclkd , /2, /4, /8 clock selector control lo g ic tioca 0 to tioca 2 tiocb 0 to tiocb 2 tstr tsnc tmdr tolr tisra tisrb tisrc tstr: timer start re g ister (8 bits) tsnc: timer synchro re g ister (8 bits) tmdr: timer mode re g ister (8 bits) tolr: timer output level settin g re g ister (8 bits) tisra: timer interrupt status re g ister a (8 bits) tisrb: timer interrupt status re g ister b (8 bits) tisrc: timer interrupt status re g ister c (8 bits) le g end: figure 9.1 16-bit timer block diagram (overall) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 288 of 764 rej09b0396-0500 block diagram of channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. both have the structure shown in figure 9.2. clock selector comparator control lo g ic tclka to tclkd , /2, /4, /8 tioca 0 tiocb 0 imia0 imib0 ovi0 16tcnt gra grb 16tcr tior module data bus le g end: 16tcnt: gra, grb: 16tcr: tior: timer counter (16 bits) general re g isters a and b (input capture/output compare re g isters) (16 bits 2) timer control re g ister (8 bits) timer i/o control re g ister (8 bits) figure 9.2 block diagram of channels 0 and 1 9. 16-bit timer rev.5.00 sep. 12, 2007 page 289 of 764 rej09b0396-0500 block diagram of channel 2: figure 9.3 is a block diagram of channel 2 clock selector comparator control lo g ic tclka to tclkd , /2, /4, /8 tioca 2 tiocb 2 imia2 imib2 ovi2 16tcnt2 gra2 grb2 16tcr2 tior2 module data bus le g end: 16tcnt2: gra2, grb2: 16tcr2: tior2: timer counter 2 (16 bits) general re g isters a2 and b2 (input capture/output compare re g isters) (16 bits 2) timer control re g ister 2 (8 bits) timer i/o control re g ister 2 (8 bits) figure 9.3 block diagram of channel 2 9. 16-bit timer rev.5.00 sep. 12, 2007 page 290 of 764 rej09b0396-0500 9.1.3 pin configuration table 9.2 summarizes the 16-bit timer pins. table 9.2 16-bit timer pins channel name abbre- viation input/ output function common clock input a tclka input external clock a input pin (phase-a input pin in phase counting mode) clock input b tclkb input external clock b input pin (phase-b input pin in phase counting mode) clock input c tclkc input external clock c input pin clock input d tclkd input external clock d input pin 0 input capture/output compare a0 tioca 0 input/ output gra0 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b0 tiocb 0 input/ output grb0 output compare or input capture pin 1 input capture/output compare a1 tioca 1 input/ output gra1 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b1 tiocb 1 input/ output grb1 output compare or input capture pin 2 input capture/output compare a2 tioca 2 input/ output gra2 output compare or input capture pin pwm output pin in pwm mode input capture/output compare b2 tiocb 2 input/ output grb2 output compare or input capture pin 9. 16-bit timer rev.5.00 sep. 12, 2007 page 291 of 764 rej09b0396-0500 9.1.4 register configuration table 9.3 summarizes the 16-bit timer registers. table 9.3 16-bit timer registers channel address * 1 name abbre- viation r/w initial value common h'fff60 timer start register tstr r/w h'f8 h'fff61 timer synchro register tsnc r/w h'f8 h'fff62 timer mode register tmdr r/w h'98 h'fff63 timer output level setting register tolr w h'c0 h'fff64 timer interrupt status register a tisra r/(w) * 2 h'88 h'fff65 timer interrupt status register b tisrb r/(w) * 2 h'88 h'fff66 timer interrupt status register c tisrc r/(w) * 2 h'88 0 h'fff68 timer control register 0 16tcr0 r/w h'80 h'fff69 timer i/o control register 0 tior0 r/w h'88 h'fff6a timer counter 0h 16tcnt0h r/w h'00 h'fff6b timer counter 0l 16tcnt0l r/w h'00 h'fff6c general register a0h gra0h r/w h'ff h'fff6d general register a0l gra0l r/w h'ff h'fff6e general register b0h grb0h r/w h'ff h'fff6f general register b0l grb0l r/w h'ff 1 h'fff70 timer control register 1 16tcr1 r/w h'80 h'fff71 timer i/o control register 1 tior1 r/w h'88 h'fff72 timer counter 1h 16tcnt1h r/w h'00 h'fff73 timer counter 1l 16tcnt1l r/w h'00 h'fff74 general register a1h gra1h r/w h'ff h'fff75 general register a1l gra1l r/w h'ff h'fff76 general register b1h grb1h r/w h'ff h'fff77 general register b1l grb1l r/w h'ff 9. 16-bit timer rev.5.00 sep. 12, 2007 page 292 of 764 rej09b0396-0500 channel address * 1 name abbre- viation r/w initial value 2 h'fff78 timer control register 2 16tcr2 r/w h'80 h'fff79 timer i/o control register 2 tior2 r/w h'88 h'fff7a timer counter 2h 16tcnt2h r/w h'00 h'fff7b timer counter 2l 16tcnt2l r/w h'00 h'fff7c general register a2h gra2h r/w h'ff h'fff7d general register a2l gra2l r/w h'ff h'fff7e general register b2h grb2h r/w h'ff h'fff7f general register b2l grb2l r/w h'ff notes: 1. the lower 20 bits of the address in advanced mode are indicated. 2. only 0 can be written in bits 3 to 0, to clear the flags. 9.2 register descriptions 9.2.1 timer start register (tstr) tstr is an 8-bit readable/writabl e register that starts and stop s the timer counter (16tcnt) in channels 0 to 2. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 str2 0 r/w 1 str1 0 r/w 0 str0 0 r/w reserved bits counter start 2 to 0 these bits start and stop 16tcnt2 to 16tcnt0 tstr is initialized to h'f8 by a reset and in standby mode. bits 7 to 3 ? reserved: these bits cannot be modified and are always read as 1. bit 2 ? counter start 2 (str2): starts and stops timer counter 2 (16tcnt2). bit 2 str2 description 0 16tcnt2 is halted (initial value) 1 16tcnt2 is counting 9. 16-bit timer rev.5.00 sep. 12, 2007 page 293 of 764 rej09b0396-0500 bit 1 ? counter start 1 (str1): starts and stops timer counter 1 (16tcnt1). bit 1 str1 description 0 16tcnt1 is halted (initial value) 1 16tcnt1 is counting bit 0 ? counter start 0 (str0): starts and stops timer counter 0 (16tcnt0). bit 0 str0 description 0 16tcnt0 is halted (initial value) 1 16tcnt0 is counting 9.2.2 timer synchro register (tsnc) tsnc is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously. channels are synchronized by setting the corresponding bits to 1. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 r/w reserved bits timer sync 2 to 0 these bits synchronize channels 2 to 0 tsnc is initialized to h'f8 by a reset and in standby mode. bits 7 to 3 ? reserved: these bits cannot be modified and are always read as 1. bit 2 ? timer sync 2 (sync2): selects whether channel 2 operates independently or synchronously. bit 2 sync2 description 0 channel 2's timer counter (16tcnt2) operates independently (initial value) 16tcnt2 is preset and cleared independently of other channels 1 channel 2 operates synchronously 16tcnt2 can be synchronously preset and cleared 9. 16-bit timer rev.5.00 sep. 12, 2007 page 294 of 764 rej09b0396-0500 bit 1 ? timer sync 1 (sync1): selects whether channel 1 operates independently or synchronously. bit 1 sync1 description 0 channel 1's timer counter (16tcnt1) operates independently (initial value) 16tcnt1 is preset and cleared independently of other channels 1 channel 1 operates synchronously 16tcnt1 can be synchronously preset and cleared bit 0 ? timer sync 0 (sync0): selects whether channel 0 operates independently or synchronously. bit 0 sync0 description 0 channel 0's timer counter (16tcnt0) operates independently (initial value) 16tcnt0 is preset and cleared independently of other channels 1 channel 0 operates synchronously 16tcnt0 can be synchronously preset and cleared 9. 16-bit timer rev.5.00 sep. 12, 2007 page 295 of 764 rej09b0396-0500 9.2.3 timer mode register (tmdr) tmdr is an 8-bit readable/writable register that selects pwm mode for channels 0 to 2. it also selects phase counting mode and the overflow flag (ovf) setting conditions for channel 2. bit initial value read/write 7 ? 1 ? 6 mdf 0 r/w 5 fdir 0 r/w 4 ? 1 ? 3 ? 1 ? 0 pwm0 0 r/w 2 pwm2 0 r/w 1 pwm1 0 r/w reserved bit reserved bit pwm mode 2 to 0 these bits select pwm mode for channels 2 to 0 phase counting mode flag selects phase counting mode for channel 2 flag direction selects the setting condition for the overflow flag (ovf) in tisrc tmdr is initialized to h'98 by a reset and in standby mode. bit 7 ? reserved: this bit cannot be modified and is always read as 1. bit 6 ? phase counting mode flag (mdf): selects whether channel 2 operates normally or in phase counting mode. bit 6 mdf description 0 channel 2 operates normally (initial value) 1 channel 2 operates in phase counting mode when mdf is set to 1 to select phase counting mode, 16tcnt2 operates as an up/down-counter and pins tclka and tclkb become counter clock input pins. 16tcnt2 counts both rising and falling edges of tclka and tclkb, and counts up or down as follows. counting direction down-counting up-counting tclka pin high low low high tclkb pin low high high low 9. 16-bit timer rev.5.00 sep. 12, 2007 page 296 of 764 rej09b0396-0500 in phase counting mode channel 2 operates as above regardless of the external clock edges selected by bits ckeg1 and ckeg0 and the clock source selected by bits tpsc2 to tpsc0. phase counting mode takes precedence over these settings. the counter clearing condition selected by th e cclr1 and cclr0 bits in 16tcr2 and the compare match/input capture setti ngs and interrupt functions of tior2, tisra, tisrb, tisrc remain effective in phase counting mode. bit 5 ? flag direction (fdir): designates the setting condition for the ovf flag in tisrc. the fdir designation is valid in all modes in channel 2. bit 5 fdir description 0 ovf is set to 1 in tisrc when 16tcnt2 overflows or underflows (initial value) 1 ovf is set to 1 in tisrc when 16tcnt2 overflows bits 4 and 3 ? reserved: these bits cannot be modified and are always read as 1. bit 2 ? pwm mode 2 (pwm2): selects whether channel 2 operates normally or in pwm mode. bit 2 pwm2 description 0 channel 2 operates normally (initial value) 1 channel 2 operates in pwm mode when bit pwm2 is set to 1 to select pwm mode, pin tioca 2 becomes a pwm output pin. the output goes to 1 at compare match with gra2, and to 0 at compare match with grb2. bit 1 ? pwm mode 1 (pwm1): selects whether channel 1 operates normally or in pwm mode. bit 1 pwm1 description 0 channel 1 operates normally (initial value) 1 channel 1 operates in pwm mode when bit pwm1 is set to 1 to select pwm mode, pin tioca 1 becomes a pwm output pin. the output goes to 1 at compare match with gra1, and to 0 at compare match with grb1. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 297 of 764 rej09b0396-0500 bit 0 ? pwm mode 0 (pwm0): selects whether channel 0 operates normally or in pwm mode. bit 0 pwm0 description 0 channel 0 operates normally (initial value) 1 channel 0 operates in pwm mode when bit pwm0 is set to 1 to select pwm mode, pin tioca 0 becomes a pwm output pin. the output goes to 1 at compare match with gra0, and to 0 at compare match with grb0. 9.2.4 timer interrupt status register a (tisra) tisra is an 8-bit readable/writable register th at indicates gra compare match or input capture and enables or disables general register compare match and input capture interrupt requests. 7 ? 1 ? bit initial value read/write 6 imiea2 0 r/w 5 imiea1 0 r/w 4 imiea0 0 r/w 3 ? 1 ? 2 imfa2 0 r/(w) * 1 imfa1 0 r/(w) * 0 imfa0 0 r/(w) * reserved bit reserved bit input c apture/ c ompare mat c h interrupt enable a2 to a0 these bits enable or disable interrupts by the imfa fla g s input c apture/ c ompare mat c h flags a2 to a0 status fla g s indicatin g gra compare match or input capture note: * only 0 can be written, to clear the fla g . tisra is initialized to h'88 by a reset and in standby mode. bit 7 ? reserved: this bit cannot be modified and is always read as 1. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 298 of 764 rej09b0396-0500 bit 6 ? input capture/compare match in terrupt enable a2 (imiea2): enables or disables the interrupt requested by the imfa2 flag when imfa2 is set to 1. bit 6 imiea2 description 0 imia2 interrupt requested by imfa2 flag is disabled (initial value) 1 imia2 interrupt requested by imfa2 flag is enabled bit 5 ? input capture/compare match in terrupt enable a1 (imiea1): enables or disables the interrupt requested by the imfa1 flag when imfa1 is set to 1. bit 5 imiea1 description 0 imia1 interrupt requested by imfa1 flag is disabled (initial value) 1 imia1 interrupt requested by imfa1 flag is enabled bit 4 ? input capture/compare match in terrupt enable a0 (imiea0): enables or disables the interrupt requested by the imfa0 flag when imfa0 is set to 1. bit 4 imiea0 description 0 imia0 interrupt requested by imfa0 flag is disabled (initial value) 1 imia0 interrupt requested by imfa0 flag is enabled bit 3 ? reserved: this bit cannot be modified and is always read as 1. bit 2 ? input capture/compare match flag a2 (imfa2): this status flag indicates gra2 compare match or input capture events. bit 2 imfa2 description 0 [clearing conditions] (initial value) ? read imfa2 when imfa2 =1, then write 0 in imfa2. ? dmac activated by imia2 interrupt. 1 [setting conditions] ? 16tcnt2 = gra2 when gra2 functions as an output compare register. ? 16tcnt2 value is transferred to gra2 by an input capture signal when gra2 functions as an input capture register. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 299 of 764 rej09b0396-0500 bit 1 ? input capture/compare match flag a1 (imfa1): this status flag indicates gra1 compare match or input capture events. bit 1 imfa1 description 0 [clearing conditions] (initial value) ? read imfa1 when imfa1 =1, then write 0 in imfa1. ? dmac activated by imia1 interrupt. 1 [setting conditions] ? 16tcnt1 = gra1 when gra1 functions as an output compare register. ? 16tcnt1 value is transferred to gra1 by an input capture signal when gra1 functions as an input capture register. bit 0 ? input capture/compare match flag a0 (imfa0): this status flag indicates gra0 compare match or input capture events. bit 0 imfa0 description 0 [clearing conditions] (initial value) ? read imfa0 when imfa0 =1, then write 0 in imfa0. ? dmac activated by imia0 interrupt. 1 [setting conditions] ? 16tcnt0 = gra0 when gra0 functions as an output compare register. ? 16tcnt0 value is transferred to gra0 by an input capture signal when gra0 functions as an input capture register. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 300 of 764 rej09b0396-0500 9.2.5 timer interrupt status register b (tisrb) tisrb is an 8-bit readable/writable register that indicates grb compare match or input capture and enables or disables general register compare match and input capture interrupt requests. 7 ? 1 ? bit initial value read/write 6 imieb2 0 r/w 5 imieb1 0 r/w 4 imieb0 0 r/w 3 ? 1 ? 2 imfb2 0 r/(w) * 1 imfb1 0 r/(w) * 0 imfb0 0 r/(w) * reserved bit reserved bit input c apture/ c ompare mat c h interrupt enable b2 to b0 these bits enable or disable interrupts by the imfb fla g s input c apture/ c ompare mat c h flags b2 to b0 status fla g s indicatin g grb compare match or input capture note: * only 0 can be written, to clear the fla g . tisrb is initialized to h'88 by a reset and in standby mode. bit 7 ? reserved: this bit cannot be modified and is always read as 1. bit 6 ? input capture/compare match in terrupt enable b2 (imieb2): enables or disables the interrupt requested by the imfb2 flag when imfb2 is set to 1. bit 6 imieb2 description 0 imib2 interrupt requested by imfb2 flag is disabled (initial value) 1 imib2 interrupt requested by imfb2 flag is enabled 9. 16-bit timer rev.5.00 sep. 12, 2007 page 301 of 764 rej09b0396-0500 bit 5 ? input capture/compare match in terrupt enable b1 (imieb1): enables or disables the interrupt requested by the imfb1 flag when imfb1 is set to 1. bit 5 imieb1 description 0 imib1 interrupt requested by imfb1 flag is disabled (initial value) 1 imib1 interrupt requested by imfb1 flag is enabled bit 4 ? input capture/compare match in terrupt enable b0 (imieb0): enables or disables the interrupt requested by the imfb0 flag when imfb0 is set to 1. bit 4 imieb0 description 0 imib0 interrupt requested by imfb0 flag is disabled (initial value) 1 imib0 interrupt requested by imfb0 flag is enabled bit 3 ? reserved: this bit cannot be modified and is always read as 1. bit 2 ? input capture/compare match flag b2 (imfb2): this status flag indicates grb2 compare match or input capture events. bit 2 imfb2 description 0 [clearing condition] (initial value) read imfb2 when imfb2 =1, then write 0 in imfb2. 1 [setting conditions] ? 16tcnt2 = grb2 when grb2 functions as an output compare register. ? 16tcnt2 value is transferred to grb2 by an input capture signal when grb2 functions as an input capture register. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 302 of 764 rej09b0396-0500 bit 1 ? input capture/compare match flag b1 (imfb1): this status flag indicates grb1 compare match or input capture events. bit 1 imfb1 description 0 [clearing condition] (initial value) read imfb1 when imfb1 =1, then write 0 in imfb1. 1 [setting conditions] ? 16tcnt1 = grb1 when grb1 functions as an output compare register. ? 16tcnt1 value is transferred to grb1 by an input capture signal when grb1 functions as an input capture register. bit 0 ? input capture/compare match flag b0 (imfb0): this status flag indicates grb0 compare match or input capture events. bit 0 imfb0 description 0 [clearing condition] (initial value) read imfb0 when imfb0 =1, then write 0 in imfb0. 1 [setting conditions] ? 16tcnt0 = grb0 when grb0 functions as an output compare register. ? 16tcnt0 value is transferred to grb0 by an input capture signal when grb0 functions as an input capture register. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 303 of 764 rej09b0396-0500 9.2.6 timer interrupt status register c (tisrc) tisrc is an 8-bit readable/writable register that indicates 16tcnt overflow or underflow and enables or disables overflow interrupt requests. 7 ? 1 ? bit initial value read/write 6 ovie2 0 r/w 5 ovie1 0 r/w 4 ovie0 0 r/w 3 ? 1 ? 2 ovf2 0 r/(w) * 1 ovf1 0 r/(w) * 0 ovf0 0 r/(w) * reserved bit reserved bit overflow interrupt enable 2 to 0 these bits enable or disable interrupts by the ovf fla g s overflow flags 2 to 0 status fla g s indicatin g interrupts by ovf fla g s note: * only 0 can be written, to clear the fla g . tisrc is initialized to h'88 by a reset and in standby mode. bit 7 ? reserved: this bit cannot be modified and is always read as 1. bit 6 ? overflow interrupt enable 2 (ovie2): enables or disables the interrupt requested by the ovf2 flag when ovf2 is set to 1. bit 6 ovie2 description 0 ovi2 interrupt requested by ovf2 flag is disabled (initial value) 1 ovi2 interrupt requested by ovf2 flag is enabled bit 5 ? overflow interrupt enable 1 (ovie1): enables or disables the interrupt requested by the ovf1 flag when ovf1 is set to 1. bit 5 ovie1 description 0 ovi1 interrupt requested by ovf1 flag is disabled (initial value) 1 ovi1 interrupt requested by ovf1 flag is enabled 9. 16-bit timer rev.5.00 sep. 12, 2007 page 304 of 764 rej09b0396-0500 bit 4 ? overflow interrupt enable 0 (ovie0): enables or disables the interrupt requested by the ovf0 flag when ovf0 is set to 1. bit 4 ovie0 description 0 ovi0 interrupt requested by ovf0 flag is disabled (initial value) 1 ovi0 interrupt requested by ovf0 flag is enabled bit 3 ? reserved: this bit cannot be modified and is always read as 1. bit 2 ? overflow flag 2 (ovf2): this status flag indicates 16tcnt2 overflow. bit 2 ovf2 description 0 [clearing condition] (initial value) read ovf2 when ovf2 =1, then write 0 in ovf2. 1 [setting condition] 16tcnt2 overflowed from h'ffff to h'0000, or underflowed from h'0000 to h'ffff. note: 16tcnt underflow occurs when 16tcnt operates as an up/down-counter. underflow occurs only when channel 2 operates in phase counting mode (mdf = 1 in tmdr). bit 1 ? overflow flag 1 (ovf1): this status flag indicates 16tcnt1 overflow. bit 1 ovf1 description 0 [clearing condition] (initial value) read ovf1 when ovf1 =1, then write 0 in ovf1. 1 [setting condition] 16tcnt1 overflowed from h'ffff to h'0000. bit 0 ? overflow flag 0 (ovf0): this status flag indicates 16tcnt0 overflow. bit 0 ovf0 description 0 [clearing condition] (initial value) read ovf0 when ovf0 =1, then write 0 in ovf0. 1 [setting condition] 16tcnt0 overflowed from h'ffff to h'0000. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 305 of 764 rej09b0396-0500 9.2.7 timer counters (16tcnt) 16tcnt is a 16-bit counter. the 16-bit timer has three 16tcnts, one for each channel. channel abbreviation function 0 16tcnt0 up-counter 1 16tcnt1 2 16tcnt2 phase counting mode: up/down-counter other modes: up-counter bit initial value read/write 14 0 r/w 12 0 r/w 10 0 r/w 8 0 r/w 6 0 r/w 0 0 r/w 4 0 r/w 2 0 r/w 15 0 r/w 13 0 r/w 11 0 r/w 9 0 r/w 7 0 r/w 1 0 r/w 5 0 r/w 3 0 r/w each 16tcnt is a 16-bit readable/writable register that counts pulse inputs from a clock source. the clock source is selected by bits tpsc2 to tpsc0 in 16tcr. 16tcnt0 and 16tcnt1 are up-counters. 16tcnt2 is an up/down-counter in phase counting mode and an up-counter in other modes. 16tcnt can be cleared to h'0000 by compare match with gra or grb or by input capture to gra or grb (counter clearing function). when 16tcnt overflows (changes fr om h'ffff to h'0000), the ovf flag is set to 1 in tisrc of the corresponding channel. when 16tcnt underflows (changes from h'0000 to h'ffff), the ovf flag is set to 1 in tisrc of the corresponding channel. the 16tcnts are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. each 16tcnt is initialized to h'0000 by a reset and in standby mode. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 306 of 764 rej09b0396-0500 9.2.8 general registers (gra, grb) the general registers are 16-bit registers. the 16-bit timer has 6 general registers, two in each channel. channel abbreviation function 0 gra0, grb0 output compare/input capture register 1 gra1, grb1 2 gra2, grb2 bit initial value read/write 14 1 r/w 12 1 r/w 10 1 r/w 8 1 r/w 6 1 r/w 0 1 r/w 4 1 r/w 2 1 r/w 15 1 r/w 13 1 r/w 11 1 r/w 9 1 r/w 7 1 r/w 1 1 r/w 5 1 r/w 3 1 r/w a general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. the function is selected by settings in tior. when a general register is used as an output co mpare register, its value is constantly compared with the 16tcnt value. when the two values match (compare match), the imfa or imfb flag is set to 1 in tisra/tisrb. compare match output can be selected in tior. when a general register is used as an input captu re register an external input capture signal are detected and the current 16tcnt value is stored in the general register. the corresponding imfa or imfb flag in tisra/tisrb is set to 1 at the same time. the valid edge or edges of the input capture signal are selected in tior. tior settings are ignored in pwm mode. general registers are linked to the cpu by an internal 16-bit bus and can be written or read by either word access or byte access. general registers are initialized to the output compare function (with no output signal) by a reset and in standby mode. the initial value is h'ffff. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 307 of 764 rej09b0396-0500 9.2.9 timer control registers (16tcr) 16tcr is an 8-bit register. the 16-bit timer has three 16tcrs, one in each channel. channel abbreviation function 0 16tcr0 1 16tcr1 2 16tcr2 cr controls the timer counter. the 16tcrs in all channels are functionally identical. when phase counting mode is selected in channel 2, the settings of bits ckeg1 and ckeg0 and tpsc2 to tpsc0 in 16tcr2 are ignored. bit initial value read/write 7 ? 1 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w timer prescaler 2 to 0 these bits select the counter clock reserved bit clock edge 1/0 these bits select external clock edges counter clear 1/0 these bits select the counter clear source each 16tcr is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. 16tcr is initialized to h'80 by a reset and in standby mode. bit 7 ? reserved: this bit cannot be modified and is always read as 1. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 308 of 764 rej09b0396-0500 bits 6 and 5 ? counter clear 1 and 0 (cclr1, cclr0): these bits select how 16tcnt is cleared. bit 6 cclr1 bit 5 cclr0 description 0 0 16tcnt is not cleared (initial value) 1 16tcnt is cleared by gra compare match or input capture * 1 1 0 16tcnt is cleared by grb compare match or input capture * 1 1 synchronous clear: 16tcnt is cleared in synchronization with other synchronized timers * 2 notes: 1. 16tcnt is cleared by compare match when the general register functions as an output compare register, and by input capture when th e general register functions as an input capture register. 2. selected in tsnc. bits 4 and 3 ? clock edge 1 and 0 (ckeg1, ckeg0): these bits select external clock input edges when an external clock source is used. bit 4 ckeg1 bit 3 ckeg0 description 0 0 count rising edges (initial value) 1 count falling edges 1 ? count both edges when channel 2 is set to phase counting mode, bits ckeg1 and ckeg0 in 16tcr2 are ignored. phase counting takes precedence. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 309 of 764 rej09b0396-0500 bits 2 to 0 ? timer prescaler 2 to 0 (tpsc2 to tpsc0): these bits select the counter clock source. bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 function 0 0 0 internal clock: (initial value) 1 internal clock: /2 1 0 internal clock: /4 1 internal clock: /8 1 0 0 external clock a: tclka input 1 external clock b: tclkb input 1 0 external clock c: tclkc input 1 external clock d: tclkd input when bit tpsc2 is cleared to 0 an internal clock source is sel ected, and the timer counts only falling edges. when bit tpsc2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits ckeg1 and ckeg0. when channel 2 is set to phase counting mode (mdf = 1 in tmdr), the settings of bits tpsc2 to tpsc0 in 16tcr2 are ignored. phase counting takes precedence. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 310 of 764 rej09b0396-0500 9.2.10 timer i/o control register (tior) tior is an 8-bit register. the 16-bit timer has three ti ors, one in each channel. channel abbreviation function 0 tior0 1 tior1 tior controls the general registers. some functions differ in pwm mode. 2 tior2 bit initial value read/write 7 ? 1 ? 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ? 1 ? 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w i/o control a2 to a0 these bits select gra functions reserved bit i/o control b2 to b0 these bits select grb functions reserved bit each tior is an 8-bit readable/writable register that selects the output compare or input capture function for gra and grb, and specifies the functions of the tiora and tiorc pins. if the output compare function is selected, tior also selects the type of output. if input capture is selected, tior also selects the edge or edges of the input capture signal. tior is initialized to h'88 by a reset and in standby mode. bit 7 ? reserved: this bit cannot be modified and is always read as 1. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 311 of 764 rej09b0396-0500 bits 6 to 4 ? i/o control b2 to b0 (iob2 to iob0): these bits select the grb function. bit 6 iob2 bit 5 iob1 bit 4 iob0 function 0 0 0 no output at compare match (initial value) 1 grb is an output compare register 0 output at grb compare match * 1 1 0 1 output at grb compare match * 1 1 output toggles at grb compare match (1 output in channel 2) * 1 * 2 1 0 0 grb captures rising edge of input 1 grb is an input compare register grb captures falling edge of input 1 0 grb captures both edges of input 1 notes: 1. after a reset, the output conforms to the tolr setting until the first compare match. 2. channel 2 output cannot be toggled by compare match. this setting selects 1 output instead. bit 3 ? reserved: this bit cannot be modified and is always read as 1. bits 2 to 0 ? i/o control a2 to a0 (ioa2 to ioa0): these bits select the gra function. bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 function 0 0 0 no output at compare match (initial value) 1 gra is an output compare register 0 output at gra compare match * 1 1 0 1 output at gra compare match * 1 1 output toggles at gra compare match (1 output in channel 2) * 1 * 2 1 0 0 gra captures rising edge of input 1 gra is an input compare register gra captures falling edge of input 1 0 gra captures both edges of input 1 notes: 1. after a reset, the output conforms to the tolr setting until the first compare match. 2. channel 2 output cannot be toggled by compare match. this setting selects 1 output instead. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 312 of 764 rej09b0396-0500 9.2.11 timer output level setting register c (tolr) tolr is an 8-bit write-only register that selects the timer output level for channels 0 to 2. 7 ? 1 ? bit initial value read/write 6 ? 1 ? 5 tob2 0 w 4 toa2 0 w 3 tob1 0 w 2 toa1 0 w 1 tob0 0 w 0 toa0 0 w reserved bits output level setting a2 to a0, b2 to b0 these bits set the levels of the timer outputs (tioca 2 to tioca 0 , and tiocb 2 to tiocb 0 ) a tolr setting can only be made when the corresponding bit in tstr is 0. tolr is a write-only register. if it is read, all bits will return a value of 1. tolr is initialized to h'c0 by a reset and in standby mode. bits 7 and 6 ? reserved: these bits cannot be modified. bit 5 ? output level setting b2 (tob2): sets the value of timer output tiocb 2 . bit 5 tob2 description 0 tiocb 2 is 0 (initial value) 1 tiocb 2 is 1 bit 4 ? output level setting a2 (toa2): sets the value of timer output tioca 2 . bit 4 toa2 description 0 tioca 2 is 0 (initial value) 1 tioca 2 is 1 9. 16-bit timer rev.5.00 sep. 12, 2007 page 313 of 764 rej09b0396-0500 bit 3 ? output level setting b1 (tob1): sets the value of timer output tiocb 1 . bit 3 tob1 description 0 tiocb 1 is 0 (initial value) 1 tiocb 1 is 1 bit 2 ? output level setting a1 (toa1): sets the value of timer output tioca 1 . bit 2 toa1 description 0 tioca 1 is 0 (initial value) 1 tioca 1 is 1 bit 1 ? output level setting b0 (tob0): sets the value of timer output tiocb 0 . bit 0 tob0 description 0 tiocb 0 is 0 (initial value) 1 tiocb 0 is 1 bit 0 ? output level setting a0 (toa0): sets the value of timer output tioca 0 . bit 0 toa0 description 0 tioca 0 is 0 (initial value) 1 tioca 0 is 1 9. 16-bit timer rev.5.00 sep. 12, 2007 page 314 of 764 rej09b0396-0500 9.3 cpu interface 9.3.1 16-bit accessible registers the timer counters (16tcnts), general registers a and b (gras and grbs) are 16-bit registers, and are linked to the cpu by an internal 16-bit data bus. these registers can be written or read a word at a time, or a byte at a time. figures 9.4 and 9.5 show examples of word read/write access to a timer counter (16tcnt). figures 9.6, 9.7, 9.8, and 9.9 show exampl es of byte read/write access to 16tcnth and 16tcntl. on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 9.4 access to timer count er (cpu writes to 16tcnt, word) on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 9.5 access to timer counter (cpu reads 16tcnt, word) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 315 of 764 rej09b0396-0500 on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 9.6 access to timer counter (c pu writes to 16tcnth, upper byte) on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 9.7 access to timer counter (c pu writes to 16tcntl, lower byte) on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 9.8 access to timer count er (cpu reads 16tcnth, upper byte) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 316 of 764 rej09b0396-0500 on-chip data bus cpu h l bus interface h l module data bus 16tcnth 16tcntl figure 9.9 access to timer count er (cpu reads 16tcntl, lower byte) 9.3.2 8-bit accessible registers the registers other than the timer counters and gene ral registers are 8-bit registers. these registers are linked to the cpu by an internal 8-bit data bus. figures 9.10 and 9.11 show examples of byte read and write access to a 16tcr. if a word-size data transfer instruction is executed, two byte transfers are performed. on-chip data bus cpu h l bus interface h l module data bus 16tcr figure 9.10 16tcr access (cpu writes to 16tcr) on-chip data bus cpu h l bus interface h l module data bus 16tcr figure 9.11 16tcr access (cpu reads 16tcr) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 317 of 764 rej09b0396-0500 9.4 operation 9.4.1 overview a summary of operations in the various modes is given below. normal operation: each channel has a timer counter and general registers. the timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. general registers a and b can be used for input capture or output compare. synchronous operation: the timer counters in designated channels are preset synchronously. data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. the timer counters can also be cleared synchronously if so designated by the cclr1 and cclr0 bits in the 16tcrs. pwm mode: a pwm waveform is output from the tioca pin. the output goes to 1 at compare match a and to 0 at compare match b. the duty cycle can be varied from 0 % to 100 % depending on the settings of gra and grb. when a channel is set to pwm mode, its gra and grb automatically become out put compare registers. phase counting mode: the phase relationship between two clock signals input at tclka and tclkb is detected and 16tcnt2 counts up or down accordingly. when phase counting mode is selected tclka and tclkb become clock input pins and 16tcnt2 operates as an up/down- counter. 9.4.2 basic functions counter operation: when one of bits str0 to str2 is set to 1 in the timer start register (tstr), the timer counter (16tcnt) in the corresponding channel starts counting. the counting can be free-running or periodic. ? sample setup procedure for counter figure 9.12 shows a sample procedure for setting up a counter. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 318 of 764 rej09b0396-0500 counter setup select counter clock type of countin g ? periodic countin g select counter clear source select output compare re g ister function set period start counter free-runnin g countin g start counter periodic counter free-runnin g counter 1 ye s no 2 3 4 55 figure 9.12 counter setup procedure (example) 1. set bits tpsc2 to tpsc0 in 16tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in 16tcr to select the desired edge(s) of the external clock signal. 2. for periodic counting, set cclr1 and cclr0 in 16tcr to have 16tcnt cleared at gra compare match or grb compare match. 3. set tior to select the output compare function of gra or grb, whichever was selected in step 2. 4. write the count period in gra or grb, whichever was selected in step 2. 5. set the str bit to 1 in tstr to start the timer counter. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 319 of 764 rej09b0396-0500 ? free-running and periodic counter operation a reset leaves the counters (16tcnts) in 16-bit timer channels 0 to 2 all set as free-running counters. a free-running counter starts counting up when the corresponding bit in tstr is set to 1. when the count overflows from h'ffff to h'0000, the ovf flag is set to 1 in tisrc. after the overflow, the counter continues co unting up from h'0000. figure 9.13 illustrates free-running counting. 16tcnt value h'ffff h'0000 str0 to str2 bit ovf time figure 9.13 free-running counter operation when a channel is set to have its counter cleared by compare match, in that channel 16tcnt operates as a periodic counter. select the output compare function of gra or grb, set bit cclr1 or cclr0 in 16tcr to have the counter cleared by compare match, and set the count period in gra or grb. after these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in tstr. when the count matches gra or grb, the imfa or imfb flag is set to 1 in tisra/tisrb and the counter is cleared to h'0000. if the corresponding imiea or imieb bit is set to 1 in tisra/tisrb, a cpu interrupt is requested at this time. after the compare match, 16tcnt continues counting up from h'0000. figure 9.14 illustrates periodic counting. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 320 of 764 rej09b0396-0500 16tcnt value gr h'0000 str bit imf time counter cleared by g eneral re g ister compare match figure 9.14 period ic counter operation ? 16tcnt count timing ? internal clock source bits tpsc2 to tpsc0 in 16tcr select the system clock ( ) or one of three internal clock sources obtained by prescaling the system clock ( /2, /4, /8). figure 9.15 shows the timing. 16tcnt internal clock n ? 1 n n + 1 16tcnt input clock figure 9.15 count timing for internal clock sources ? external clock source bits tpsc2 to tpsc0 in 16tcr select an external clock input pin (tclka to tclkd), and its valid edge or edges are selected by bits ckeg1 and ckeg0. the rising edge, falling edge, or both edges can be selected. the pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edge s are selected. shorter pulses will not be counted correctly. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 321 of 764 rej09b0396-0500 figure 9.16 shows the timing when both edges are detected. external clock input n ? 1 n n + 1 16tcnt input clock 16tcnt figure 9.16 count timing for external cl ock sources (when both edges are detected) waveform output by compare match: in 16-bit timer channels 0, 1 compare match a or b can cause the output at the tioca or tiocb pin to go to 0, go to 1, or toggle. in channel 2 the output can only go to 0 or go to 1. ? sample setup procedure for waveform output by compare match figure 9.17 shows an example of the setup procedure for waveform output by compare match. output setup select waveform output mode set output timin g start counter waveform output select the compare match output mode (0, 1, or to gg le) in tior. when a waveform output mode is selected, the pin switches from its g eneric input/ output function to the output compare function (tioca or tiocb). an output compare pin outputs the value set in tolr until the first compare match occurs. set a value in gra or grb to desi g nate the compare match timin g . set the str bit to 1 in tstr to start the timer counter. 1 2 3 1. 2. 3. figure 9.17 setup procedure for wavefo rm output by compare match (example) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 322 of 764 rej09b0396-0500 ? examples of waveform output figure 9.18 shows examples of 0 and 1 output. 16tcnt operates as a free-running counter, 0 output is selected for compare match a, and 1 ou tput is selected for compare match b. when the pin is already at the selected output level, the pin level does not change. time h'ffff grb tiocb tioca gra no chan g e no chan g e no chan g e no chan g e 1 output 0 output 16tcnt value h'0000 figure 9.18 0 and 1 output (toa = 1, tob = 0) figure 9.19 shows examples of toggle output. 16tcnt operates as a periodic counter, cleared by compare match b. toggle output is sel ected for both compare match a and b. grb tiocb tioca gra 16tcnt value time counter cleared by compare match with grb to gg le output to gg le output h'0000 figure 9.19 toggle output (toa = 1, tob = 0) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 323 of 764 rej09b0396-0500 ? output compare output timing the compare match signal is generated in the last state in which 16tcnt and the general register match (when 16tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the output compare pin (tioca or tiocb). when 16tcnt matches a general register, the compare match signal is not generated until the next counter clock pulse. figure 9.20 shows the output compare timing. n + 1 n n 16tcnt input clock 16tcnt gr compare match si g nal tioca, tiocb figure 9.20 output compare output timing input capture function: the 16tcnt value can be captured into a general register when a transition occurs at an input capture/output compare pin (tioca or tiocb). capture can take place on the rising edge, falling edge, or both edges. the input capture function can be used to measure pulse width or period. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 324 of 764 rej09b0396-0500 ? sample setup procedure for input capture figure 9.21 shows a sample procedure for setting up input capture. input selection select input-capture input start counter input capture set tior to select the input capture function of a g eneral re g ister and the risin g ed g e, fallin g ed g e, or both ed g es of the input capture si g nal. clear the ddr bit to 0 before makin g these tior settin g s. set the str bit to 1 in tstr to start the timer counter. 1 2 1. 2. figure 9.21 setup procedure for input capture (example) ? examples of input capture figure 9.22 illustrates input capture when the falling edge of tiocb and both edges of tioca are selected as capture edges. 16tcnt is cleared by input capture into grb. h'0005 h'0180 h'0180 h'0160 h'0005 h'0000 tiocb tioca gra grb 16tcnt value h'0160 figure 9.22 input capture (example) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 325 of 764 rej09b0396-0500 ? input capture signal timing input capture on the rising edge, falling edge, or both edges can be sel ected by settings in tior. figure 9.23 shows the timing when the rising edge is selected. the pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. n n input-capture input input capture si g nal 16tcnt gra, grb figure 9.23 input capture signal timing 9.4.3 synchronization the synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). with appropriate 16tcr settings, two or more timer counters can also be cleared simultaneously (synchronous clear). synchronization enables additional general registers to be associated with a single time base. synchronization can be selected for all channels (0 to 2). 9. 16-bit timer rev.5.00 sep. 12, 2007 page 326 of 764 rej09b0396-0500 sample setup procedure for synchronization: figure 9.24 shows a sample procedure for setting up synchronization. setup for synchronization synchronous preset set the sync bits to 1 in tsnc for the channels to be synchronized. when a value is written in 16tcnt in one of the synchronized channels, the same value is simultaneously written in 16tcnt in the other channels. 1. 2. 2 3 1 5 4 5 select synchronization synchronous preset write to 16tcnt synchronous clear clearin g synchronized to this channel? select counter clear source start counter counter clear synchronous clear start counter select counter clear source ye s no set the cclr1 or cclr0 bit in 16tcr to have the counter cleared by compare match or input capture. set the cclr1 and cclr0 bits in 16tcr to have the counter cleared synchronously. set the str bits in tstr to 1 to start the synchronized counters. 3. 4. 5. figure 9.24 setup procedure for synchronization (example) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 327 of 764 rej09b0396-0500 example of synchronization: figure 9.25 shows an example of synchronization. channels 0, 1, and 2 are synchronized, and are set to operate in pwm mode. channel 0 is set for counter clearing by compare match with grb0. channels 1 and 2 are set for synchronous counter clearing. the timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with grb0. a three-phase pwm waveform is output from pins tioca 0 , tioca 1 , and tioca 2 . for further information on pwm mode, see section 9.4.4, pwm mode. tioca 2 tioca 1 tioca 0 gra2 gra1 grb2 gra0 grb1 grb0 value of 16tcnt0 to 16tcnt2 synchronous clearin g by grb0 compare match h'0000 figure 9.25 synchronization (example) 9.4.4 pwm mode in pwm mode gra and grb are paired and a pwm waveform is output from the tioca pin. gra specifies the time at which the pwm output ch anges to 1. grb specifies the time at which the pwm output changes to 0. if either gra or grb is selected as the counter clear source, a pwm waveform with a duty cycle from 0 % to 100 % is output at the tioca pin. pwm mode can be selected in all channels (0 to 2). table 9.4 summarizes the pwm output pins and corresponding registers. if the same value is set in gra and grb, the output does not change when compare match occurs. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 328 of 764 rej09b0396-0500 table 9.4 pwm output pins and registers channel output pin 1 output 0 output 0 tioca 0 gra0 grb0 1 tioca 1 gra1 grb1 2 tioca 2 gra2 grb2 sample setup procedure for pwm mode: figure 9.26 shows a sample procedure for setting up pwm mode. pwm mode 1. set bits tpsc2 to tpsc0 in 16tcr to select the counter clock source. if an external clock source is selected, set bits ckeg1 and ckeg0 in 16tcr to select the desired ed g e(s) of the external clock si g nal. pwm mode select counter clock 1 select counter clear source 2 set gra 3 set grb 4 select pwm mode 5 start counter 6 2. set bits cclr1 and cclr0 in 16tcr to select the counter clear source. 3. set the time at which the pwm waveform should g o to 1 in gra. 4. set the time at which the pwm waveform should g o to 0 in grb. 5. set the pwm bit in tmdr to select pwm mode. when pwm mode is selected, re g ardless of the tior contents, gra and grb become output compare re g isters specifyin g the times at which the pwm output g oes to 1 and 0. the tioca pin automatically becomes the pwm output pin. the tiocb pin conforms to the settin g s of bits iob1 and iob0 in tior. if tiocb output is not desired, clear both iob1 and iob0 to 0. 6. set the str bit to 1 in tstr to start the timer counter. figure 9.26 setup procedu re for pwm mode (example) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 329 of 764 rej09b0396-0500 examples of pwm mode: figure 9.27 shows examples of operation in pwm mode. in pwm mode tioca becomes an output pin. the output goes to 1 at compare match with gra, and to 0 at compare match with grb. in the examples shown, 16tcnt is cleared by compare match with gra or grb. synchronized operation and free-running counting are also possible. 16tcnt value counter cleared by compare match a time gra grb tioca a. counter cleared by gra (toa = 1) 16tcnt value counter cleared by compare match b time grb gra tioca b. counter cleared by grb (toa = 0) h'0000 h'0000 figure 9.27 pwm mode (example 1) figure 9.28 shows examples of the output of pwm waveforms with duty cycles of 0 % and 100 % . if the counter is cleared by compare match with g rb, and gra is set to a higher value than grb, 9. 16-bit timer rev.5.00 sep. 12, 2007 page 330 of 764 rej09b0396-0500 the duty cycle is 0 % . if the counter is cleared by compare match with gra, and grb is set to a higher value than gra, the duty cycle is 100 % . 16tcnt value counter cleared by compare match b time grb gra tioca a. 0 % duty cycle (toa = 0) 16tcnt value counter cleared by compare match a time gra grb tioca b. 100 % duty cycle (toa = 1) write to gra write to gra write to grb write to grb h'0000 h'0000 figure 9.28 pwm mode (example 2) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 331 of 764 rej09b0396-0500 9.4.5 phase counting mode in phase counting mode the phase difference between two external clock inputs (at the tclka and tclkb pins) is detect ed, and 16tcnt2 counts up or down accordingly. in phase counting mode, the tclka and tclkb pins automatically function as external clock input pins and 16tcnt2 becomes an up/down-counter, regardless of the settings of bits tpsc2 to tpsc0, ckeg1, and ckeg0 in 16tcr2. settings of bits cclr1, cclr0 in 16tcr2, and settings in tior2, tisra, tisrb, tisrc, st r2 in tstr, gra2, and grb2 are valid. the input capture and output compare functions can be used, and interrupts can be generated. phase counting is available only in channel 2. sample setup procedure for phase counting mode: figure 9.29 shows a sample procedure for setting up phase counting mode. phase countin g mode select phase countin g mode select fla g settin g condition start counter 1 2 3 phase countin g mode 1. 2. 3. set the mdf bit in tmdr to 1 to select phase countin g mode. select the fla g settin g condition with the fdir bit in tmdr. set the str2 bit to 1 in tstr to start the timer counter. figure 9.29 setup procedure for phase counting mode (example) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 332 of 764 rej09b0396-0500 example of phase counting mode: figure 9.30 shows an example of operations in phase counting mode. table 9.5 lists the up-counting and down-counting conditions for 16tcnt2. in phase counting mode both the rising and falling edges of tclka and tclkb are counted. the phase difference between tclka and tclkb must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pul se width must be at least 2.5 states. 16tcnt2 value countin g up countin g down tclkb tclka figure 9.30 operation in phase counting mode (example) table 9.5 up/down counting conditions counting direction down-counting up-counting tclkb pin high low high low tclka pin low high low high tclka tclkb phase difference phase difference pulse width pulse width overlap overlap phase difference and overlap: pulse width: at least 1.5 states at least 2.5 states figure 9.31 phase differen ce, overlap, and pulse widt h in phase counting mode 9. 16-bit timer rev.5.00 sep. 12, 2007 page 333 of 764 rej09b0396-0500 9.4.6 setting initial value of 16-bit timer output any desired value can be specified for the initial 16-bit timer output value when a timer count operation is started by making a setting in tolr. figure 9.32 shows the timing for setting the initial output value with tolr. only write to tolr when the correspo nding bit in tstr is cleared to 0. t 1 tolr address n n t 2 t 3 address bus tolr 16-bit timer output pin figure 9.32 example of timing for setting initial value of 16-bit timer output by writing to tolr 9. 16-bit timer rev.5.00 sep. 12, 2007 page 334 of 764 rej09b0396-0500 9.5 interrupts the 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 setting of status flags timing of setting of imfa and imfb at compare match: imfa and imfb are set to 1 by a compare match signal generated when 16tcnt matches a general register (gr). the compare match signal is generated in the last state in which the values match (when 16tcnt is updated from the matching count to the next count). therefore, when 16tcnt matches a general register, the compare match signal is not generated until th e next 16tcnt clock input . figure 9.33 shows the timing of the setting of imfa and imfb. 16tcnt gr imf imi 16tcnt input clock compare match si g nal nn + 1 n figure 9.33 timing of setting of imfa and imfb by compare match 9. 16-bit timer rev.5.00 sep. 12, 2007 page 335 of 764 rej09b0396-0500 timing of setting of imfa and imfb by input capture: imfa and imfb are set to 1 by an input capture signal. the 16tcnt contents are simultaneously transferred to the corresponding general register. figure 9.34 shows the timing. input capture si g nal n n imf 16tcnt gr imi figure 9.34 timing of setting of imfa and imfb by input capture timing of setting of overflow flag (ovf): ovf is set to 1 when 16tcnt overflows from h'ffff to h'0000 or underflows from h'00 00 to h'ffff. figure 9. 35 shows the timing. overflow si g nal 16tcnt ovf ovi figure 9.35 timing of setting of ovf 9. 16-bit timer rev.5.00 sep. 12, 2007 page 336 of 764 rej09b0396-0500 9.5.2 timing of clearing of status flags if the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 9.36 shows the timing. address imf, ovf tisr write cycle tisr address t 1 t 2 t 3 figure 9.36 timing of clearing of status flags 9.5.3 interrupt sources and dma controller activation each 16-bit timer channel can generate a comp are match/input capture a interrupt, a compare match/input capture b interrupt, and an overflow interrupt. in total there are nine interrupt sources of three kinds, all independently vectored. an interrupt is requested when the interrupt request flag are set to 1. the priority order of the channels can be modified in interrupt priority register a (ipra). for details see section 5, interrupt controller. compare match/input capture a interrupts in channels 0 to 2 can activate the dma controller (dmac). when the dmac is activated a cpu interrupt is not requested. table 9.6 lists the interrupt sources. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 337 of 764 rej09b0396-0500 table 9.6 16-bit timer interrupt sources channel interrupt source description dmac activatable priority * 0 imia0 imib0 ovi0 compare match/input capture a0 compare match/input capture b0 overflow 0 yes no no high 1 imia1 imib1 ovi1 compare match/input capture a1 compare match/input capture b1 overflow 1 yes no no 2 imia2 imib2 ovi2 compare match/input capture a2 compare match/input capture b2 overflow 2 yes no no low note: * the priority immediately after a reset is indicated. inter-channel priorities can be changed by settings in ipra. 9. 16-bit timer rev.5.00 sep. 12, 2007 page 338 of 764 rej09b0396-0500 9.6 usage notes this section describes contention and other matters requiring special attention during 16-bit timer operations. contention between 16tcnt write and clear: if a counter clear signal occurs in the t 3 state of a 16tcnt write cycle, clearing of the counter takes priority and the write is not performed. see figure 9.37. address bus internal write si g nal counter clear si g nal 16tcnt 16tcnt write cycle 16tcnt address n h'0000 t 1 t 2 t 3 figure 9.37 contention be tween 16tcnt write and clear 9. 16-bit timer rev.5.00 sep. 12, 2007 page 339 of 764 rej09b0396-0500 contention between 16tcnt word write and increment: if an increment pulse occurs in the t 3 state of a 16tcnt word write cycle, writing takes priority and 16tcnt is not incremented. figure 9.38 shows the timing in this case. address bus internal write si g nal 16tcnt input clock 16tcnt n 16tcnt address m 16tcnt write data 16tcnt word write cycle t 1 t 2 t 3 figure 9.38 contention between 16tcnt word write and increment 9. 16-bit timer rev.5.00 sep. 12, 2007 page 340 of 764 rej09b0396-0500 contention between 16tcnt byte write and increment: if an increment pulse occurs in the t 2 or t 3 state of a 16tcnt byte write cycle, writing takes priority and 16tcnt is not incremented. the 16tcnt byte that was not written retains its previous value. see figure 9.39, which shows an increment pulse o ccurring in the t 2 state of a byte write to 16tcnth. address bus internal write si g nal 16tcnt input clock 16tcnth 16tcntl 16tcnth byte write cycle t 1 t 2 t 3 n 16tcnth address m 16tcnt write data xx x + 1 figure 9.39 contention between 16tcnt byte write and increment 9. 16-bit timer rev.5.00 sep. 12, 2007 page 341 of 764 rej09b0396-0500 contention between general re gister write and compare match: if a compare match occurs in the t 3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. see figure 9.40. address bus internal write si g nal 16tcnt gr compare match si g nal general re g ister write cycle t 1 t 2 t 3 n gr address m n n + 1 general re g ister write data inhibited figure 9.40 contention between gen eral register write and compare match 9. 16-bit timer rev.5.00 sep. 12, 2007 page 342 of 764 rej09b0396-0500 contention between 16tcnt writ e and overflow or underflow: if an overflow occurs in the t 3 state of a 16tcnt write cycle, writing takes priority and the counter is not incremented. ovf is set to 1. the same holds for underflow. see figure 9.41. address bus internal write si g nal 16tcnt input clock overflow si g nal 16tcnt ovf h'ffff 16tcnt address m 16tcnt write data 16tcnt write cycle t 1 t 2 t 3 figure 9.41 contention between 16tcnt write and overflow 9. 16-bit timer rev.5.00 sep. 12, 2007 page 343 of 764 rej09b0396-0500 contention between general register read and input capture: if an input capture signal occurs during the t 3 state of a general register read cycle, the value before input capture is read. see figure 9.42. address bus internal read si g nal input capture si g nal gr internal data bus gr address x general re g ister read cycle t 1 t 2 t 3 xm figure 9.42 contention between general register read and input capture 9. 16-bit timer rev.5.00 sep. 12, 2007 page 344 of 764 rej09b0396-0500 contention between counter clearing by input capture and counter increment: if an input capture signal and counter increm ent signal occur simultaneously, th e counter is cleared according to the input capture signal. the counter is not incremented by the increment signal. the value before the counter is cleared is transferred to the general register. see figure 9.43. input capture si g nal counter clear si g nal 16tcnt input clock 16tcnt gr n n h'0000 figure 9.43 contention between counter clearing by input capture and counter increment 9. 16-bit timer rev.5.00 sep. 12, 2007 page 345 of 764 rej09b0396-0500 contention between general re gister write and input capture: if an input capture signal occurs in the t 3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. see figure 9.44. address bus internal write si g nal input capture si g nal 16tcnt gr m gr address general re g ister write cycle t 1 t 2 t 3 m figure 9.44 contention between general register write and input capture note on waveform period setting: when a counter is cleared by compare match, the counter is cleared in the last state at whic h the 16tcnt value matches the general register value, at the time when this value would normally be updated to the next count. the actual counter frequency is therefore given by the following formula: f = (n +1) (f: counter frequency. : system clock frequency. n: value set in general register.) 9. 16-bit timer rev.5.00 sep. 12, 2007 page 346 of 764 rej09b0396-0500 note on writes in sy nchronized operation: when channels are synchronized, if a 16tcnt value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (example) when channels 1 and 2 are synchronized ? byte write to channel 1 or byte write to channel 2 16tcnt1 16tcnt2 w y x z 16tcnt1 16tcnt2 a a x x 16tcnt1 16tcnt2 y y a a 16tcnt1 16tcnt2 w y x z 16tcnt1 16tcnt2 a a b b ? word write to channel 1 or word write to channel 2 upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte upper byte lower byte write a to upper byte of channel 1 write a to lower byte of channel 2 write ab word to channel 1 or 2 9. 16-bit timer rev.5.00 sep. 12, 2007 page 347 of 764 rej09b0396-0500 16-bit timer operating modes table 9.7 (a) 16-bit timer operating modes (channel 0) register settings tsnc tmdr tior0 16tcr0 syn c hro- clear clo c k operating mode nization mdf fdir pwm ioa iob sele c t sele c t synchronous preset sync0 = 1 ?? pwm mode ?? pwm0 = 1 ? * output compare a ?? pwm0 = 0 ioa2 = 0 other bits unrestricted output compare b ?? iob2 = 0 other bits unrestricted input capture a ?? pwm0 = 0 ioa2 = 1 other bits unrestricted input capture b ?? pwm0 = 0 iob2 = 1 other bits unrestricted counter by compare ?? cclr1 = 0 clearin g match/input cclr0 = 1 capture a by compare ?? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync0 = 1 ?? cclr1 = 1 chronous cclr0 = 1 clear note: * the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match si g nal is inhibited. le g end: settin g available (valid) settin g does not affect this mode ? 9. 16-bit timer rev.5.00 sep. 12, 2007 page 348 of 764 rej09b0396-0500 table 9.7 (b) 16-bit timer operating modes (channel 1) register settings tsnc tmdr tior1 16tcr1 syn c hro- clear clo c k operating mode nization mdf fdir pwm ioa iob sele c t sele c t synchronous preset sync1 = 1 ?? pwm mode ?? pwm1 = 1 ? output compare a ?? pwm1 = 0 ioa2 = 0 other bits unrestricted output compare b ?? iob2 = 0 other bits unrestricted input capture a ?? pwm1 = 0 ioa2 = 1 other bits unrestricted input capture b ?? pwm1 = 0 iob2 = 1 other bits unrestricted counter by compare ?? cclr1 = 0 clearin g match/input cclr0 = 1 capture a by compare ?? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync1 = 1 ?? cclr1 = 1 chronous cclr0 = 1 clear * note: * the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match si g nal is inhibited. le g end: settin g available (valid) settin g does not affect this mode ? 9. 16-bit timer rev.5.00 sep. 12, 2007 page 349 of 764 rej09b0396-0500 table 9.7 (c) 16-bit timer operating modes (channel 2) register settings tsnc tmdr tior2 16tcr2 syn c hro- clear clo c k operating mode nization mdf fdir pwm ioa iob sele c t sele c t synchronous preset sync2 = 1 ? pwm mode ? pwm2 = 1 ? * output compare a ? pwm2 = 0 ioa2 = 0 other bits unrestricted output compare b ? iob2 = 0 other bits unrestricted input capture a ? pwm2 = 0 ioa2 = 1 other bits unrestricted input capture b ? pwm2 = 0 iob2 = 1 other bits unrestricted counter by compare ? cclr1 = 0 clearin g match/input cclr0 = 1 capture a by compare ? cclr1 = 1 match/input cclr0 = 0 capture b syn- sync2 = 1 ? cclr1 = 1 chronous cclr0 = 1 clear phase countin g mdf = 1 ? mode note: * the input capture function cannot be used in pwm mode. if compare match a and compare match b occur simultaneously, the compare match si g nal is inhibited. le g end: settin g available (valid) settin g does not affect this mode ? 9. 16-bit timer rev.5.00 sep. 12, 2007 page 350 of 764 rej09b0396-0500 10. 8-bit timers rev.5.00 sep. 12, 2007 page 351 of 764 rej09b0396-0500 section 10 8-bit timers 10.1 overview the h8/3006 and h8/3007 have a bu ilt-in 8-bit timer module with four channels (tmr0, tmr1, tmr2, and tmr3), based on 8-bit counters. each channel has an 8-bit timer counter (8tcnt) and two 8-bit time constant registers (tcora and tcorb) that are constantly compared with the 8tcnt value to detect compare match events. the timers can be used as multifunctional timers in a variety of applications, including the generation of a rectangular-wave output with an arbitrary duty cycle. 10.1.1 features the features of the 8-bit timer module are listed below. ? selection of four clock sources the counters can be driven by one of three internal clock signals ( /8, /64, or /8192) or an external clock input (enabling use as an external event counter). ? selection of three ways to clear the counters the counters can be cleared on compare match a or b, or input capture b. ? timer output controlled by two compare match signals the timer output signal in each channel is controlled by two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or pwm output. ? a/d converter can be activated by a compare match ? two channels can be cascaded ? channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). ? channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit count mode). ? channel 1 can count channel 0 compare matc h events (compare match count mode). ? channel 3 can count channel 2 compare matc h events (compare match count mode). ? input capture function can be set 8-bit or 16-bit input capture operation is available. ? twelve interrupt sources there are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 352 of 764 rej09b0396-0500 two of the compare match sources and two of th e combined compare matc h/input capture sources each have an independent interrupt vector. the remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources. 10.1.2 block diagram the 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. figure 10.1 shows a block diagram of 8-bit timer group 0. /8 /64 /8192 cmia0 cmib0 cmia1/cmib1 ovi0/ovi1 interrupt si g nals tmo 0 tmio 1 tcora0 tcorb0 8tcsr0 8tcr0 tcora1 8tcnt1 tcorb1 8tcsr1 8tcr1 tclka tclkc 8tcnt0 le g end: tcora: timer constant re g ister a tcorb: timer constant re g ister b 8tcnt: timer counter 8tcsr: timer control/status re g ister 8tcr: timer control re g ister external clock sources internal clock sources clock select control lo g ic clock 1 clock 0 compare match a1 compare match a0 overflow 1 overflow 0 compare match b1 compare match b0 input capture b1 comparator a0 comparator a1 comparator b0 comparator b1 internal bus figure 10.1 block diagram of 8-bit timer unit (two channels: group 0) 10. 8-bit timers rev.5.00 sep. 12, 2007 page 353 of 764 rej09b0396-0500 10.1.3 pin configuration table 10.1 summarizes the input/output pins of the 8-bit timer module. table 10.1 8-bit timer pins group channel name abbreviation i/o input/output 0 0 timer output tmo 0 output compare match output timer clock input tclkc input counter external clock input 1 timer input/output tmio 1 i/o compare match output/input capture input timer clock input tclka input counter external clock input 1 2 timer output tmo 2 output compare match output timer clock input tclkd input counter external clock input 3 timer input/output tmio 3 i/o compare match output/input capture input timer clock input tclkb input counter external clock input 10. 8-bit timers rev.5.00 sep. 12, 2007 page 354 of 764 rej09b0396-0500 10.1.4 register configuration table 10.2 summarizes the registers of the 8-bit timer module. table 10.2 8-bit timer registers channel address * 1 name abbreviation r/w initial value 0 h'fff80 timer control register 0 8tcr0 r/w h'00 h'fff82 timer control/status register 0 8tcsr0 r/(w) * 2 h'00 h'fff84 timer constant register a0 tcora0 r/w h'ff h'fff86 timer constant register b0 tcorb0 r/w h'ff h'fff88 timer counter 0 8tcnt0 r/w h'00 1 h'fff81 timer control register 1 8tcr1 r/w h'00 h'fff83 timer control/status register 1 8tcsr1 r/(w) * 2 h'00 h'fff85 timer constant register a1 tcora1 r/w h'ff h'fff87 timer constant register b1 tcorb1 r/w h'ff h'fff89 timer counter 1 8tcnt1 r/w h'00 2 h'fff90 timer control register 2 8tcr2 r/w h'00 h'fff92 timer control/status register 2 8tcsr2 r/(w) * 2 h'10 h'fff94 timer constant register a2 tcora2 r/w h'ff h'fff96 timer constant register b2 tcorb2 r/w h'ff h'fff98 timer counter 2 8tcnt2 r/w h'00 3 h'fff91 timer control register 3 8tcr3 r/w h'00 h'fff93 timer control/status register 3 8tcsr3 r/(w) * 2 h'00 h'fff95 timer constant register a3 tcora3 r/w h'ff h'fff97 timer constant register b3 tcorb3 r/w h'ff h'fff99 timer counter 3 8tcnt3 r/w h'00 notes: 1. indicates the lower 20 bits of the address in advanced mode. 2. only 0 can be written to bits 7 to 5, to clear these flags. each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the channel 0 register as the upper 8 bits and the channel 1 register as the lower 8 bits, so they can be accessed together by word access. similarly, each pair of registers for channel 2 a nd channel 3 comprises a 16-bit register with the channel 2 register as the upper 8 bits and the channel 3 register as the lower 8 bits, so they can be accessed together by word access. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 355 of 764 rej09b0396-0500 10.2 register descriptions 10.2.1 timer counters (8tcnt) 15 0 r/w bit initial value read/write 14 0 r/w bit initial value read/write 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 8tcnt0 8tcnt1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w 8tcnt2 8tcnt3 the timer counters (8tcnt) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. the clock source is selected by clock select bits 2 to 0 (cks2 to cks0) in the timer contro l register (8tcr). the cpu can always read or write to the timer counters. the 8tcnt0 and 8tcnt1 pair, and the 8tcnt2 and 8tcnt3 pair, can each be accessed as a 16-bit register by word access. 8tcnt can be cleared by an input capture signal or compare match signal. counter clear bits 1 and 0 (cclr1 and cclr0) in 8tcr select the method of clearing. when 8tcnt overflows from h'ff to h'00, the overflow flag (ovf) in the timer control/status register (8tcsr) is set to 1. each 8tcnt is initialized to h'00 by a reset and in standby mode. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 356 of 764 rej09b0396-0500 10.2.2 time constant registers a (tcora) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora2 tcora3 bit initial value read/write bit initial value read/write tcora0 to tcora3 are 8-bit readable/writable registers. the tcora0 and tcora1 pair, and the tcora2 and tcora3 pair, can each be accessed as a 16-bit register by word access. the tcora value is constantly compared with th e 8tcnt value. when a match is detected, the corresponding compare match flag a (cmfa) is set to 1 in 8tcsr. the timer output can be freely controlled by these compare match signals and the settings of output select bits 1 and 0 (os1, os0) in 8tcsr. each tcora register is initialized to h'ff by a reset and in standby mode. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 357 of 764 rej09b0396-0500 10.2.3 time constant registers b (tcorb) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb2 tcorb3 bit initial value read/write bit initial value read/write tcorb0 to tcorb3 are 8-bit readable/writable registers. the tcorb0 and tcorb1 pair, and the tcorb2 and tcorb3 pair, can each be accessed as a 16-bit register by word access. the tcorb value is constantly compared with th e 8tcnt value. when a match is detected, the corresponding compare match flag b (cmfb) is set to 1 in 8tcsr*. the timer output can be freely controlled by these compare match signals and the settings of output/input capture edge select bits 3 and 2 (ois3, ois2) in 8tcsr. when tcorb is used for input capture, it stores the 8tcnt value on detection of an external input capture signal. at this time, the cmfb flag is set to 1 in the corresponding 8tcsr register. the detected edge of the input capture signal is set in 8tcsr. each tcorb register is initialized to h'ff by a reset and in standby mode. note: * when channel 1 and channel 3 are designated for tcorb input capture, the cmfb flag is not set by a channel 0 or channel 2 compare match b. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 358 of 764 rej09b0396-0500 10.2.4 timer control register (8tcr) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write 8tcr is an 8-bit readable/writable register that selects the input clock source and the time at which 8tcnt is cleared, and enables interrupts. 8tcr is initialized to h'00 by a reset and in standby mode. for the timing, see section 10.4, operation. bit 7 ? compare match interrupt enable b (cmieb): enables or disables the cmib interrupt request when the cmfb flag is set to 1 in 8tcsr. bit 7 cmieb description 0 cmib interrupt requested by cmfb is disabled (initial value) 1 cmib interrupt requested by cmfb is enabled bit 6 ? compare match interrupt enable a (cmiea): enables or disables the cmia interrupt request when the cmfa flag is set to 1 in 8tcsr. bit 6 cmiea description 0 cmia interrupt requested by cmfa is disabled (initial value) 1 cmia interrupt requested by cmfa is enabled bit 5 ? timer overflow interrupt enable (ovie): enables or disables the ovi interrupt request when the ovf flag is set to 1 in 8tcsr. bit 5 ovie description 0 ovi interrupt requested by ovf is disabled (initial value) 1 ovi interrupt requested by ovf is enabled 10. 8-bit timers rev.5.00 sep. 12, 2007 page 359 of 764 rej09b0396-0500 bits 4 and 3 ? counter clear 1 and 0 (cclr1, cclr0): these bits specify the 8tcnt clearing source. compare match a or b, or input cap ture b, can be selected as the clearing source. bit 4 cclr1 bit 3 cclr0 description 0 0 clearing is disabled (initial value) 1 cleared by compare match a 1 0 cleared by compare match b/input capture b 1 cleared by input capture b note: when input capture b is set as the 8tcnt1 and 8tcnt3 counter clear source, 8tcnt0 and 8tcnt2 are not cleared by compare match b. bits 2 to 0 ? clock select 2 to 0 (csk2 to csk0): these bits select whether the clock input to 8tcnt is an internal or external clock. three internal clocks can be selected , all divided from the system clock ( ): /8, /64, and /8192. the rising edge of the selected in ternal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 360 of 764 rej09b0396-0500 when cks2, cks1, cks0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded. the incrementing clock source is different when 8tcr0 and 8tcr2 are set, and when 8tcr1 and 8tcr3 are set. bit 2 cks2 bit 1 cks1 bit 0 cks0 description 0 0 0 clock input disabled (initial value) 1 internal clock, counted on falling edge of /8 1 0 internal clock, counted on falling edge of /64 1 internal clock, counted on falling edge of /8192 1 0 0 channel 0 (16-bit count mode): count on 8tcnt1 overflow signal * 1 channel 1 (compare match count mode): count on 8tcnt0 compare match a * 1 channel 2 (16-bit count mode): count on 8tcnt3 overflow signal * 2 channel 3 (compare match count mode): count on 8tcnt2 compare match a * 2 1 external clock, counted on rising edge 1 0 external clock, counted on falling edge 1 external clock, counted on both rising and falling edges notes: 1. if the clock input of channel 0 is the 8tcnt1 overflow signal and that of channel 1 is the 8tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. 2. if the clock input of channel 2 is the 8tcnt3 overflow signal and that of channel 3 is the 8tcnt2 compare match signal, no incrementing clock is generated. do not use this setting. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 361 of 764 rej09b0396-0500 10.2.5 timer control/status registers (8tcsr) 8tcsr0 bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf adte ois3 ois2 os1 os0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w r/w 8tcsr2 bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf ? ois3 ois2 os1 os0 initial value 0 0 0 1 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * ? r/w r/w r/w r/w 8tcsr1, 8tcsr3 bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf ice ois3 ois2 os1 os0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w r/w note: * only 0 can be written to bits 7 to 5, to clear these flags. the timer control/status registers (8tcsr) are 8-bit registers that indicate compare match/input capture and timer overflow statuses, and control compare match output/input capture edge selection. each 8tcsr is initialized to h'00 by a reset and in standby mode. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 362 of 764 rej09b0396-0500 bit 7 ? compare match/input capture flag b (cmfb): status flag th at indicates the occurrence of a tcorb compare match or input capture. bit 7 cmfb description 0 [clearing condition] (initial value) read cmfb when cmfb = 1, then write 0 in cmfb 1 [setting conditions] ? 8tcnt = tcorb * ? the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register note: * when bit ice is set to 1 in 8tcsr1 and 8tcsr3, the cmfb flag is not set when 8tcnt0 = tcorb0 or 8tcnt2 = tcorb2. bit 6 ? compare match flag a (cmfa): status flag that indicates the occurrence of a tcora compare match. bit 6 cmfa description 0 clearing condition (initial value) read cmfa when cmfa = 1, then write 0 in cmfa 1 setting condition 8tcnt = tcora bit 5 ? timer overflow flag (ovf): status flag that indicates that the 8tcnt has overflowed (h'ff h'00). bit 5 ovf description 0 clearing condition (initial value) read ovf when ovf = 1, then write 0 in ovf 1 setting condition 8tcnt overflows from h'ff to h'00 10. 8-bit timers rev.5.00 sep. 12, 2007 page 363 of 764 rej09b0396-0500 bit 4 ? a/d trigger enable (adte) (8tcsr0): in combination with trge in the a/d control register (adcr), enables or disables a/d converter start requests by compare match a or an external trigger. bit 4 of 8tcsr2 is reserved, but can be read and written. trge * bit 4 adte description 0 0 a/d converter start requests by compare match a or an external trigger pin ( adtrg ) input are disabled (initial value) 1 a/d converter start requests by compare match a or an external trigger pin ( adtrg ) input are disabled 1 0 a/d converter start requests by an external trigger pin ( adtrg ) are enabled, and a/d converter start requests by compare match a are disabled 1 a/d converter start requests by compare match a are enabled, and a/d converter start requests by an external trigger pin ( adtrg ) are disabled note: * trge is bit 7 of the a/d control register (adcr). bit 4 ? reserved (in 8tcsr1): this bit is a reserved bit, but can be read and written. bit 4 ? input capture enable (ice) (in 8tcsr1 and 8tcsr3): selects the function of tcorb1 and tcorb3. bit 4 ice description 0 tcorb1 and tcorb3 are compare match registers (initial value) 1 tcorb1 and tcorb3 are input capture registers when bit ice is set to 1 in 8tcsr1 or 8tcsr3, the operation of the tcora and tcorb registers in channels 0 to 3 is as shown in the tables below. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 364 of 764 rej09b0396-0500 table 10.3 operation of channels 0 and 1 when bit ice is set to 1 in 8tcsr1 register register register function status flag change timer output capture input interrupt request tcora0 compare match operation cmfa changed from 0 to 1 in 8tcsr0 by compare match tmo 0 output controllable cmia0 interrupt request generated by compare match tcorb0 compare match operation cmfb not changed from 0 to 1 in 8tcsr0 by compare match no output from tmo 0 cmib0 interrupt request not generated by compare match tcora1 compare match operation cmfa changed from 0 to 1 in 8tcsr1 by compare match tmio 1 is dedicated input capture pin cmia1 interrupt request generated by compare match tcorb1 input capture operation cmfb changed from 0 to 1 in 8tcsr1 by input capture tmio 1 is dedicated input capture pin cmib1 interrupt request generated by input capture table 10.4 operation of channels 2 and 3 when bit ice is set to 1 in 8tcsr3 register register register function status flag change timer output capture input interrupt request tcora2 compare match operation cmfa changed from 0 to 1 in 8tcsr2 by compare match tmo 2 output controllable cmia2 interrupt request generated by compare match tcorb2 compare match operation cmfb not changed from 0 to 1 in 8tcsr2 by compare match no output from tmo 2 cmib2 interrupt request not generated by compare match tcora3 compare match operation cmfa changed from 0 to 1 in 8tcsr3 by compare match tmio 3 is dedicated input capture pin cmia3 interrupt request generated by compare match tcorb3 input capture operation cmfb changed from 0 to 1 in 8tcsr3 by input capture tmio 3 is dedicated input capture pin cmib3 interrupt request generated by input capture bits 3 and 2 ? output/input capture edge select b3 and b2 (ois3, ois2): in combination with the ice bit in 8tcsr1 (8tcsr3), these bits select the compare match b output level or the input capture input detected edge. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 365 of 764 rej09b0396-0500 the function of tcorb1 (tcorb3) depends on the setting of bit 4 of 8tcsr1 (8tcsr3). tcorb0 and tcorb2 function as compare match registers regardless of the setting of bit 4 of 8tcsr1 (8tcsr3). ice bit in 8tcsr1 (8tcsr3) bit 3 ois3 bit 2 ois2 description 0 0 0 no change when compare match b occurs (initial value) 1 0 is output when compare match b occurs 1 0 1 is output when compare match b occurs 1 output is inverted when compare match b occurs (toggle output) 1 0 0 tcorb input capture on rising edge 1 tcorb input capture on falling edge 1 0 tcorb input capture on both rising and falling edges 1 ? when the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. ? if compare match a and b occur simultaneously , the output changes in accordance with the higher-priority compare match. ? when bits ois3, ois2, os1, and os0 are a ll cleared to 0, timer output is disabled. bits 1 and 0 ? output select a1 and a0 (os1, os0): these bits select the compare match a output level. bit 1 os1 bit 0 os0 description 0 0 no change when compare match a occurs (initial value) 1 0 is output when compare match a occurs 1 0 1 is output when compare match a occurs 1 output is inverted when compare match a occurs (toggle output) ? when the compare match register function is used, the timer output priority order is: toggle output > 1 output > 0 output. ? if compare match a and b occur simultaneously , the output changes in accordance with the higher-priority compare match. ? when bits ois3, ois2, os1, and os0 are a ll cleared to 0, timer output is disabled. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 366 of 764 rej09b0396-0500 10.3 cpu interface 10.3.1 8-bit registers 8tcnt, tcora, tcorb, 8tcr, and 8tcsr are 8-b it registers. these registers are connected to the cpu by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time. figures 10.2 and 10.3 show the operation in word read and write accesses to 8tcnt. figures 10.4 to 10.7 show the operation in byte read and write accesses to 8tcnt0 and 8tcnt1. 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 10.2 8tcnt access operation (cpu writes to 8tcnt, word) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 10.3 8tcnt access operation (cpu reads 8tcnt, word) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 10.4 8tcnth access operation (c pu writes to 8tcnth, upper byte) 10. 8-bit timers rev.5.00 sep. 12, 2007 page 367 of 764 rej09b0396-0500 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 10.5 8tcnt1 access operation (cpu writes to 8tcnt1, lower byte) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 10.6 8tcnt0 acces s operation (cpu read s 8tcnt0, upper byte) 8tcnt0 8tcnt1 h l h l c p u internal data bus bus interface module data bus figure 10.7 8tcnt1 acces s operation (cpu read s 8tcnt1, lower byte) 10. 8-bit timers rev.5.00 sep. 12, 2007 page 368 of 764 rej09b0396-0500 10.4 operation 10.4.1 8tcnt count timing 8tcnt is incremented by input clock pulses (either internal or external). internal clock: three different internal clock signals ( /8, /64, or /8192) divided from the system clock ( ) can be selected by setting bits cks2 to cks0 in 8tcr. figure 10.8 shows the count timing. 8tcnt n ? 1 n n + 1 internal clock 8tcnt input clock figure 10.8 count timing for internal clock input note: even when the same internal clock is selected for both the 16- and 8-bit timers, they do not operate in the same manner because the count-up edge differs. external clock: three incrementation methods can be selected by setting bits cks2 to cks0 in 8tcr: on the rising edge, the falling e dge, and both rising and falling edges. the pulse width of the external clock signal must be at least 1.5 serial clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. shorter pulses will not be counted correctly. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 369 of 764 rej09b0396-0500 figure 10.9 shows the timing for incrementation on both edges of the external clock signal. 8tcnt n ? 1 n n + 1 external clock input 8tcnt input clock figure 10.9 count timing for external clock input (when detecting the both edges) 10.4.2 compare match timing timer output timing: when compare match a or b occurs, the timer output is as specified by the ois3, ois2, os1, and os0 bits in 8tcsr (unchanged, 0 output, 1 output, or toggle output). figure 10.10 shows the timing when the output is set to toggle on compare match a. compare match a si g nal timer output figure 10.10 timing of timer output 10. 8-bit timers rev.5.00 sep. 12, 2007 page 370 of 764 rej09b0396-0500 clear by compare match: depending on the setting of the cclr1 and cclr0 bits in 8tcr, 8tcnt can be cleared when compare match a or b occurs. figure 10.11 shows the timing of this operation. n h'00 8tcnt compare match si g nal figure 10.11 timing of clear by compare match clear by input capture: depending on the setting of the cclr1 and cclr0 bits in 8tcr, 8tcnt can be cleared when input capture b occurs. figure 10.12 shows the timing of this operation. input capture si g nal input capture input 8tcnt nh '00 figure 10.12 timing of clear by input capture 10. 8-bit timers rev.5.00 sep. 12, 2007 page 371 of 764 rej09b0396-0500 10.4.3 input capture signal timing input capture on the rising edge, falling edge, or both edges can be selected by settings in 8tcsr. figure 10.13 shows the timing when the rising edge is selected. the pulse width of the input capture input signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. input capture si g nal input capture input 8tcnt n tcorb n figure 10.13 timing of input capture input signal 10. 8-bit timers rev.5.00 sep. 12, 2007 page 372 of 764 rej09b0396-0500 10.4.4 timing of status flag setting timing of cmfa/cmfb flag settin g when compare match occurs: cmfa and cmfb in 8tcsr are set to 1 by the compare match signal output when the tcor and 8tcnt values match. the compare match signal is generated in the last state of the match (when the matched 8tcnt count value is updated). therefore, after the 8tcnt and tcor values match, the compare match signal is not generated until an incrementing clock pulse is generated. figure 10.14 shows the timing in this case. cmf compare match si g nal 8tcnt n n + 1 n tcor figure 10.14 cmf flag setting timing when compare match occurs timing of cmfb flag setting when input capture occurs: on generation of an input capture signal, the cmfb flag is set to 1 and at the same time the 8tcnt value is transferred to tcorb. figure 10.15 shows the timing in this case. cmfb input capture si g nal 8tcnt n n tcorb figure 10.15 cmfb flag setting ti ming when input capture occurs 10. 8-bit timers rev.5.00 sep. 12, 2007 page 373 of 764 rej09b0396-0500 timing of overflow flag (ovf) setting: the ovf flag in 8tcsr is set to 1 by the overflow signal generated when 8tcnt overflows (from h'ff to h'00). figure 10.16 shows the timing in this case. ovf overflow si g nal 8tcnt h'ff h'00 figure 10.16 timing of ovf setting 10.4.5 operation with cascaded connection if bits cks2 to cks0 are set to (100) in either 8tcr0 or 8tcr1, the 8-bit timers of channels 0 and 1 are cascaded. with this configuration, the two timers can be used as a single 16-bit timer (16-bit count mode), or channel 0 8-bit timer compare matches can be counted in channel 1 (compare match count mode). in this case, the timer operates as below. similarly, if bits cks2 to cks0 are set to (100) in either 8tcr2 or 8tcr3, the 8-bit timers of channels 2 and 3 are cascaded. with this configuration, the two timers can be used as a single 16-bit timer (16-bit count mode), or channel 2 8-bit timer compare matche s can be counted in channel 3 (compare match count mode). timer operation in these cases is described below. 16-bit count mode ? channels 0 and 1: when bits cks2 to cks0 are set to (100) in 8tcr0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ? setting when compare match occurs ? the cmf flag is set to 1 in 8tcr0 when a 16-bit compare match occurs. ? the cmf flag is set to 1 in 8tcr1 when a lower 8-bit compare match occurs. ? tmo0 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr0 is in accordance with the 16-bit compare match conditions. ? tmio1 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr1 is in accordance with the lower 8-bit compare match conditions. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 374 of 764 rej09b0396-0500 ? setting when input capture occurs ? the cmfb flag is set to 1 in 8tcr0 and 8tcr1 when the ice bit is 1 in 8tcsr1 and input capture occurs. ? tmio 1 pin input capture input signal edge detection is selected by bits ois3 and ois2 in 8tcsr0. ? counter clear specification ? if counter clear on compare match or input capture has been selected by the cclr1 and cclr0 bits in 8tcr0, the 16-bit counter (both 8tcnt0 and 8tcnt1) is cleared. ? the settings of the cclr1 and cclr0 bits in 8tcr1 are ignored. the lower 8 bits cannot be cleared independently. ? ovf flag operation ? the ovf flag is set to 1 in 8tcsr0 when the 16-bit counter (8tcnt0 and 8tcnt1) overflows (from h' ffff to h'0000). ? the ovf flag is set to 1 in 8tcsr1 when the 8-bit counter (8tcnt1) overflows (from h'ff to h'00). ? channels 2 and 3: when bits cks2 to cks0 are set to (100) in 8tcr2, the timer functions as a single 16-bit timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits. ? setting when compare match occurs ? the cmf flag is set to 1 in 8tcr2 when a 16-bit compare match occurs. ? the cmf flag is set to 1 in 8tcr3 when a lower 8-bit compare match occurs. ? tmo 2 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr2 is in accordance with the 16-bit compare match conditions. ? tmio 3 pin output control by bits ois3, ois2, os1, and os0 in 8tcsr3 is in accordance with the lower 8-bit compare match conditions. ? setting when input capture occurs ? the cmfb flag is set to 1 in 8tcr2 and 8tcr3 when the ice bit is 1 in 8tcsr3 and input capture occurs. ? tmio 3 pin input capture input signal edge detection is selected by bits ois3 and ois2 in 8tcsr2. ? counter clear specification ? if counter clear on compare match has been selected by the cclr1 and cclr0 bits in 8tcr2, the 16-bit counter (both 8tcnt2 and 8tcnt3) is cleared. ? the settings of the cclr1 and cclr0 bits in 8tcr3 are ignored. the lower 8 bits cannot be cleared independently. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 375 of 764 rej09b0396-0500 ? ovf flag operation ? the ovf flag is set to 1 in 8tcsr2 when the 16-bit counter (8tcnt2 and 8tcnt3) overflows (from h' ffff to h'0000). ? the ovf flag is set to 1 in 8tcsr3 when the 8-bit counter (8tcnt3) overflows (from h'ff to h'00). compare match count mode ? channels 0 and 1: when bits cks2 to cks0 are set to (100) in 8tcr1, 8tcnt1 counts channel 0 compare match a events. channels 0 and 1 are controlled independently. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. ? channels 2 and 3: when bits cks2 to cks0 are set to (100) in 8tcr3, 8tcnt3 counts channel 2 compare match a events. channels 2 and 3 are controlled independently. cmf flag setting, interrupt generation, tmo pin output, counter clearing, and so on, is in accordance with the settings for each channel. caution: do not set 16-bit count mode and compare match count mode simultaneously within the same group, as the 8tcnt input clock will not be generated and the counters will not operate. 10.4.6 input capture setting the 8tcnt value can be transferred to tcorb on detection of an input edge on the input capture/output compare pin (tmio 1 or tmio 3 ). rising edge, falling edge , or both edge detection can be selected. in 16-bit count mode , 16-bit input capture can be used. setting input capture operation in 8-bit timer mode (normal operation) ? channel 1: ? set tcorb1 as an 8-bit input capture register with the ice bit in 8tcsr1. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 1 ) with bits ois3 and ois2 in 8tcsr1. ? select the input clock with bits cks2 to cks0 in 8tcr1, and start the 8tcnt count. ? channel 3: ? set tcorb3 as an 8-bit input capture register with the ice bit in 8tcsr3. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 3 ) with bits ois3 and ois2 in 8tcsr3. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 376 of 764 rej09b0396-0500 ? select the input clock with bits cks2 to cks0 in 8tcr3, and start the 8tcnt count. note: when tcorb1 in channel 1 is used for input capture, tcorb0 in channel 0 cannot be used as a compare match register. similarly, when tcorb3 in channel 3 is used for input capture, tcorb2 in channel 2 cannot be used as a compare match register. setting input capture operation in 16-bit count mode ? channels 0 and 1: ? in 16-bit count mode, tcorb0 and tcorb1 function as a 16-bit input capture register when the ice bit is set to 1 in 8tcsr1. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 1 ) with bits ois3 and ois2 in 8tcsr0. (in 16-bit count mode, the settings of bits ois3 and ois2 in 8tcsr1 are ignored.) ? select the input clock with bits cks2 to cks0 in 8tcr1, and start the 8tcnt count. ? channels 2 and 3: ? in 16-bit count mode, tcorb2 and tcorb3 function as a 16-bit input capture register when the ice bit is set to 1 in 8tcsr3. ? select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (tmio 3 ) with bits ois3 and ois2 in 8tcsr2. (in 16-bit count mode, the settings of bits ois3 and ois2 in 8tcsr3 are ignored.) ? select the input clock with bits cks2 to cks0 in 8tcr3, and start the 8tcnt count. 10.5 interrupt 10.5.1 interrupt source the 8-bit timer unit can generate three types of interrupt: compare match a and b (cmia and cmib) and overflow (ovi). table 10.5 shows the interrupt sources and their priority order. each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8tcr. a separate interrupt request signal is sent to the interrupt controller by each interrupt source. table 10.5 types of 8-bit timer int errupt sources and priority order interrupt source description priority cmia interrupt by cmfa high cmib interrupt by cmfb tovi interrupt by ovf low 10. 8-bit timers rev.5.00 sep. 12, 2007 page 377 of 764 rej09b0396-0500 for compare match interrupts cmia1/cmib1 and cmia3/cmib3 and the overflow interrupts (tovi0/tovi1 and tovi2/tovi3), one vector is shared by two interrupts. table 10.6 lists the interrupt sources. table 10.6 8-bit timer interrupt sources channel interrupt source description 0 cmia0 tcora0 compare match cmib0 tcorb0 compare match/input capture 1 cmia1/cmib1 tcora1 compare match, or tcorb1 compare match/input capture 0, 1 tovi0/tovi1 counter 0 or counter 1 overflow 2 cmia2 tcora2 compare match cmib2 tcorb2 compare match/input capture 3 cmia3/cmib3 tcora3 compare match, or tcorb3 compare match/input capture 2, 3 tovi2/tovi3 counter 2 or counter 3 overflow 10.5.2 a/d converter activation the a/d converter can only be activated by channel 0 compare match a. when the cmfa flag in 8tcsr0 is set to 1 and the adte bit is also set to 1, activation of the a/d converter will be requested on generation of ch annel 0 compare match a. if the trge bit in adcr is set to 1 at this time, the a/d converter will be activated. when adte bit in 8tcsr0 is set to 1, the a/d converter external trigger pin ( adtrg ) input is disabled. 10.6 8-bit timer application example figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired duty cycle. the settings for this example are as follows: ? clear the cclr1 bit to 0 and set the cclr0 bit to 1 in 8tcr so that 8tcnt is cleared by a tcora compare match. ? set bits ois3, ois2, os1, and os0 to (0110) in 8tcsr so that 1 is output on a tcora compare match and 0 is output on a tcorb compare match. the above settings enable a wave form with the cycle determined by tcora and the pulse width detected by tcorb to be output without software intervention. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 378 of 764 rej09b0396-0500 8tcnt h'ff counter clear tcora tcorb h'00 tmo figure 10.17 example of pulse output 10.7 usage notes note that the following kinds of contention can occur in 8-bit timer operation. 10.7.1 contention between 8tcnt write and clear if a timer counter clear signal occurs in the t 3 state of a 8tcnt write cycle, clearing of the counter takes priority and the write is not performed. figure 10.18 shows the timing in this case. address bus 8tcnt address internal write si g nal counter clear si g nal 8tcnt n h'00 t 1 t 3 t 2 8tcnt write cycle figure 10.18 contention be tween 8tcnt write and clear 10. 8-bit timers rev.5.00 sep. 12, 2007 page 379 of 764 rej09b0396-0500 10.7.2 contention between 8tcnt write and increment if an increment puls e occurs in the t 3 state of a 8tcnt write cycle, writing takes priority and 8tcnt is not incremented. figure 10.19 shows the timing in this case. address bus 8tcnt address internal write si g nal 8tcnt input clock 8tcnt nm t 1 t 3 t 2 8tcnt write cycle 8tcnt write data figure 10.19 contention betw een 8tcnt write and increment 10. 8-bit timers rev.5.00 sep. 12, 2007 page 380 of 764 rej09b0396-0500 10.7.3 contention between tc or write and compare match if a compare match occurs in the t 3 state of a tcor write cycle, writing takes priority and the compare match signal is inhibited. figure 10.20 shows the timing in this case. address bus tcor address internal write si g nal 8tcnt tcor nm t 1 t 3 t 2 tcor write cycle tcor write data n n+1 compare match si g nal inhibited figure 10.20 contention between tcor write and compare match 10. 8-bit timers rev.5.00 sep. 12, 2007 page 381 of 764 rej09b0396-0500 10.7.4 contention between tcor read and input capture if an input capture signal occurs in the t 3 state of a tcor read cycle, the value before input capture is read. figure 10.21 shows the timing in this case. address bus tcorb address internal read si g nal input capture si g nal tcorb nm t 1 t 3 t 2 tcorb read cycle internal data bus n figure 10.21 contention between tcor read and input capture 10. 8-bit timers rev.5.00 sep. 12, 2007 page 382 of 764 rej09b0396-0500 10.7.5 contention between counter cleari ng by input capture and counter increment if an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. the value before the counter is cleared is transferred to tcorb. figure 10.22 shows the timing in this case. counter clear si g nal 8tcnt internal clock 8tcnt n x h'00 t 1 t 3 t 2 input capture si g nal tcorb n figure 10.22 contention between counter clearing by input capture and counter increment 10. 8-bit timers rev.5.00 sep. 12, 2007 page 383 of 764 rej09b0396-0500 10.7.6 contention between tcor write and input capture if an input capture signal occurs in the t 3 state of a tcor write cycle, input capture takes priority and the write to tcor is not performed. figure 10.23 shows the timing in this case. address bus tcor address internal write si g nal input capture si g nal 8tcnt m t 1 t 3 t 2 tcor write cycle tcor m x figure 10.23 contention between tcor write and input capture 10. 8-bit timers rev.5.00 sep. 12, 2007 page 384 of 764 rej09b0396-0500 10.7.7 contention between 8tcnt byte wr ite and increment in 16-bit count mode (cascaded connection) if an increment puls e occurs in the t 2 or t 3 state of a 8tcnt byte write cycle in 16-bit count mode, writing takes priority and 8tcnt is not incremented. the byte data for which a write was not performed retains its previous value. figure 10.24 shows the timing when an increment pulse occurs in the t 2 state of a byte write to 8tcnth. address bus 8tcnth address internal write si g nal 8tcnt input clock 8tcnth n 8tcnt write data t 1 t 3 t 2 8tcnth byte write cycle 8tcntl x + 1 x figure 10.24 contention be tween 8tcnt byte write and increment in 16-bit count mode 10. 8-bit timers rev.5.00 sep. 12, 2007 page 385 of 764 rej09b0396-0500 10.7.8 contention between compare matches a and b if compare matches a and b occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for co mpare match a and compare match b, as shown in table 10.5. table 10.5 timer output priority order output setting priority toggle output high 1 output 0 output no change low 10.7.9 8tcnt operation at int ernal clock source switchover switching internal clock sources may cause 8tcnt to increment, depending on the switchover timing. table 10.6 shows the relation between th e time of the switchover (by writing to bits cks1 and cks0) and the operation of 8tcnt. the 8tcnt input clock is generated from the internal clock source by detecting the rising edge of the internal clock. if a switchover is made from a low clock source to a high clock source, as in case no. 3 in table 10.6, the switchover will be re garded as a falling edge, a 8tcnt clock pulse will be generated, and 8tcnt will be incremented. 8tcnt may also be incremented when switchi ng between internal and external clocks. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 386 of 764 rej09b0396-0500 table 10.6 internal clock switchover and 8tcnt operation no. cks1 and cks0 write timing 8tcnt operation 1 high high switchover * 1 old clock source new clock source 8tcnt clock 8tcnt cks bits rewritten n n + 1 2 high low switchover * 2 cks bits rewritten n n + 1 n + 2 old clock source new clock source 8tcnt clock 8tcnt 3 low high switchover * 3 n n + 1 n + 2 * 4 cks bits rewritten old clock source new clock source 8tcnt clock 8tcnt 10. 8-bit timers rev.5.00 sep. 12, 2007 page 387 of 764 rej09b0396-0500 no. cks1 and cks0 write timing 8tcnt operation 4 low low switchover * 4 n n + 1 n + 2 cks bits rewritten old clock source new clock source 8tcnt clock 8tcnt notes: 1. including switchovers from a high clock s ource to the halted state, and from the halted state to a high clock source. 2. including switchover from the halted state to a low clock source. 3. including switchover from a low clock source to the halted state. 4. the switchover is regarded as a rising edge, causing 8tcnt to increment. 10. 8-bit timers rev.5.00 sep. 12, 2007 page 388 of 764 rej09b0396-0500 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 389 of 764 rej09b0396-0500 section 11 programmable timing pattern controller (tpc) 11.1 overview the h8/3006 and h8/3007 have a built-in progra mmable timing pattern controller (tpc) that provides pulse outputs by using the 16-bit timer as a time base. the tpc pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 11.1.1 features tpc features are listed below. ? 16-bit output data maximum 16-bit data can be output. tpc output can be enabled on a bit-by-bit basis. ? four output groups output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. ? selectable output trigger signals output trigger signals can be selected for each group from the compare match signals of three 16-bit timer channels. ? non-overlap mode a non-overlap margin can be provided between pulse outputs. ? can operate together with the dma controller (dmac) the compare-match signals selected as trigge r signals can activate the dmac for sequential output of data without cpu intervention. 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 390 of 764 rej09b0396-0500 11.1.2 block diagram figure 11.1 shows a block diagram of the tpc. paddr ndera tpmr pbddr nderb tpcr internal data bus tp tp tp tp tp tp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 control lo g ic 16-bit timer compare match si g nals pulse output pins, g roup 3 pbdr pa d r le g end: tpmr: tpcr: nderb: ndera: pbddr: paddr: ndrb: ndra: pbdr: pa d r : pulse output pins, g roup 2 pulse output pins, g roup 1 pulse output pins, g roup 0 tpc output mode re g ister tpc output control re g ister next data enable re g ister b next data enable re g ister a port b data direction re g ister port a data direction re g ister next data re g ister b next data re g ister a port b data re g ister port a data re g ister ndrb ndra tp tp tp tp tp tp tp tp tp tp figure 11.1 tpc block diagram 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 391 of 764 rej09b0396-0500 11.1.3 pin configuration table 11.1 summarizes the tpc output pins. table 11.1 tpc pins name symbol i/o function tpc output 0 tp 0 output group 0 pulse output tpc output 1 tp 1 output tpc output 2 tp 2 output tpc output 3 tp 3 output tpc output 4 tp 4 output group 1 pulse output tpc output 5 tp 5 output tpc output 6 tp 6 output tpc output 7 tp 7 output tpc output 8 tp 8 output group 2 pulse output tpc output 9 tp 9 output tpc output 10 tp 10 output tpc output 11 tp 11 output tpc output 12 tp 12 output group 3 pulse output tpc output 13 tp 13 output tpc output 14 tp 14 output tpc output 15 tp 15 output 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 392 of 764 rej09b0396-0500 11.1.4 register configuration table 11.2 summarizes the tpc registers. table 11.2 tpc registers address * 1 name abbreviation r/w function h'ee009 port a data direction register paddr w h'00 h'fffd9 port a data register padr r/(w) * 2 h'00 h'ee00a port b data direction register pbddr w h'00 h'fffda port b data register pbdr r/(w) * 2 h'00 h'fffa0 tpc output mode register tpmr r/w h'f0 h'fffa1 tpc output control register tpcr r/w h'ff h'fffa2 next data enable register b nderb r/w h'00 h'fffa3 next data enable register a ndera r/w h'00 h'fffa5/ h'fffa7 * 3 next data register a ndra r/w h'00 h'fffa4/ h'fffa6 * 3 next data register b ndrb r/w h'00 notes: 1. lower 20 bits of the address in advanced mode. 2. bits used for tpc output cannot be written. 3. the ndra address is h'fffa5 when the same output trigger is selected for tpc output groups 0 and 1 by settings in tpcr. when the output triggers are different, the ndra address is h'fffa7 for group 0 and h'fffa5 for group 1. similarly, the address of ndrb is h'fffa4 when the same output trigger is selected for tpc output groups 2 and 3 by settings in tpcr. when the output triggers are different, the ndrb address is h'fffa6 for group 2 and h'fffa4 for group 3. 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 393 of 764 rej09b0396-0500 11.2 register descriptions 11.2.1 port a data di rection register (paddr) paddr is an 8-bit write-only register that se lects input or output for each pin in port a. bit initial value read/write 7 pa ddr 0 w port a data dire c tion 7 to 0 these bits select input or output for port a pins 7 6 pa ddr 0 w 6 5 pa ddr 0 w 5 4 pa ddr 0 w 4 3 pa ddr 0 w 3 2 pa ddr 0 w 2 1 pa ddr 0 w 1 0 pa ddr 0 w 0 port a is multiplexed with pins tp 7 to tp 0 . bits corresponding to pins used for tpc output must be set to 1. for further information about paddr, see section 8.7, port a. 11.2.2 port a data register (padr) padr is an 8-bit readable/writable register that stores tpc output data for groups 0 and 1, when these tpc output groups are used. bit initial value read/write 0 pa 0 r/(w) 0 1 pa 0 r/(w) 1 2 pa 0 r/(w) 2 3 pa 0 r/(w) 3 4 pa 0 r/(w) 4 5 pa 0 r/(w) 5 6 pa 0 r/(w) 6 7 pa 0 r/(w) 7 port a data 7 to 0 these bits store output data for tpc output g roups 0 and 1 ******** note: bits selected for tpc output by ndera settin g s become read-only bits. * for further information about padr, see section 8.7, port a. 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 394 of 764 rej09b0396-0500 11.2.3 port b data di rection register (pbddr) pbddr is an 8-bit write-only register that se lects input or output for each pin in port b. bit initial value read/write 7 pb ddr 0 w port b data dire c tion 7 to 0 these bits select input or output for port b pins 7 6 pb ddr 0 w 6 5 pb ddr 0 w 5 4 pb ddr 0 w 4 3 pb ddr 0 w 3 2 pb ddr 0 w 2 1 pb ddr 0 w 1 0 pb ddr 0 w 0 port b is multiplexed with pins tp 15 to tp 8 . bits corresponding to pins used for tpc output must be set to 1. for further information about pbddr, see section 8.8, port b. 11.2.4 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores tpc output data for groups 2 and 3, when these tpc output groups are used. bit initial value read/write 0 pb 0 r/(w) 0 1 pb 0 r/(w) 1 2 pb 0 r/(w) 2 3 pb 0 r/(w) 3 4 pb 0 r/(w) 4 5 pb 0 r/(w) 5 6 pb 0 r/(w) 6 7 pb 0 r/(w) 7 port b data 7 to 0 these bits store output data for tpc output groups 2 and 3 ******** note: bits selected for tpc output by nderb settings become read-only bits. * for further information about pbdr, see section 8.8, port b. 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 395 of 764 rej09b0396-0500 11.2.5 next data register a (ndra) ndra is an 8-bit readable/writable register that stores the next output data for tpc output groups 1 and 0 (pins tp 7 to tp 0 ). during tpc output, when an 16-bit timer compare match event specified in tpcr occurs, ndra contents are transferred to the corresponding bits in padr. the address of ndra differs depending on whether tpc output groups 0 and 1 have the same output trigger or different output triggers. ndra is initialized to h'00 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. same trigger for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by the same compare match event, the ndra address is h'fffa5. the upper 4 bits belong to group 1 and the lower 4 bits to group 0. address h'fffa7 consists entirely of reserved bits that cannot be modified and always read 1. address h'fffa5 bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w next data 3 to 0 these bits store the next output data for tpc output g roup 0 next data 7 to 4 these bits store the next output data for tpc output g roup 1 address h'fffa7 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 396 of 764 rej09b0396-0500 different triggers for tpc output groups 0 and 1: if tpc output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of ndra (group 1) is h'fffa5 and the address of the lower 4 bits (group 0) is h'fffa7. bits 3 to 0 of address h'fffa5 and bits 7 to 4 of address h'fffa7 are reserved bits th at cannot be modified and always read 1. address h'fffa5 bit initial value read/write 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? reserved bits next data 7 to 4 these bits store the next output data for tpc output g roup 1 address h'fffa7 bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 0 r/w next data 3 to 0 these bits store the next output data for tpc output g roup 0 reserved bits 11.2.6 next data register b (ndrb) ndrb is an 8-bit readable/writable register that stores the next output data for tpc output groups 3 and 2 (pins tp 15 to tp 8 ). during tpc output, when an 16-bit timer compare match event specified in tpcr occurs, ndrb c ontents are transferred to the co rresponding bits in pbdr. the address of ndrb differs depending on whether tpc output groups 2 and 3 have the same output trigger or different output triggers. ndrb is initialized to h'00 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 397 of 764 rej09b0396-0500 same trigger for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by the same compare match event, the ndrb address is h'fffa4. the upper 4 bits belong to group 3 and the lower 4 bits to group 2. address h'fffa6 consists entirely of reserved bits that cannot be modified and always read 1. address h'fffa4 bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w next data 11 to 8 these bits store the next output data for tpc output g roup 2 next data 15 to 12 these bits store the next output data for tpc output g roup 3 address h'fffa6 bit initial value read/write 0 ? 1 ? 1 ? 1 ? 2 ? 1 ? 3 ? 1 ? 4 ? 1 ? 5 ? 1 ? 6 ? 1 ? 7 ? 1 ? reserved bits different triggers for tpc output groups 2 and 3: if tpc output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of ndrb (group 3) is h'fffa4 and the address of the lower 4 bits (group 2) is h'fffa6. bits 3 to 0 of address h'fffa4 and bits 7 to 4 of address h'fffa6 are reserved bits th at cannot be modified and always read 1. address h'fffa4 bit initial value read/write 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? reserved bits next data 15 to 12 these bits store the next output data for tpc output g roup 3 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 398 of 764 rej09b0396-0500 address h'fffa6 bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 0 r/w next data 11 to 8 these bits store the next output data for tpc output g roup 2 reserved bits 11.2.7 next data enable register a (ndera) ndera is an 8-bit readable/writable register that enables or disables tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. bit initial value read/write 0 nder0 0 r/w 1 nder1 0 r/w 2 nder2 0 r/w 3 nder3 0 r/w 4 nder4 0 r/w 5 nder5 0 r/w 6 nder6 0 r/w 7 nder7 0 r/w next data enable 7 to 0 these bits enable or disable tpc output g roups 1 and 0 if a bit is enabled for tpc output by ndera, then when the 16-bit timer compare match event selected in the tpc output cont rol register (tpcr) occurs, th e ndra value is automatically transferred to the corresponding padr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndra to padr and the output value does not change. ndera is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0 ? next data enable 7 to 0 (nder7 to nder0): these bits enable or disable tpc output groups 1 and 0 (tp 7 to tp 0 ) on a bit-by-bit basis. bits 7 to 0 nder7 to nder0 description 0 tpc outputs tp 7 to tp 0 are disabled (ndr7 to ndr0 are not transferred to pa 7 to pa 0 ) (initial value) 1 tpc outputs tp 7 to tp 0 are enabled (ndr7 to ndr0 are transferred to pa 7 to pa 0 ) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 399 of 764 rej09b0396-0500 11.2.8 next data enable register b (nderb) nderb is an 8-bit readable/writable register that enables or disables tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. bit initial value read/write 0 nder8 0 r/w 1 nder9 0 r/w 2 nder10 0 r/w 3 nder11 0 r/w 4 nder12 0 r/w 5 nder13 0 r/w 6 nder14 0 r/w 7 nder15 0 r/w next data enable 15 to 8 these bits enable or disable tpc output g roups 3 and 2 if a bit is enabled for tpc output by nderb, then when the 16-bit timer compare match event selected in the tpc output cont rol register (tpcr) occurs, th e ndrb value is automatically transferred to the corresponding pbdr bit, updating the output value. if tpc output is disabled, the bit value is not transferred from ndrb to pbdr and the output value does not change. nderb is initialized to h'00 by a reset and in ha rdware standby mode. it is not initialized in software standby mode. bits 7 to 0 ? next data enable 15 to 8 (nder15 to nder8): these bits enable or disable tpc output groups 3 and 2 (tp 15 to tp 8 ) on a bit-by-bit basis. bits 7 to 0 nder15 to nder 8 description 0 tpc outputs tp 15 to tp 8 are disabled (ndr15 to ndr8 are not transferred to pb 7 to pb 0 ) (initial value) 1 tpc outputs tp 15 to tp 8 are enabled (ndr15 to ndr8 are transferred to pb 7 to pb 0 ) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 400 of 764 rej09b0396-0500 11.2.9 tpc output control register (tpcr) tpcr is an 8-bit readable/writable register that selects output trigger signals for tpc outputs on a group-by-group basis. bit initial value read/write 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 0 g0cms0 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w group 3 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 3 (tp to tp ) group 2 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 2 (tp to tp ) group 1 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 1 (tp to tp ) group 0 compare match select 1 and 0 these bits select the compare match event that triggers tpc output group 0 (tp to tp ) 15 12 11 8 74 30 tpcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 and 6 ? group 3 compare match select 1 and 0 (g3cms1, g3cms0): these bits select the compare match event that triggers tpc output group 3 (tp 15 to tp 12 ). bit 7 g3cms1 bit 6 g3cms0 description 0 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 (initial value) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 401 of 764 rej09b0396-0500 bits 5 and 4 ? group 2 compare match select 1 and 0 (g2cms1, g2cms0): these bits select the compare match event that triggers tpc output group 2 (tp 11 to tp 8 ). bit 5 g2cms1 bit 4 g2cms0 description 0 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 (initial value) bits 3 and 2 ? group 1 compare match select 1 and 0 (g1cms1, g1cms0): these bits select the compare match event that triggers tpc output group 1 (tp 7 to tp 4 ). bit 3 g1cms1 bit 2 g1cms0 description 0 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 (initial value) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 402 of 764 rej09b0396-0500 bits 1 and 0 ? group 0 compare match select 1 and 0 (g0cms1, g0cms0): these bits select the compare match event that triggers tpc output group 0 (tp 3 to tp 0 ). bit 1 g0cms1 bit 0 g0cms0 description 0 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 0 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 1 1 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 (initial value) 11.2.10 tpc output mode register (tpmr) tpmr is an 8-bit readable/writable register that selects normal or non-overlapping tpc output for each group. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 g3nov 0 r/w 0 g0nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w group 3 non-overlap selects non-overlapping tpc output for group 3 (tp to tp ) reserved bits group 2 non-overlap selects non-overlapping tpc output for group 2 (tp to tp ) group 1 non-overlap selects non-overlapping tpc output for group 1 (tp to tp ) group 0 non-overlap selects non-overlapping tpc output for group 0 (tp to tp ) 15 12 11 8 74 30 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 403 of 764 rej09b0396-0500 the output trigger period of a non-overlapping tpc output waveform is set in general register b (grb) in the 16-bit timer channel selected for output triggering. the non-overlap margin is set in general register a (gra). the output values change at compare match a and b. for details see section 11.3.4, non-overlapping tpc output. tpmr is initialized to h'f0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 4 ? reserved: these bits cannot be modified and are always read as 1. bit 3 ? group 3 non-overlap (g3nov): selects normal or non-overlapping tpc output for group 3 (tp 15 to tp 12 ). bit 3 g3nov description 0 normal tpc output in group 3 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 3 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 2 ? group 2 non-overlap (g2nov): selects normal or non-overlapping tpc output for group 2 (tp 11 to tp 8 ). bit 2 g2nov description 0 normal tpc output in group 2 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 2 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) bit 1 ? group 1 non-overlap (g1nov): selects normal or non-overlapping tpc output for group 1 (tp 7 to tp 4 ). bit 1 g1nov description 0 normal tpc output in group 1 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 1 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 404 of 764 rej09b0396-0500 bit 0 ? group 0 non-overlap (g0nov): selects normal or non-overlapping tpc output for group 0 (tp 3 to tp 0 ). bit 0 g0nov description 0 normal tpc output in group 0 (output values change at compare match a in the selected 16-bit timer channel) (initial value) 1 non-overlapping tpc output in group 0 (independent 1 and 0 output at compare match a and b in the selected 16-bit timer channel) 11.3 operation 11.3.1 overview when corresponding bits in paddr or pbddr and ndera or nderb are set to 1, tpc output is enabled. the tpc output initially consists of the corresponding padr or pbdr contents. when a compare-match event se lected in tpcr occurs, the corresponding ndra or ndrb bit contents are transferred to padr or pbdr to update the output values. figure 11.2 illustrates the tpc output operation. table 11.3 summarizes the tpc operating conditions. ddr nder qq tpc output pin dr ndr c qd qd internal data bus output tri gg er si g nal figure 11.2 tpc output operation 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 405 of 764 rej09b0396-0500 table 11.3 tpc operating conditions nder ddr pin function 0 0 generic input port 1 generic output port 1 0 generic input port (but the dr bit is a read-only bit, and when compare match occurs, the ndr bit value is transferred to the dr bit) 1 tpc pulse output sequential output of up to 16-bit patterns is possible by writing new output data to ndra and ndrb before the next compare match. for information on non-overlapping operation, see section 11.3.4, non-overlapping tpc output. 11.3.2 output timing if tpc output is enabled, ndra/ndrb contents are transferred to padr/pbdr and output when the selected compare matc h event occurs. figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. 16tcnt gra compare match a si g nal ndrb pbdr tp to tp 815 n n n m m n + 1 n n figure 11.3 timing of transfer of next data register contents and output (example) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 406 of 764 rej09b0396-0500 11.3.3 normal tpc output sample setup procedure for normal tpc output: figure 11.4 shows a sample procedure for setting up normal tpc output. normal tpc output set next tpc output data compare match? no ye s set next tpc output data 16-bit timer setup 16-bit timer setup port and tpc setup 10 11 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. set tior to make gra an output compare re g ister (with output inhibited). set the tpc output tri gg er period. select the counter clock source with bits tpsc2 to tpsc0 in 16tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tisra. the dmac can also be set up to transfer data to the next data re g ister. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. select the 16-bit timer compare match event to be used as the tpc output tri gg er in tpcr. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, set the next output values in the ndr bits. 1 2 3 4 5 6 7 8 select gr functions set gra value select countin g operation select interrupt request start counter set initial output data select port output enable tpc output select tpc output tri gg er figure 11.4 setup procedure fo r normal tpc output (example) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 407 of 764 rej09b0396-0500 example of normal tpc output (example of five-phase pulse output): figure 11.5 shows an example in which the tpc is used for cyclic five-phase pulse output. gra h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 ? ? ? ? time 80 tcnt tcnt value c0 40 60 20 30 10 18 08 88 80 c0 compare match the 16-bit timer channel to be used as the output tri gg er channel is set up so that gra is an output compare re g ister and the counter will be cleared by compare match a. the tri gg er period is set in gra. the imiea bit is set to 1 in tisra to enable the compare match a interrupt. h'f8 is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set in tpcr to select compare match in the 16-bit timer channel set up in step 1 as the output tri gg er. output data h'80 is written in ndrb. the timer counter in this 16-bit timer channel is started. when compare match a occurs, the ndrb contents are transferred to pbdr and output. the compare match/input capture a (imfa) interrupt service routine writes the next output data (h'c0) in ndrb. five-phase overlappin g pulse output (one or two phases active at a time) can be obtained by writin g h'40, h'60, h'20, h'30, h'10, h'18, h'08, h'88 at successive imfa interrupts. if the dmac is set for activation by this interrupt, pulse output can be obtained without loadin g the cpu. 00 80 c0 40 60 20 30 10 18 08 88 80 c0 40 figure 11.5 normal tpc output example (five-phase pulse output) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 408 of 764 rej09b0396-0500 11.3.4 non-overlapping tpc output sample setup procedure for non-overlapping tpc output: figure 11.6 shows a sample procedure for setting up non-overlapping tpc output. non-overlappin g tpc output set next tpc output data compare match a? no ye s set next tpc output data start counter 16-bit timer setup 16-bit timer setup port and tpc setup set initial output data set up tpc output enable tpc transfer select tpc transfer tri gg er select non-overlappin g g roups 1 2 3 4 12 10 11 5 6 7 8 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. set tior to make gra and grb output compare re g isters (with output inhibited). set the tpc output tri gg er period in grb and the non-overlap mar g in in gra. select the counter clock source with bits tpsc2 to tpsc0 in 16tcr. select the counter clear source with bits cclr1 and cclr0. enable the imfa interrupt in tisra. the dmac can also be set up to transfer data to the next data re g ister. set the initial output values in the dr bits of the input/output port pins to be used for tpc output. set the ddr bits of the input/output port pins to be used for tpc output to 1. set the nder bits of the pins to be used for tpc output to 1. in tpcr, select the 16-bit timer compare match event to be used as the tpc output tri gg er. in tpmr, select the g roups that will operate in non-overlap mode. set the next tpc output values in the ndr bits. set the str bit to 1 in tstr to start the timer counter. at each imfa interrupt, write the next output value in the ndr bits. select gr functions set gr values select countin g operation select interrupt requests figure 11.6 setup procedure for non-overlapping tpc output (example) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 409 of 764 rej09b0396-0500 example of non-overlapping tpc output (example of four-phase complementary non- overlapping output): figure 11.7 shows an example of the use of tpc output for four-phase complementary non-overlapping pulse output. grb h'0000 ndrb pbdr tp 15 tp 14 tp 13 tp 12 tp 11 tp 10 tp 9 tp 8 time 95 00 65 95 59 56 95 65 05 65 41 59 50 56 14 95 05 65 16tcnt period is set in grb. the non-overlap mar g in is set in gra. the imiea bit is set to 1 in tisra to enable imfa interrupts. h'ff is written in pbddr and nderb, and bits g3cms1, g3cms0, g2cms1, and g2cms0 are set in tpcr to select compare match in the 16-bit timer channel set up in step 1 as the output tri gg er. bits g3nov and g2nov are set to 1 in tpmr to select non-overlappin g output. output data h'95 is written in ndrb. 16tcnt value non-overlap mar g in the 16-bit timer channel to be used as the output tri gg er channel is set up so that gra and grb are output compare re g isters and the counter will be cleared by compare match b. the tpc output tri gg er ? ? ? ? the timer counter in this 16-bit timer channel is started. when compare match b occurs, outputs chan g e from 1 to 0. when compare match a occurs, outputs chan g e from 0 to 1 (the chan g e from 0 to 1 is delayed by the value of gra). the imfa interrupt service routine writes the next output data (h'65) in ndrb. four-phase complementary non-overlappin g pulse output can be obtained by writin g h'59, h'56, h'95? at successive imfa interrupts. if the dmac is set for activation by this interrupt, pulse output can be obtained without loadin g the cpu. gra figure 11.7 non-overlapping tpc output example (four-phase complementary non-overlapping pulse output) 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 410 of 764 rej09b0396-0500 11.3.5 tpc output triggering by input capture tpc output can be triggered by 16-bit timer input capture as well as by compare match. if gra functions as an input capture register in the 16 -bit timer channel selected in tpcr, tpc output will be triggered by the input capture si gnal. figure 11.8 shows the timing. tioc pin input capture si g nal ndr dr n n m figure 11.8 tpc output triggering by input capture (example) 11.4 usage notes 11.4.1 operation of tpc output pins tp 0 to tp 15 are multiplexed with 16-bit timer, dmac, address bus, and other pin functions. when 16-bit timer, dmac, or address output is enabled, the corresponding pins cannot be used for tpc output. the data transfer from ndr bits to dr bits takes place, however, regardless of the usage of the pin. pin functions should be changed only under conditi ons in which the output trigger event will not occur. 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 411 of 764 rej09b0396-0500 11.4.2 note on non-overlapping output during non-overlapping operation, the transfer of ndr bit values to dr bits takes place as follows. 1. ndr bits are always transferred to dr bits at compare match a. 2. at compare match b, ndr bits are transferred onl y if their value is 0. bits are not transferred if their value is 1. figure 11.9 illustrates the non-overlapping tpc output operation. ddr nder qq tpc output pin dr ndr c qd qd compare match a compare match b figure 11.9 non-overlapping tpc output therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlap margin). this can be accomplished by having the imfa inte rrupt service routine wr ite the next data in ndr, or by having the imfa interrupt activate the dmac. the next data must be written before the next compare match b occurs. figure 11.10 shows the timing relationships. 11. programmable timing pattern controller (tpc) rev.5.00 sep. 12, 2007 page 412 of 764 rej09b0396-0500 compare match a compare match b ndr write ndr ndr write dr 0/1 output 0/1 output 0 output 0 output do not write to ndr in this interval do not write to ndr in this interval write to ndr in this interval write to ndr in this interval figure 11.10 non-overlapping operation and ndr write timing 12. watchdog timer rev.5.00 sep. 12, 2007 page 413 of 764 rej09b0396-0500 section 12 watchdog timer 12.1 overview the h8/3006 and h8/3007 have an on-chip watchdog timer (wdt). the wdt has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. as a watchdog timer, it generates a reset signal for the h8/3006 and h8/3007 chip if a system crash allows the timer counter (tcnt) to overflow before being rewritten. in interval timer operation, an interval timer interrupt is requested at each tcnt overflow. 12.1.1 features wdt features are listed below. ? selection of eight counter clock sources /2, /32, /64, /128, /256, /512, /2048, or /4096 ? interval timer option ? timer counter overflow generates a reset signal or interrupt. the reset signal is generated in watchdog timer operation. an interval timer interrupt is generated in interval timer operation. ? watchdog timer reset signal resets the entire h8/3006 and h8/3007 internally, and can also be output externally. the reset signal generated by timer counter overflow during watchdog timer operation resets the entire h8/3006 and h8/3007 internally. an external reset signal can be output from the reso pin to reset other system devices simultaneously. 12. watchdog timer rev.5.00 sep. 12, 2007 page 414 of 764 rej09b0396-0500 12.1.2 block diagram figure 12.1 shows a block diagram of the wdt. /2 /32 /64 /128 /256 /512 /2048 /4096 tcnt tcsr rstcsr reset control interrupt signal reset (internal, external) (interval timer) interrupt control overflow clock clock selector read/ write control internal data bus internal clock sources legend: tcnt: tcsr: rstcsr: timer counter timer control/status register reset control/status register figure 12.1 wdt block diagram 12.1.3 pin configuration table 12.1 describes the wdt output pin. table 12.1 wdt pin name abbreviation i/o function reset output reso output * external output of the watchdog timer reset signal note: * open-drain output. 12. watchdog timer rev.5.00 sep. 12, 2007 page 415 of 764 rej09b0396-0500 12.1.4 register configuration table 12.2 summarizes the wdt registers. table 12.2 wdt registers address * 1 write * 2 read name abbreviation r/w initial value h'fff8c h'fff8c timer control/status register tcsr r/(w) * 3 h'18 h'fff8d timer counter tcnt r/w h'00 h'fff8e h'fff8f reset control/status register rstcsr r/(w) * 3 h'3f notes: 1. lower 20 bits of the address in advanced mode. 2. write word data starting at this address. 3. only 0 can be written in bit 7, to clear the flag. 12.2 register descriptions 12.2.1 timer counter (tcnt) tcnt is an 8-bit readab le and writable up-counter. bit initial value read/write note: tcnt is write-protected by a password. for details see section 12.2.4, notes on re g ister access. 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w when the tme bit is set to 1 in tcsr, tcnt st arts counting pulses generated from an internal clock source selected by bits ck s2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), the ovf bit is set to 1 in tcsr. tc nt is initialized to h'00 by a reset and when the tme bit is cleared to 0. 12. watchdog timer rev.5.00 sep. 12, 2007 page 416 of 764 rej09b0396-0500 12.2.2 timer control/sta tus register (tcsr) tcsr is an 8-bit readable and writable register. its functions include selecting the timer mode and clock source. bit initial value read/write notes: tcsr is write-protected by a password. for details see section 12.2.4, notes on register access. * only 0 can be written, to clear the flag. 7 ovf 0 r/(w) 6 wt/ it 0 r/w 5 tme 0 r/w 4 ? 1 ? 3 ? 1 ? 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w overflow flag status flag indicating overflow clock select these bits select the tcnt clock source timer mode select selects the mode timer enable selects whether tcnt runs or halts reserved bits * bits 7 to 5 are initialized to 0 by a reset and in standby mode. bits 2 to 0 are initialized to 0 by a reset. in software standby mode bits 2 to 0 are not initialized, but retain their previous values. bit 7 ? overflow flag (ovf): this status flag indicates that the timer counter has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing condition] (initial value) cleared by reading ovf when ovf = 1, then writing 0 in ovf 1 [setting condition] set when tcnt changes from h'ff to h'00 12. watchdog timer rev.5.00 sep. 12, 2007 page 417 of 764 rej09b0396-0500 bit 6 ? timer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request when tcnt overflows. if used as a watchdog timer, the wdt generates a reset signal when tcnt overflows. bit 6 wt/ it description 0 interval timer: requests interval timer interrupts (initial value) 1 watchdog timer: generates a reset signal bit 5 ? timer enable (tme): selects whether tcnt runs or is halted. when wt/ it = 1, clear the software standby bit (ssby) to 0 in sysc r before setting tme. when setting ssby to 1, tme should be cleared to 0. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt is counting bits 4 and 3 ? reserved: these bits cannot be modified and are always read as 1. bits 2 to 0 ? clock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources, obtained by prescaling the system clock ( ), for input to tcnt. bit 2 cks2 bit 1 cks1 bit 0 cks0 description 0 0 0 /2 (initial value) 1 /32 1 0 /64 1 /128 1 0 0 /256 1 /512 1 0 /2048 1 /4096 12. watchdog timer rev.5.00 sep. 12, 2007 page 418 of 764 rej09b0396-0500 12.2.3 reset control/status register (rstcsr) rstcsr is an 8-bit readable and writable register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. bit initial value read/write notes: rstcsr is write-protected by a password. for details see section 12.2.4, notes on register access. * only 0 can be written in bit 7, to clear the flag. 7 wrst 0 r/(w) 6 rstoe 0 r/w 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? * watchdog timer reset indicates that a reset signal has been generated reserved bits reset output enable enables or disables external output of the reset signal bits 7 and 6 are initialized by input of a reset signal at the res pin. they are not initialized by reset signals generated by watchdog timer overflow. bit 7 ? watchdog timer reset (wrst): during watchdog timer operation, this bit indicates that tcnt has overflowed and generated a reset signal. this reset signal resets the entire h8/3006 and h8/3007 chip internally. if bit rstoe is set to 1, this reset signal is also output (low) at the reso pin to initialize external system devices. bit 7 wrst description 0 [clearing condition] reset signal at res pin. read wrst when wrst =1, then write 0 in wrst. (initial value) 1 [setting condition] set when tcnt overflow generates a reset signal during watchdog timer operation 12. watchdog timer rev.5.00 sep. 12, 2007 page 419 of 764 rej09b0396-0500 bit 6 ? reset output enable (rstoe): enables or disables external output at the reso pin of the reset signal generated if tcnt overflows during watchdog timer operation. bit 6 rstoe description 0 reset signal is not output externally (initial value) 1 reset signal is output externally bits 5 to 0 ? reserved: these bits cannot be modified and are always read as 1. 12.2.4 notes on register access the watchdog timer's tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write. the procedures for writing and reading these registers are given below. writing to tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte instructions. figure 12.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must contain h'5a (password for tcnt) or h'a5 (password for tcsr). this transf ers the write data from the lower byte to tcnt or tcsr. 15 8 7 0 h'5a write data address h'fff8c * 15 8 7 0 h'a5 write data address h'fff8c * tcnt write tcsr write note: lower 20 bits of the address in advanced mode. * figure 12.2 format of data written to tcnt and tcsr writing to rstcsr: rstcsr must be written by a word transfer instruction. it cannot be written by byte transfer instructions. figure 12.3 shows the format of data written to rstcsr. to write 0 in the wrst bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. the data (h'00) in the lower byte is written to rstcsr, clearing the wrst bit to 0. to write to the rstoe bit, the upper byte must contain h'5a and the lower byte must contain the write data. writing this word transfers a write data value into the rstoe bit. 12. watchdog timer rev.5.00 sep. 12, 2007 page 420 of 764 rej09b0396-0500 15 8 7 0 h'a5 h'00 address h'fff8e * 15 8 7 0 h'5a write data address h'fff8e * writin g 0 in wrst bit writin g to rstoe bit note: lower 20 bits of the address in advanced mode. * figure 12.3 format of data written to rstcsr reading tcnt, tcsr, and rstcsr: for reads of tcnt, tcsr, and rstcsr, address h'fff8c is assigned to tcsr, address h'fff8d to tcnt, and address h'fff8f to rstcsr. these registers are therefore read like other registers. byte transfer instructions can be used for reading. table 12.3 lists the read addresses of tcnt, tcsr, and rstcsr. table 12.3 read addresses of tcnt, tcsr, and rstcsr address * register h'fff8c tcsr h'fff8d tcnt h'fff8f rstcsr note: * lower 20 bits of the address in advanced mode. 12.3 operation operations when the wdt is used as a watchdog timer and as an interval timer are described below. 12.3.1 watchdog timer operation figure 12.4 illustrates watchdog timer operation. to use the wdt as a watchdog timer, set the wt/ it and tme bits to 1 in tcsr. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. if tcnt fails to be rewritten and overflows due to a system crash etc., the h8/3006 and h8/3007 are internally reset for a duration of 518 states. the watchdog reset signal can be externally output from the reso pin to reset external system devices. the reset signal is output externally for 132 states. external output can be enabled or disabled by the rstoe bit in rstcsr. 12. watchdog timer rev.5.00 sep. 12, 2007 page 421 of 764 rej09b0396-0500 a watchdog reset has the same vector as a reset generated by input at the res pin. software can distinguish a res reset from a watchdog reset by checking the wrst bit in rstcsr. if a res reset and a watchdog reset occur simultaneously, the res reset takes priority. h'ff h'00 reso wdt overflow start h'00 written in tcnt reset tme set to 1 h'00 written in tcnt internal reset si g nal 518 states 132 states tcnt count value ovf = 1 figure 12.4 operation in watchdog timer mode 12. watchdog timer rev.5.00 sep. 12, 2007 page 422 of 764 rej09b0396-0500 12.3.2 interval timer operation figure 12.5 illustrates interval timer operation. to use the wdt as an interval timer, clear bit wt/ it to 0 and set bit tme to 1 in tcsr. an interv al timer interrupt request is generated at each tcnt overflow. this function can be used to generate interval timer interrupts at regular intervals. tcnt count value time t interval timer interrupt interval timer interrupt interval timer interrupt interval timer interrupt wt/ = 0 tme = 1 it h'ff h'00 figure 12.5 interval timer operation 12.3.3 timing of setting of overflow flag (ovf) figure 12.6 shows the timing of setting of the ovf flag. the ovf flag is set to 1 when tcnt overflows. at the same time, a reset signal is gene rated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. tcnt overflow si g nal ovf h'ff h'00 figure 12.6 timing of setting of ovf 12. watchdog timer rev.5.00 sep. 12, 2007 page 423 of 764 rej09b0396-0500 12.3.4 timing of setting of watchdog timer reset bit (wrst) the wrst bit in rstcsr is valid when bits wt/ it and tme are both set to 1 in tcsr. figure 12.7 shows the timing of setting of wrst and the internal reset timing. the wrst bit is set to 1 when tcnt overflows and ovf is set to 1. at the same time an internal reset signal is generated for the entire h8/3006 and h8/3007 chip. this internal reset signal clears ovf to 0, but the wrst bit remains set to 1. the reset routine must therefore clear the wrst bit. tcnt overflow si g nal ovf wrst h'ff h'00 wdt internal reset figure 12.7 timing of setting of wrst bit and internal reset 12.4 interrupts during interval timer operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested when ever the ovf bit is set to 1 in tcsr. 12. watchdog timer rev.5.00 sep. 12, 2007 page 424 of 764 rej09b0396-0500 12.5 usage notes contention between tcnt write and increment: if a timer counter clock pulse is generated during the t 3 state of a write cycle to tcnt, the write takes priority and the timer count is not incremented. see figure 12.8. tcnt tcnt nm counter write data t 3 t 2 t 1 cpu: tcnt write cycle internal write si g nal tcnt input clock figure 12.8 contention betw een tcnt write and count up changing cks2 to cks0 bit: halt tcnt by clearing the tme bit to 0 in tcsr before changing the values of bits cks2 to cks0. 13. serial communication interface rev.5.00 sep. 12, 2007 page 425 of 764 rej09b0396-0500 section 13 serial communication interface 13.1 overview the h8/3006 and h8/3007 have a serial communi cation interface (sci) with three independent channels. all three channels have identical functions. the sci can communicate in both asynchronous and synchronous mode. it also has a multiprocessor communication function for serial communication among two or more processors. when the sci is not used, it can be halted to conserve power. each sci channel can be halted independently. for details, see section 19.6, module standby function. the sci also has a smart card interface function co nforming to the iso/iec 7816-3 (identification card) standard. this function supports serial communication with a smart card. switching between the normal serial comm unication interface and the smart card interface is carried out by means of a register setting. 13.1.1 features sci features are listed below. ? selection of synchronous or asynchronous mode for serial communication asynchronous mode serial data communication is synchronized one channel at a time. the sci can communicate with a universal asynchronous receiver/tr ansmitter (uart), asynchronous communication interface adapter (acia), or othe r chip that employs standard asynchronous communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve sel ectable serial data transfer formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? multiprocessor bit: 1 or 0 ? receive error detection: parity , overrun, and framing errors ? break detection: by reading the rxd level directly when a framing error occurs 13. serial communication interface rev.5.00 sep. 12, 2007 page 426 of 764 rej09b0396-0500 synchronous mode serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a synchronous communication function. there is a single serial data communication format. ? data length: 8 bits ? receive error detecti on: overrun errors ? full-duplex communication the transmitting and receiving sections are inde pendent, so the sci can transmit and receive simultaneously. the transmitting and receiving s ections are both double- buffered, so serial data can be transmitted and received continuously. ? the following settings can be made for the serial data to be transferred: ? lsb-first or msb-first transfer ? inversion of data logic level ? built-in baud rate generator with selectable bit rates ? selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the sck pin ? four types of interrupts transmit-data-empty, transmit-end, receive-data-fu ll, and receive-error interrupts are requested independently. the transmit-data-empty and r eceive-data-full interrupts from sci0 can activate the dma controller (dmac) to transfer data. features of the smart card interface are listed below. ? asynchronous communication ? data length: 8 bits ? parity bits generated and checked ? error signal output in receive mode (parity error) ? error signal detect and automatic data retransmit in transmit mode ? supports both direct convention and inverse convention ? built-in baud rate generator with selectable bit rates ? three types of interrupts transmit-data-empty, receive-data-full, and tr ansmit/receive-error interrupts are requested independently. the transmit-data-empty and recei ve-data-full interrupt s can activate the dma controller (dmac) to transfer data. 13. serial communication interface rev.5.00 sep. 12, 2007 page 427 of 764 rej09b0396-0500 13.1.2 block diagram figure 13.1 shows a block diagram of the sci. rdr rsr tdr tsr ssr scr smr scmr brr / 4 /16 /64 rxd txd sck tei txi rxi eri legend: rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register scmr: smart card mode register module data bus bus interface internal data bus parity generate parity check transmit/receive control baud rate generator clock external clock figure 13.1 sci block diagram 13. serial communication interface rev.5.00 sep. 12, 2007 page 428 of 764 rej09b0396-0500 13.1.3 pin configuration the sci has serial pins for each channel as listed in table 13.1. table 13.1 sci pins channel name abbreviation i/o function 0 serial clock pin sck 0 input/output sci 0 clock input/output receive data pin rxd 0 input sci 0 receive data input transmit data pin txd 0 output sci 0 transmit data output 1 serial clock pin sck 1 input/output sci 1 clock input/output receive data pin rxd 1 input sci 1 receive data input transmit data pin txd 1 output sci 1 transmit data output 2 serial clock pin sck 2 input/output sci 2 clock input/output receive data pin rxd 2 input sci 2 receive data input transmit data pin txd 2 output sci 2 transmit data output 13. serial communication interface rev.5.00 sep. 12, 2007 page 429 of 764 rej09b0396-0500 13.1.4 register configuration the sci has internal registers as listed in table 13.2. these registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface. table 13.2 sci registers channel address * 1 name abbreviation r/w initial value 0 h'fffb0 serial mode register smr r/w h'00 h'fffb1 bit rate register brr r/w h'ff h'fffb2 serial control register scr r/w h'00 h'fffb3 transmit data register tdr r/w h'ff h'fffb4 serial status register ssr r/(w) * 2 h'84 h'fffb5 receive data register rdr r h'00 h'fffb6 smart card mode register scmr r/w h'f2 1 h'fffb8 serial mode register smr r/w h'00 h'fffb9 bit rate register brr r/w h'ff h'fffba serial control register scr r/w h'00 h'fffbb transmit data register tdr r/w h'ff h'fffbc serial status register ssr r/(w) * 2 h'84 h'fffbd receive data register rdr r h'00 h'fffbe smart card mode register scmr r/w h'f2 2 h'fffc0 serial mode register smr r/w h'00 h'fffc1 bit rate register brr r/w h'ff h'fffc2 serial control register scr r/w h'00 h'fffc3 transmit data register tdr r/w h'ff h'fffc4 serial status register ssr r/(w) * 2 h'84 h'fffc5 receive data register rdr r h'00 h'fffc6 smart card mode register scmr r/w h'f2 notes: 1. indicates the lower 20 bits of the address in advanced mode. 2. only 0 can be written, to clear flags. 13. serial communication interface rev.5.00 sep. 12, 2007 page 430 of 764 rej09b0396-0500 13.2 register descriptions 13.2.1 receive shift register (rsr) rsr is the register that receives serial data. bit 7 6 5432 10 ? ? ???? ?? read/write the sci loads serial data input at the rxd pin in to rsr in the order received, lsb (bit 0) first, thereby converting the data to parallel data. wh en one byte of data has been received, it is automatically transferred to rdr. the cpu cannot read or write rsr directly. 13.2.2 receive data register (rdr) rdr is the register that st ores received serial data. bit 7654321 0 initial value read/write r 00000 0 0 0 r r r r r r r when the sci has received one byte of serial data , it transfers the receive d data from rsr into rdr for storage, completing the r eceive operation. rsr is then ready to receive the next data. this double-buffering allows data to be received continuously. rdr is a read-only register. its contents cannot be modified by the cpu. rdr is initialized to h'00 by a reset and in standby mode. 13. serial communication interface rev.5.00 sep. 12, 2007 page 431 of 764 rej09b0396-0500 13.2.3 transmit shift register (tsr) tsr is the register that transmits serial data. bit 7 6 5432 10 ? ? ???? ?? read/write the sci loads transmit data from tdr to tsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from tdr into tsr and starts transmitting it. if the tdre flag is set to 1 in ssr, however, the sci does not load the tdr contents into tsr. the cpu cannot read or write tsr directly. 13.2.4 transmit data register (tdr) tdr is an 8-bit register that stor es data for serial transmission. bit 7 6 54 3 2 1 0 initial value read/write r/w 11 1111 11 r/w r/w r/w r/w r/w r/w r/w when the sci detects that tsr is empty, it moves transmit data written in tdr from tdr into tsr and starts serial transmission. continuous se rial transmission is po ssible by writing the next transmit data in tdr during serial transmission from tsr. the cpu can always read and write tdr. tdr is initialized to h'ff by a reset and in standby mode. 13. serial communication interface rev.5.00 sep. 12, 2007 page 432 of 764 rej09b0396-0500 13.2.5 serial mode register (smr) smr is an 8-bit register that sp ecifies the sci's serial communica tion format and selects the clock source for the baud rate generator. c/ a chr pe o/ e stop mp cks1 cks0 r/w 000 0 0000 r/w r/w r/w r/w r/w r/w r/w initial value read/write bit 76 54 32 1 0 clo c k sele c t 1/0 these bits select the baud rate g enerator's clock source communi c ation mode selects asynchronous or synchronous mode chara c ter length selects character len g th in asynchronous mode parity enable selects whether a parity bit is added parity mode selects even or odd parity stop bit length selects the stop bit len g th multipro c essor mode selects the multiprocessor function the cpu can always read and write smr. smr is initialized to h'00 by a reset and in standby mode. 13. serial communication interface rev.5.00 sep. 12, 2007 page 433 of 764 rej09b0396-0500 bit 7 ? communication mode (c/ a )/gsm mode (gm): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): selects whether the sci operates in asynchronous or synchronous mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 synchronous mode for smart card interface (smif bit in scmr set to 1): selects gsm mode for the smart card interface. bit 7 gm description 0 the tend flag is set 12.5 etu after the start bit (initial value) 1 the tend flag is set 11.0 etu after the start bit note: etu: elementary time unit (time required to transmit one bit) bit 6 ? character length (chr): selects 7-bit or 8-bits data length in asynchronous mode. in synchronous mode, the data length is 8 bits regardless of the chr setting, bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 13. serial communication interface rev.5.00 sep. 12, 2007 page 434 of 764 rej09b0396-0500 bit 5 ? parity enable (pe): in asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data , and the checking of the parity bit in receive data. in synchronous mode, the parity bit is neither added nor checked, regardless of the pe bit setting. bit 5 pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe bit is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selection by the o/ e bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the o/ e bit. bit 4 ? parity mode (o/ e ): selects even or odd parity. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is ignored in synchronous mode, or when parity addition and checking is disabled in asynchronous mode. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. when odd parity is selected, the parity bi t added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. bit 3 ? stop bit length (stop): selects one or two stop bits in asynchronous mode. this setting is used only in asynchronous mode. in synchronous mod no stop bit is added, so the stop bit setting is ignored. bit 3 stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. one stop bit (with value 1) is added to the end of each transmitted character. 2. two stop bits (with value 1) are added to the end of each transmitted character. 13. serial communication interface rev.5.00 sep. 12, 2007 page 435 of 764 rej09b0396-0500 in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit. if the second stop bit is 0, it is treated as the start bit of the next incoming character. bit 2 ? multiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, parity settings made by the pe and o/ e bits are ignored. the mp bit setting is valid only in asynchronous mode. it is ignored in synchronous mode. for further information on the multiprocessor communication function, see section 13.3.3, multiprocessor communication. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0 ? clock select 1 and 0 (cks1, cks0): these bits select the clock source for the on- chip baud rate generator. four clock sources are available: , /4, /16, and /64. for the relationship between the clock source, bit rate register setting, and baud rate, see section 13.2.8, bit rate register (brr). bit 1 cks1 bit 0 cks0 description 0 0 (initial value) 0 1 /4 1 0 /16 1 1 /64 13. serial communication interface rev.5.00 sep. 12, 2007 page 436 of 764 rej09b0396-0500 13.2.6 serial control register (scr) scr register enables or disables the sci transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. bit 7 6 5 4 3210 tie rie te re mpie teie cke1 cke0 initial value read/write r/w 0 00000 0 0 r/w r/w r/w r/w r/w r/w r/w transmit-end interrupt enable enables or disables transmit-end interrupts (tei) multipro c essor interrupt enable enables or disables multiprocessor interrupts re c eive enable enables or disables the receiver transmit enable enables or disables the transmitter re c eive interrupt enable enables or disables receive-data-full interrupts (rxi) and receive-error interrupts (eri) transmit interrupt enable enables or disables transmit-data-empty interrupts (txi) clo c k enable 1/0 these bits select the sci clock source the cpu can always read and write scr. scr is initialized to h'00 by a reset and in standby mode. 13. serial communication interface rev.5.00 sep. 12, 2007 page 437 of 764 rej09b0396-0500 bit 7 ? transmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the tdre flag in ssr is set to 1 due to transfer of serial transmit data from tdr to tsr. bit 7 tie description 0 transmit-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * txi interrupt requests can be cleared by reading the value 1 from the tdre flag, then clearing it to 0; or by clearing the tie bit to 0. bit 6 ? receive interrupt enable (rie): enables or disables the r eceive-data-full interrupt (rxi) requested when the rdrf flag in ssr is set to 1 due to transfer of serial receive data from rsr to rdr; also enables or disables th e receive-error interrupt (eri). bit 6 rie description 0 receive-data-full (rxi) and receive-error (eri) interrupt requests are disabled * (initial value) 1 receive-data-full (rxi) and receive-error (eri) interrupt requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the value 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0; or by clearing the rie bit to 0. bit 5 ? transmit enable (te): enables or disables the start of sci serial transmitting operations. bit 5 te description 0 transmitting disabled * 1 (initial value) 1 transmitting enabled * 2 notes: 1. the tdre flag is fixed at 1 in ssr. 2. in the enabled state, serial transmission starts when the tdre flag in ssr is cleared to 0 after writing of transmit data into tdr. select the transmit format in smr before setting the te bit to 1. 13. serial communication interface rev.5.00 sep. 12, 2007 page 438 of 764 rej09b0396-0500 bit 4 ? receive enable (re): enables or disables the start of sci serial receiving operations. bit 4 re description 0 receiving disabled * 1 (initial value) 1 receiving enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags. these flags retain their previous values. 2. in the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. select the receive format in smr before setting the re bit to 1. bit 3 ? multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is valid only in asynchronous mode, and only if the mp bit is set to 1 in smr. the mpie bit setting is ignored in synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts are disabled (nor mal receive operation) (initial value) [clearing conditions] ? the mpie bit is cleared to 0 ? mpb = 1 in received data 1 multiprocessor interrupts are enabled * receive-data-full interrupts (rxi), receive-error interrupts (eri), and setting of the rdrf, fer, and orer status flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * the sci does not transfer receive data from rsr to rdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in ssr. when it receives data in which mpb = 1, the sci sets the mpb bit to 1 in ssr, automatically clears the mpie bit to 0, enables rxi and eri interrupts (if the tie and rie bits in scr are set to 1), and allows the fer and orer flags to be set. 13. serial communication interface rev.5.00 sep. 12, 2007 page 439 of 764 rej09b0396-0500 bit 2 ? transmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain valid transmit data when the msb is transmitted. bit 2 teie description 0 transmit-end interrupt requests (tei) are disabled * (initial value) 1 transmit-end interrupt requests (tei) are enabled * note: * tei interrupt requests can be cleared by reading the value 1 from the tdre flag in ssr, then clearing the tdre flag to 0, thereby also clearing the tend flag to 0; or by clearing the teie bit to 0. bits 1 and 0 ? clock enable 1 and 0 (cke1, cke0): the function of these bits differs for the normal serial communication interface and for the smart card interface. their function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): these bits select the sci clock source and enable or disable clock output from the sck pin. depending on the settings of cke1 and cke0, the sck pin can be used for generic input/output, serial clock output, or serial clock input. the cke0 setting is valid only in asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in synchronous mode, or when an external clock source is selected (cke1 = 1). select the sci operating mode in smr before setting the cke1 and cke0 bits. for further details on selection of the sci clock source, see table 13.9 in section 13.3, operation. bit 1 cke1 bit 0 cke0 description 0 0 asynchronous mode internal clock, sck pin available for generic input/output * 1 synchronous mode internal clock, sck pin used for serial clock output * 1 0 1 asynchronous mode internal clock, sck pin used for clock output * 2 synchronous mode internal clock, sck pin used for serial clock output 1 0 asynchronous mode external clock, sck pin used for clock input * 3 synchronous mode external clock, sck pin used for serial clock input 1 1 asynchronous mode external clock, sck pin used for clock input * 3 synchronous mode external clock, sck pin used for serial clock input notes: 1. initial value 2. the output clock frequency is the same as the bit rate. 3. the input clock frequency is 16 times the bit rate. 13. serial communication interface rev.5.00 sep. 12, 2007 page 440 of 764 rej09b0396-0500 for smart card interface (smif bit in scmr set to 1): these bits, together with the gm bit in smr, determine whether the sck pin is used for generic input/output or as the serial clock output pin. smr gm bit 1 cke1 bit 0 cke0 description 0 0 0 sck pin available for generic input/output (initial value) 0 0 1 sck pin used for clock output 1 0 0 sck pin output fixed low 1 0 1 sck pin used for clock output 1 1 0 sck pin output fixed high 1 1 1 sck pin used for clock output 13. serial communication interface rev.5.00 sep. 12, 2007 page 441 of 764 rej09b0396-0500 13.2.7 serial status register (ssr) ssr is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the sci. initial value read/write rr/w 0 1000100 bit 76 54 32 1 0 multiprocessor bit transfer value of multiprocessor bit to be transmitted r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r tdre rdrf orer fer/ers per tend mpb mpbt multiprocessor bit stores the received multiprocessor bit value transmit end * 2 status flag indicating end of transmission parity error status flag indicating detection of a receive parity error framing error (fer)/error signal status (ers) * 2 status flag indicating detection of a receive framing error, or flag indicating detection of an error signal overrun error status flag indicating detection of a receive overrun error receive data register full status flag indicating that data has been received and stored in rdr transmit data register empty status flag indicating that transmit data has been transferred from tdr into tsr and new data can be written in tdr notes: 1. only 0 can be written, to clear the flag. 2. function differs between the normal serial communication interface and the smart card interface. 13. serial communication interface rev.5.00 sep. 12, 2007 page 442 of 764 rej09b0396-0500 the cpu can always read and write ssr, but cannot write 1 in the tdre, rdrf, orer, per, and fer flags. these flags can be cleared to 0 only if they have first been read while set to 1. the tend and mpb flags are read-only bits that cannot be written. ssr is initialized to h'84 by a reset and in standby mode. bit 7 ? transmit data register empty (tdre): indicates that the sci has loaded transmit data from tdr into tsr and the next serial data can be written in tdr. bit 7 tdre description 0 tdr contains valid transmit data [clearing conditions] ? read tdre when tdre = 1, then write 0 in tdre ? the dmac writes data in tdr 1 tdr does not contain valid transmit data (initial value) [setting conditions] ? the chip is reset or enters standby mode ? the te bit in scr is cleared to 0 ? tdr contents are loaded into tsr, so new data can be written in tdr bit 6 ? receive data register full (rdrf): indicates that rdr cont ains new receive data. bit 6 rdrf description 0 rdr does not contain new receive data (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read rdrf when rdrf = 1, then write 0 in rdrf ? the dmac reads data from rdr 1 rdr contains new receive data [setting condition] serial data is received normally and transferred from rsr to rdr note: the rdr contents and the rdrf flag are not affected by detection of receive errors or by clearing of the re bit to 0 in scr. they retain their previous values. if the rdrf flag is still set to 1 when reception of the next data ends, an overrun error will occur and the receive data will be lost. 13. serial communication interface rev.5.00 sep. 12, 2007 page 443 of 764 rej09b0396-0500 bit 5 ? overrun error (orer): indicates that data reception ended abnormally due to an overrun error. bit 5 orer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read orer when orer = 1, then write 0 in orer 1 a receive overrun error occurred * 2 [setting condition] reception of the next serial data ends when rdrf = 1 notes: 1. clearing the re bit to 0 in scr does not affect the orer flag, which retains its previous value. 2. rdr continues to hold the receive data prior to the overrun error, so subsequent receive data is lost. serial receiving cannot continue while the orer flag is set to 1. in synchronous mode, serial transmitting is also disabled. bit 4 ? framing error (fer)/erro r signal status (ers): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. for serial communication interface (smif bit in scmr cleared to 0): indicates that data reception ended abnormally due to a framing error in asynchronous mode. bit 4 fer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read fer when fer = 1, then write 0 in fer 1 a receive framing error occurred [setting condition] the stop bit at the end of the receive data is checked and found to be 0 * 2 notes: 1. clearing the re bit to 0 in scr does not affect the fer flag, which retains its previous value. 2. when the stop bit length is 2 bits, only the first bit is checked. the second stop bit is not checked. when a framing error occurs the sci transfers the receive data into rdr but does not set the rdrf flag. serial receiving cannot continue while the fer flag is set to 1. in synchronous mode, serial transmitting is also disabled. 13. serial communication interface rev.5.00 sep. 12, 2007 page 444 of 764 rej09b0396-0500 for smart card interface (smif bit in scmr set to 1): indicates the status of the error signal sent back from the receiving side during transmi ssion. framing errors are not detected in smart card interface mode. bit 4 ers description 0 normal reception, no error signal * (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read ers when ers = 1, then write 0 in ers 1 an error signal has been sent from the receiving side indicating detection of a parity error [setting condition] the error signal is low when sampled note: * clearing the te bit to 0 in scr does not affect the ers flag, which retains its previous value. bit 3 ? parity error (per): indicates that data reception ended abnormally due to a parity error in asynchronous mode. bit 3 per description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? the chip is reset or enters standby mode ? read per when per = 1, then write 0 in per 1 a receive parity error occurred * 2 [setting condition] the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of o/ e in smr notes: 1. clearing the re bit to 0 in scr does not affect the per flag, which retains its previous value. 2. when a parity error occurs the sci transfers the receive data into rdr but does not set the rdrf flag. serial receiving cannot continue while the per flag is set to 1. in synchronous mode, serial transmitting is also disabled. bit 2 ? transmit end (tend): the function of this bit differs for the normal serial communication interface and for the smart card interface. its function is switched with the smif bit in scmr. 13. serial communication interface rev.5.00 sep. 12, 2007 page 445 of 764 rej09b0396-0500 for serial communication interface (smif bit in scmr cleared to 0): indicates that when the last bit of a serial character was transmitted tdr did not contain valid transmit data, so transmission has ended. the tend flag is a read-only bit and cannot be written. bit 2 tend description 0 transmission is in progress [clearing conditions] ? read tdre when tdre = 1, then write 0 in tdre ? the dmac writes data in tdr 1 end of transmission (initial value) [setting conditions] ? the chip is reset or enters standby mode ? the te bit in scr is cleared to 0 ? tdre is 1 when the last bit of a 1-byte serial transmit character is transmitted for smart card interface (smif bit in scmr set to 1): indicates that when the last bit of a serial character was transmitted tdr did not contain valid transmit data, so transmission has ended. the tend flag is a read -only bit and cannot be written. bit 2 tend description 0 transmission is in progress [clearing conditions] ? read tdre when tdre = 1, then write 0 in tdre ? the dmac writes data in tdr 1 end of transmission (initial value) [setting conditions] ? the chip is reset or enters standby mode ? the te bit is cleared to 0 in scr and the fer/ers bit is also cleared to 0 ? tdre is 1 and fer/ers is 0 (normal transmission) 2.5 etu (when gm = 0) or 1.0 etu (when gm = 1) after a 1-byte serial character is transmitted note: etu: elementary time unit (time required to transmit one bit) 13. serial communication interface rev.5.00 sep. 12, 2007 page 446 of 764 rej09b0396-0500 bit 1 ? multiprocessor bit (mpb): stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. mpb is a read-only bit, and cannot be written. bit 1 mpb description 0 multiprocessor bit value in receive data is 0 * (initial value) 1 multiprocessor bit value in receive data is 1 note: * if the re bit in scr is cleared to 0 when a multiprocessor format is selected, mpb retains its previous value. bit 0 ? multiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. the mpbt bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the sci cannot transmit. bit 0 mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1 13.2.8 bit rate register (brr) brr is an 8-bit register that, together with the cks1 and cks0 bits in smr that select the baud rate generator clock source, determines the serial communication bit rate. bit initial value read/write 7 r/w r/w r/w r/w r/w r/w r/w r/w 6 1 11 1 11 11 5 4 32 1 0 the cpu can always read and write brr. brr is initialized to h'ff by a reset and in standby mode. each sci channel has independent baud rate generator control, so different values can be set in the three channels. table 13.3 shows examples of brr settings in asynchronous mode. table 13.4 shows examples of brr settings in synchronous mode. 13. serial communication interface rev.5.00 sep. 12, 2007 page 447 of 764 rej09b0396-0500 table 13.3 examples of bit rates and brr settings in asynchronous mode (mhz) 2 2.097152 2.4576 3 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 141 0.03 1 148 ? 0.04 1 174 ? 0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ? 0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ? 2.48 0 15 0.00 0 19 ? 2.34 9600 0 6 ? 6.99 0 6 ? 2.48 0 7 0.00 0 9 ? 2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ? 2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ? 18.62 0 1 ? 14.67 0 1 0.00 ? ? ? (mhz) 3.6864 4 4.9152 5 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 64 0.07 2 70 0.03 2 86 0.31 2 88 ? 0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ? 1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ? 6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ? 1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 13. serial communication interface rev.5.00 sep. 12, 2007 page 448 of 764 rej09b0396-0500 (mhz) 6 6.144 7.3728 8 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 106 ? 0.44 2 108 0.08 2 130 ? 0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ? 2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ? 2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 ? 2.34 0 4 0.00 0 5 0.00 0 6 ? 6.99 (mhz) 9.8304 10 12 12.288 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 174 ? 0.26 2 177 ? 0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ? 1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ? 2.34 0 19 0.00 31250 0 9 ? 1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ? 2.34 0 9 0.00 13. serial communication interface rev.5.00 sep. 12, 2007 page 449 of 764 rej09b0396-0500 (mhz) 13 14 14.7456 16 18 20 bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 230 ? 0.08 2 248 ? 0.17 3 64 0.70 3 70 0.03 3 79 ? 0.12 3 88 ? 0.25 150 2 168 0.16 2 181 0.16 2 191 0.00 2 207 0.16 2 233 0.16 3 64 0.16 300 2 84 ? 0.43 2 90 0.16 2 95 0.00 2 103 0.16 2 116 0.16 2 129 0.16 600 1 168 0.16 1 181 0.16 1 191 0.00 1 207 0.16 1 233 0.16 2 64 0.16 1200 1 84 ? 0.43 1 90 0.16 1 95 0.00 1 103 0.16 1 116 0.16 1 129 0.16 2400 0 168 0.16 0 181 0.16 0 191 0.00 0 207 0.16 0 233 0.16 1 64 0.16 4800 0 84 ? 0.43 0 90 0.16 0 95 0.00 0 103 0.16 0 116 0.16 0 129 0.16 9600 0 41 0.76 0 45 ? 0.93 0 47 0.00 0 51 0.16 0 58 ? 0.69 0 64 0.16 19200 0 20 0.76 0 22 ? 0.93 0 23 0.00 0 25 0.16 0 28 1.02 0 32 ? 1.36 31250 0 12 0.00 0 13 0.00 0 14 ? 1.70 0 15 0.00 0 17 0.00 0 19 0.00 38400 0 10 ? 3.82 0 10 3.57 0 11 0.00 0 12 0.16 0 14 ? 2.34 0 15 1.73 13. serial communication interface rev.5.00 sep. 12, 2007 page 450 of 764 rej09b0396-0500 table 13.4 examples of bit rates and brr settings in synchronous mode (mhz) 2 4 8 10 13 16 18 20 bit rate (bit/s) n n n n n n n n n n n n n n n n 110 3 70 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 250 2 124 2 249 3 124 ? ? 3 202 3 249 ? ? ? ? 500 1 249 2 124 2 249 ? ? 3 101 3 124 3 140 3 155 1k 1 124 1 249 2 124 ? ? 2 202 2 249 3 69 3 77 2.5k 0 199 1 99 1 199 1 249 2 80 2 99 2 112 2 124 5k 0 99 0 199 1 99 1 124 1 162 1 199 1 224 1 249 10k 0 49 0 99 0 199 0 249 1 80 1 99 1 112 1 124 25k 0 19 0 39 0 79 0 99 0 129 0 159 0 179 0 199 50k 0 9 0 19 0 39 0 49 0 64 0 79 0 89 0 99 100k 0 4 0 9 0 19 0 24 ? ? 0 39 0 44 0 49 250k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 0 19 500k 0 0 * 0 1 0 3 0 4 ? ? 0 7 0 8 0 9 1m 0 0 * 0 1 ? ? ? ? 0 3 0 4 0 4 2m 0 0 * ? ? ? ? 0 1 ? ? ? ? 2.5m ? ? 0 0 * ? ? ? ? ? ? ? ? 4m 0 0 * ? ? ? ? legend: blank: no setting available ? : setting possible, but error occurs * : continuous transmission/reception not possible note: settings with an error of 1 % or less are recommended. 13. serial communication interface rev.5.00 sep. 12, 2007 page 451 of 764 rej09b0396-0500 the brr setting is calculated as follows: asynchronous mode: n = 64 2 2n-1 b 10 6 ? 1 synchronous mode: n = 8 2 2n-1 b 10 6 ? 1 legend: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : system clock frequency (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see the following table.) smr settings n clock source cks1 cks0 0 0 0 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is calculated as follows: error ( % ) = (n + 1) b 64 2 2n-1 ? 1 100 10 6 13. serial communication interface rev.5.00 sep. 12, 2007 page 452 of 764 rej09b0396-0500 table 13.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. table 13.6 and 13.7 shows the maximum bit rates with external clock input. table 13.5 maximum bit rates for vari ous frequencies (asynchronous mode) settings (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 20 625000 0 0 13. serial communication interface rev.5.00 sep. 12, 2007 page 453 of 764 rej09b0396-0500 table 13.6 maximum bit rates with external clock input (asynchronous mode) (mhz) external input clock (m hz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 20 5.0000 312500 13. serial communication interface rev.5.00 sep. 12, 2007 page 454 of 764 rej09b0396-0500 table 13.7 maximum bit rates with external clock input (synchronous mode) (mhz) external input clock (m hz) maximum bit rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 13.3 operation 13.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. a sm art card interface is also supported as a serial communication function for an ic card interface. selection of asynchronous or synchronous mode and the transmission format for the normal serial communication interface is made in smr, as s hown in table 13.8. the sci clock source is selected by the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 13.9. for details of the procedures for switching between lsb-first and msb-first mode and inverting the data logic level, see section 14.2.1, smart card mode register (scmr). for selection of the smart card interface format, see section 14.3.3, data format. asynchronous mode ? data length is selectable: 7 or 8 bits ? parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). these selections determine the communica tion format and character length. ? in receiving, it is possible to de tect framing errors, parity errors, overrun errors, and the break state. 13. serial communication interface rev.5.00 sep. 12, 2007 page 455 of 764 rej09b0396-0500 ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. ? when an external clock is sel ected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode ? the communication format has a fixed 8-bit data length. ? in receiving, it is possible to detect overrun errors. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal to external devices. ? when an external clock is selected, the sci operates on the input serial clock. the on-chip baud rate generator is not used. smart card interface ? one frame consists of 8-bit data and a parity bit. ? in transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of the next frame. (an elementary time unit is the time required to transmit one bit.) ? in receiving, if a parity error is detected, a lo w error signal level is out put for 1 etu, beginning 10.5 etu after the start bit.. ? in transmitting, if an error signal is received, the same data is automatically transmitted again after at least 2 etu. ? only asynchronous communication is supported. there is no synchronous communication function. for details of smart card interface operation, see section 14, smart card interface. 13. serial communication interface rev.5.00 sep. 12, 2007 page 456 of 764 rej09b0396-0500 table 13.8 smr settings and serial communication formats smr settings sci communication format bit 7 c/ a bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multi- processor bit parity bit stop bit length 0 0 0 0 0 8-bit data absent absent 1 bit 1 2 bits 1 0 asyn- chronous mode present 1 bit 1 2 bits 1 0 0 7-bit data absent 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 0 1 ? 0 8-bit data present absent 1 bit ? 1 2 bits 1 ? 0 7-bit data 1 bit ? 1 asyn- chronous mode (multi- processor 2 bits 1 ? ? ? ? syn- chronous mode 8-bit data absent none table 13.9 smr and scr settings and sci clock so urce selection smr scr setting sci transmit/receive clock bit 7 c/ a bit 1 cke1 bit 0 cke0 mode clock source sck pin function 0 0 0 internal sci does not use the sck pin 1 asynchronous mode outputs clock with frequency matching the bit rate 1 0 external inputs clock with frequency 16 times the bit 1 rate 1 0 0 internal outputs the serial clock 1 synchronous mode 1 0 external inputs the serial clock 1 13. serial communication interface rev.5.00 sep. 12, 2007 page 457 of 764 rej09b0396-0500 13.3.2 operation in asynchronous mode in asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full-duplex communication is possible. the transmitter and the receiver are bo th double-buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 13.2 shows the general format of asynchronous serial communication. in asynchronous serial communication the communicati on line is normally held in the mark (high) state. the sci monitors the line and starts se rial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and one or two stop bits (high), in that order. when receiving in asynchronous mode, the sci synchr onizes at the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 1 d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 idle (mark) state 1 (msb) (lsb) 0 1 serial data start bit 1 bit transmit or receive data 7 or 8 bits one unit of data (character or frame) 1 bit, or none parity bit 1 or 2 bits stop bit(s) figure 13.2 data format in asynchronous communication (example: 8-bit data with parity and 2 stop bits) communication formats: table 13.10 shows the 12 communica tion formats that can be selected in asynchronous mode. the format is selected by settings in smr. 13. serial communication interface rev.5.00 sep. 12, 2007 page 458 of 764 rej09b0396-0500 table 13.10 serial communication formats (asynchronous mode) 7-bit data stop stop mpb stop mpb stop p stop stop p stop stop smr settings chr pe mp stop 00 0 0 00 0 1 01 0 0 01 0 1 10 0 0 10 0 1 11 0 0 11 0 1 0 ? 10 0 ? 11 1 ? 10 1 ? 11 serial communication format and frame length 123456789101112 stop 8-bit data s 8-bit data s stop p 8-bit data s 8-bit data s stop 7-bit data s 7-bit data s 7-bit data s s 8-bit data s stop stop mpb 8-bit data s 7-bit data s 7-bit data s p stop stop stop stop stop mpb legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit 13. serial communication interface rev.5.00 sep. 12, 2007 page 459 of 764 rej09b0396-0500 clock: an internal clock generated by the on-chip ba ud rate generator or an external clock input from the sck pin can be selected as the sci tran smit/receive clock. the clock source is selected by the c/ a bit in smr and bits cke1 and cke0 in scr. for details of sci clock source selection, see table 13.9. when an external clock is input at the sck pin, it must have a frequency 16 times the desired bit rate. when the sci is operated on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as shown in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit. d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 0 1 frame figure 13.3 phase relationship between output clock and serial data (asynchronous mode) transmitting and receiving data: ? sci initialization (asynchronous mode): before transmitting or receiving data, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or form at, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets the tdre flag to 1 and initializes tsr. clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags, or rdr, which retain their previous contents. when an external clock is used the clock should not be stopped during initialization or subsequent operation, since operation will be unreliable in this case. figure 13.4 shows a sample flowchart for initializing the sci. 13. serial communication interface rev.5.00 sep. 12, 2007 page 460 of 764 rej09b0396-0500 start of initialization set value in brr select communication format in smr 1-bit interval elapsed? wait (4) (3) (2) (1) yes no 13. serial communication interface rev.5.00 sep. 12, 2007 page 461 of 764 rej09b0396-0500 ? transmitting serial data (asynchronous mode): figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. yes yes 13. serial communication interface rev.5.00 sep. 12, 2007 page 462 of 764 rej09b0396-0500 in transmitting serial data, the sci operates as follows: ? the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0, the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: ? start bit: one 0 bit is output. ? transmit data: 7 or 8 bits are output, lsb first. ? parity bit or multiprocessor bit: one parity bit (even or odd parity),or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. ? stop bit(s): one or two 1 bits (stop bits) are output. ? mark state: output of 1 bits continues until the start bit of the next transmit data. ? the sci checks the tdre flag wh en it outputs the stop bit. if the tdre flag is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit- end interrupt (tei) is requested at this time figure 13.6 shows an example of sci transmit operation in asynchronous mode. 0 / 1 d0 d1 d7 0 / 11 1 0 start bit 0d0d1 d7 1 1 data parity bit stop bit start bit data parity bit stop bit tdre tend idle state (mark state) tei interrupt request txi interrupt request txi interrupt handler writes data in tdr and clears tdre flag to 0 txi interrupt request 1 frame figure 13.6 example of sci transmit operation in asynchronous mode (8-bit data with parity and one stop bit) 13. serial communication interface rev.5.00 sep. 12, 2007 page 463 of 764 rej09b0396-0500 ? receiving serial data (asynchr onous mode): figure 13.7 s hows a sample flowchart for receiving serial data and indicates the procedure to follow. yes yes no no 13. serial communication interface rev.5.00 sep. 12, 2007 page 464 of 764 rej09b0396-0500 yes 13. serial communication interface rev.5.00 sep. 12, 2007 page 465 of 764 rej09b0396-0500 in receiving, the sci operates as follows: ? the sci monitors the communication line. when it detects a start bit (0 bit), the sci synchronizes internally and starts receiving. ? receive data is stored in rsr in order from lsb to msb. ? the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks: ? parity check: the number of 1s in the receive data must match the even or odd parity setting of in the o/ e bit in smr. ? stop bit check: the stop bit value must be 1. if there are two stop bits, only the first is checked. ? status check: the rdrf flag must be 0, indica ting that the receive data can be transferred from rsr into rdr. if these all checks pass, the rdrf fl ag is set to 1 and the received data is stored in rdr. if one of the checks fails (receive error*), the sci operates as shown in table 13.11. note: * when a receive error occurs, further recei ving is disabled. in r eceiving, the rdrf flag is not set to 1. be sure to clear the error flags to 0. ? when the rdrf flag is set to 1, if the rie bit is set to 1 in scr, a receive-data-full interrupt (rxi) is requested. if the orer, per, or fer flag is set to 1 and the rie bit in scr is also set to 1, a receive-error interrupt (eri) is requested. table 13.11 receive error conditions receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf flag is still set to 1 in ssr receive data is not transferred from rsr to rdr framing error fer stop bit is 0 receive data is transferred from rsr to rdr parity error per parity of received data differs from even/odd parity setting in smr receive data is transferred from rsr to rdr 13. serial communication interface rev.5.00 sep. 12, 2007 page 466 of 764 rej09b0396-0500 figure 13.8 shows an example of sci r eceive operation in asynchronous mode. 0 / 1 d0 d1 d7 0 / 11 1 0 start bit 0d0d1 d7 1 1 data data parity bit parity bit stop bit stop bit stop bit start bit rdrf fer idle (mark) state framin g error, eri request rxi request rxi interrupt handler reads data in rdr and clears rdrf fla g to 0 1 frame figure 13.8 example of sci r eceive operation (8-bit data wi th parity and one stop bit) 13.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of an id-sending cycl e that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit disti nguishes id-sending cycl es from data-sending cycles. the transmitting processor stars by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. processors with ids not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 13.9 shows an example of communication among different processors using a multiprocessor format. communication formats: four formats are available. parity bit settings are ignored when a multiprocessor format is selected. for details see table 13.10. clock: see the description of asynchronous mode. 13. serial communication interface rev.5.00 sep. 12, 2007 page 467 of 764 rej09b0396-0500 (id = 04) (id = 01) (id = 02) (id = 03) transmittin g processor receivin g processor b receivin g processor a receivin g processor c receivin g processor d h'01 (mpb = 1) serial data h'aa (mpb = 0) serial communication line id-sendin g cycle: receivin g processor address data-sendin g cycle: data sent to receivin g processor specified by id le g end: mpb : multiprocessor bit figure 13.9 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting and receiving data: ? transmitting multiprocessor serial data: figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. 13. serial communication interface rev.5.00 sep. 12, 2007 page 468 of 764 rej09b0396-0500 tend = 1 no no read tend fla g in ssr yes yes yes yes no no 13. serial communication interface rev.5.00 sep. 12, 2007 page 469 of 764 rej09b0396-0500 in transmitting serial data, the sci operates as follows: ? the sci monitors the tdre flag in ssr. when the tdre flag is cleared to 0, the sci recognizes that tdr contains new data, and loads this data from tdr into tsr. ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: ? start bit: one 0 bit is output. ? transmit data: 7 or 8 bits are output, lsb first. ? multiprocessor bit: one multiprocessor bit (mpbt value) is output. ? stop bit(s): one or two 1 bits (stop bits) are output. ? mark state: output of 1 bits continues until the start bit of the next transmit data. ? the sci checks the tdre flag wh en it outputs the stop bit. if the tdre flag is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit is set to 1 in scr, a transmit- end interrupt (tei) is requested at this time figure 13.11 shows an example of sci transmit operation using a multiprocessor format. d0 d1 d7 0/1 1 1 0 start bit 0 d0 d1 d7 0/1 1 data multi- processor bit stop bit start bit data multi- processor bit stop bit tdre tend idle (mark) state tei interrupt request txi interrupt request txi interrupt handler writes data in tdr and clears tdre fla g to 0 txi interrupt request 1 frame figure 13.11 example of sci transmit operation (8-bit data with multiprocessor bit and one stop bit) 13. serial communication interface rev.5.00 sep. 12, 2007 page 470 of 764 rej09b0396-0500 ? receiving multiprocessor serial data: figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. read rdrf fla g in ssr no yes yes yes no yes yes no no no read orer and fer fla g s in ssr (3) (1) (2) (4) (1) (2) (3) (4) (5) rdrf = 1 fer orer = 1 fer orer = 1 start receivin g own id? 13. serial communication interface rev.5.00 sep. 12, 2007 page 471 of 764 rej09b0396-0500 yes yes no no 13. serial communication interface rev.5.00 sep. 12, 2007 page 472 of 764 rej09b0396-0500 figure 13.13 shows an example of sci receive operation using a multiprocessor format. id2 data2 idle (mark) state not own id, so mpie bit is set to 1 a g ain a. own id does not match data b. own id matches data d0 d1 d7 1 1 0 start bit start bit stop bit stop bit 0 d0 d1 d7 0 1 1 data (id1) data (data1) start bit stop bit stop bit data (data1) mpie idle (mark) state 1 mpb rdrf rdr value rdr value rxi interrupt request (multiprocessor interrupt) mpb detection mpie = 0 rxi interrupt handler reads rdr data and clears rdrf fla g to 0 no rxi interrupt request, rdr not updated id1 mpb d0 d1 d7 1 1 0 start bit 0 d0 d1 d7 0 1 1 data (id2) mpie 1 mpb rdrf rxi interrupt request (multiprocessor interrupt) mpb detection mpie = 0 rxi interrupt handler reads rdr data and clears rdrf fla g to 0 own id, so receivin g continues, with data received by rxi interrupt handler mpb id1 mpie bit is set to 1 a g ain figure 13.13 example of sci receive operation (8-bit data with multiprocessor bit and one stop bit) 13. serial communication interface rev.5.00 sep. 12, 2007 page 473 of 764 rej09b0396-0500 13.3.4 synchronous operation in synchronous mode, the sci transmits and receive s data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible. the transmitter and the receiver are also double-buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 13.14 shows the general format in synchronous serial communication. don't care one unit (character or frame) of transfer data msb bit 0 bit 1 bit 3 bit 2 bit 4 bit 5 bit 6 bit 7 lsb don't care serial clock serial data * * note: * hi g h except in continuous transmittin g or receivin g figure 13.14 data format in synchronous communication in synchronous serial communica tion, each data bit is placed on the communication line from one falling edge of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in each character, the serial data bits are transferred in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb. in synchronous mode the sci receives data by synchronizing w ith the rise of the serial clock. communication format: the data length is fixed at 8 bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip ba ud rate generator or an external clock input from the sck pin can be selected by means of the c/ a bit in smr and the cke1 and cke0 bits in scr. see table 13.9 for details of sci clock source selection. when the sci operates on an internal clock, it outputs the clock source at the sck pin. eight clock pulses are output per transmitted or receive d character. when the sci is not transmitting or receiving, the clock signal remains in the high st ate. if receiving in single-character units is required, an external clock should be selected. 13. serial communication interface rev.5.00 sep. 12, 2007 page 474 of 764 rej09b0396-0500 transmitting and receiving data: ? sci initialization (synchronous mode): before tr ansmitting or receiving data, clear the te and re bits to 0 in scr, then initialize the sci as follows. when changing the communication mode or form at, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets the tdre flag to 1 and initializes tsr. clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags, or rdr, which retain their previous contents. figure 13.15 shows a sample flowchart for initializing the sci. 13. serial communication interface rev.5.00 sep. 12, 2007 page 475 of 764 rej09b0396-0500 ? transmitting serial data (synchronous mode): figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 13. serial communication interface rev.5.00 sep. 12, 2007 page 476 of 764 rej09b0396-0500 ? after loading the data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmitting. if the tie bit is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output is selected, the sci outputs eight serial clock pulses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data is output from the txd pin n order from lsb (bit 0) to msb (bit 7). ? the sci checks the tdre fl ag when it outputs the msb (bit 7). if the tdre flag is 0, the sci loads data from tdr into tsr and begins serial transmission of the next frame. if the tdre flag is 1, the sci sets the tend flag to 1 in ssr, and after transmitting the msb, holds the txd pin in the msb state. if the teie bit is set to 1 in scr, a transmit-end interrupt (tei) is requested at this time ? after the end of serial transmission, the sck pin is held in a constant state. figure 13.17 shows an example of sci transmit operation. bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 serial clock serial data 1 frame txi interrupt request txi interrupt handler writes data in tdr and clears tdre fla g to 0 txi interrupt request tei interrupt request transmit direction tend tdre figure 13.17 example of sci transmit operation 13. serial communication interface rev.5.00 sep. 12, 2007 page 477 of 764 rej09b0396-0500 ? receiving serial data (synchr onous mode): figure 13.18 shows a sample flowchart for receiving serial data an d indicates the procedure to follo w. when switching from asynchronous to synchronous mode, make sure that the orer, per, and fer flags are cleared to 0. if the fer or per flag is set to 1 the rdrf flag will not be set and both transmitting and receiving will be disabled. yes yes no no 13. serial communication interface rev.5.00 sep. 12, 2007 page 478 of 764 rej09b0396-0500 13. serial communication interface rev.5.00 sep. 12, 2007 page 479 of 764 rej09b0396-0500 serial clock serial data rxi interrupt handler reads data in rdr and clears rdrf fla g to 0 rxi interrupt request rxi interrupt request overrun error, eri interrupt request orer rdrf bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 1 frame figure 13.19 example of sci receive operation 13. serial communication interface rev.5.00 sep. 12, 2007 page 480 of 764 rej09b0396-0500 ? transmitting and receiving data simultaneously (synchronous mode): figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. yes no no 13. serial communication interface rev.5.00 sep. 12, 2007 page 481 of 764 rej09b0396-0500 13.4 sci interrupts the sci has four interrupt request sources: tran smit-end interrupt (tei), receive-error (eri), receive-data-full (rxi), and transm it-data-empty interrupt (txi). table 13.12 lists the interrupt sources and indicates their priority. these interrupt s can be enabled or disabled by the tie, rie, and teie bits in scr. each interrupt request is sent separately to the interrupt controller. a txi interrupt is requested when the tdre flag is set to 1 in ssr. a tei interrupt is requested when the tend flag is set to 1 in ssr. a txi interrupt request can activate the dmac to transfer data. data transfer by the dmac automatically clears the tdre flag to 0. a tei interrupt request cannot activate the dmac. an rxi interrupt is requested when the rdrf fl ag is set to 1 in ssr. an eri interrupt is requested when the orer, per, or fer flag is se t to 1 in ssr. an rxi interrupt can activate the dmac to transfer data. data transfer by the dm ac automatically clears th e rdrf flag to 0. an eri interrupt request cannot activate the dmac. the dmac can be activated by interrupts from sci channel 0. table 13.12 sci interrupt sources interrupt source description priority eri receive error (orer, fer, or per) high rxi receive data register full (rdrf) txi transmit data register empty (tdre) tei transmit end (tend) low 13. serial communication interface rev.5.00 sep. 12, 2007 page 482 of 764 rej09b0396-0500 13.5 usage notes 13.5.1 notes on use of sci note the following points when using the sci. tdr write and tdre flag: the tdre flag in ssr is a stat us flag indicating the loading of transmit data from tdr to tsr. the sci sets the tdre flag to 1 when it transfers data from tdr to tsr. data can be written into tdr regardless of the state of the tdre flag. if new data is written in tdr when the tdre flag is 0, the old data stored in tdr will be lost because this data has not yet been transferred to tsr. before writing transmit data in tdr, be sure to check that the tdre flag is set to 1. simultaneous multiple receive errors: table 13.13 shows the state of the ssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs the rsr contents are not transferred to rdr, so receive data is lost. table 13.13 ssr status flags and transfer of receive data ssr status flags rdrf orer fer per receive data transfer rsr rdr receive errors 1 1 0 0 not transferred overrun error 0 0 1 0 transferred framing error 0 0 0 1 transferred parity error 1 1 1 0 not transferred overrun error + framing error 1 1 0 1 not transferred overrun error + parity error 0 0 1 1 transferred framing error + parity error 1 1 1 1 not transferred overrun error + framing error + parity error break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. in the break state the sci receiver continues to operate, so if the fer flag is cleared to 0 it will be set to 1 again. 13. serial communication interface rev.5.00 sep. 12, 2007 page 483 of 764 rej09b0396-0500 sending a break signal: the input/output condition and level of the txd pin are determined by dr and ddr bits. this feature can be used to send a break signal. after the serial transmitter is initialized, the dr value substitutes for the mark state until the te bit is set to 1 (the txd pin function is not sel ected until the te bit is set to 1). the ddr and dr bits should therefore be set to 1 beforehand. to send a break signal during serial transmission, clear the dr bit to 0 , then clear the te bit to 0. when the te bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the txd pin becomes an input/output outputting the value 0. receive error flags and transmitter operation (s ynchronous mode only): when a receive error flag (orer, per, or fer) is set to 1 th e sci will not start transmitting, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 wh en starting to transmit. note that clearing the re bit to 0 does not cl ear the receive error flags to 0. receive data sampling timing in asyn chronous mode and receive margin: in asynchronous mode the sci operates on a base clock with 16 times the bit rate frequency. in receiving, the sci synchronizes internally with the fa ll of the start bit, which it sa mples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. see figure 13.21. 15 0 internal base clock 8 clocks 7 0 receive data (rxd) synchronization samplin g timin g data samplin g timin g 15 0 d 0 d 1 start bit 16 clocks 7 figure 13.21 receive data samplin g timing in asynchronous mode 13. serial communication interface rev.5.00 sep. 12, 2007 page 484 of 764 rej09b0396-0500 the receive margin in asynchronous mode can therefore be expressed as shown in equation (1). m = (0.5 ? 1 2n d ? 0.5 n ) ? (l ? 0.5) f ? (1 + f) 100 % . . . . . . . . (1) m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (l = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875 % , as given by equation (2). m = 2 16 ) 100 % (0.5 ? 1 d = 0.5, f = 0 = 46.875 % . . . . . . . . (2) this is a theoretical value. a reasonable margin to allow in system designs is 20 % to 30 % . restrictions on use of dmac: ? when an external clock source is used for the serial clock, after the dmac updates tdr, allow an inversion of at least five system clock ( ) cycles before input of the serial clock to start transmitting. if the serial clock is i nput within four states of the tdr update, a malfunction may occur. (see figure 13.22) ? to have the dmac read rdr, be sure to select the corresponding sci receive-data-full interrupt (rxi) as the activation source with bits dts2 to dts0 in dtcr. 13. serial communication interface rev.5.00 sep. 12, 2007 page 485 of 764 rej09b0396-0500 sck d0 d1 d2 d3 d4 d5 d6 d7 tdre t note: in operation with an external clock source, be sure that t >4 states. figure 13.22 example of synchronous transmission using dmac switching from sck pin function to port pin function: ? problem in operation: when switching the sck pin function to the output port function (high- level output) by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 13.23) sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3.c/ a = 0 2. te = 0 half-cycle low-level output figure 13.23 operation when switching from sck pin function to port pin function 13. serial communication interface rev.5.00 sep. 12, 2007 page 486 of 764 rej09b0396-0500 ? sample procedure for avoiding low-level output: as this sample procedure temporarily places the sck pin in the input state, the sck/por t pin should be pulled up beforehand with an external circuit. with ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, make the following settings in the order shown. 1. end of serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ a bit = 0 ... switchover to port output 5. cke1 bit = 0 sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 3.cke1 = 1 5.cke1 = 0 4.c/ a = 0 2.te = 0 hi g h-level output figure 13.24 operation when switching from sck pin function to port pin function (example of preventing low-level output) 14. smart card interface rev.5.00 sep. 12, 2007 page 487 of 764 rej09b0396-0500 section 14 smart card interface 14.1 overview an ic card (smart card) interface conforming to the iso/iec 7816-3 (identification card) standard is supported as an extension of th e serial communication in terface (sci) functions. switchover between the normal serial communicati on interface and the smart card interface is controlled by a register setting. 14.1.1 features features of the smart card interface supporte d by the h8/3067 group are listed below. ? asynchronous communication ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported ? built-in baud rate generator allows any bit rate to be selected ? three interrupt sources ? there are three interrupt sources ? transmit-data-empty, receive-data-full, and transmit/receive error ? that can issue requests independently. ? the transmit-data-empty interrupt and recei ve-data-full interrupt can activate the dma controller (dmac) to execute data transfer. 14. smart card interface rev.5.00 sep. 12, 2007 page 488 of 764 rej09b0396-0500 14.1.2 block diagram figure 14.1 shows a block diagram of the smart card interface. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate g enerator internal data bus rxd txd sck parity g eneration parity check clock external clock /4 /16 /64 txi rxi eri smr le g end: scmr: smart card mode re g ister rsr: receive shift re g ister rdr: receive data re g ister tsr: transmit shift re g ister tdr: transmit data re g ister smr: serial mode re g ister scr: serial control re g ister ssr: serial status re g ister brr: bit rate re g ister figure 14.1 block diagram of smart card interface 14.1.3 pin configuration table 14.1 shows the smart card interface pins. table 14.1 smart card interface pins pin name abbreviation i/o function serial clock pin sck i/o clock input/output receive data pin rxd input receive data input transmit data pin txd output transmit data output 14. smart card interface rev.5.00 sep. 12, 2007 page 489 of 764 rej09b0396-0500 14.1.4 register configuration the smart card interface has the internal registers listed in table 14.2. the brr, tdr, and rdr registers have their normal seri al communication interface functions , as described in section 13, serial communication interface. table 14.2 smart card interface registers channel address * 1 name abbreviation r/w initial value 0 h'fffb0 serial mode register smr r/w h'00 h'fffb1 bit rate register brr r/w h'ff h'fffb2 serial control register scr r/w h'00 h'fffb3 transmit data register tdr r/w h'ff h'fffb4 serial status register ssr r/(w) * 2 h'84 h'fffb5 receive data register rdr r h'00 h'fffb6 smart card mode register scmr r/w h'f2 1 h'fffb8 serial mode register smr r/w h'00 h'fffb9 bit rate register brr r/w h'ff h'fffba serial control register scr r/w h'00 h'fffbb transmit data register tdr r/w h'ff h'fffbc serial status register ssr r/(w) * 2 h'84 h'fffbd receive data register rdr r h'00 h'fffbe smart card mode register scmr r/w h'f2 2 h'fffc0 serial mode register smr r/w h'00 h'fffc1 bit rate register brr r/w h'ff h'fffc2 serial control register scr r/w h'00 h'fffc3 transmit data register tdr r/w h'ff h'fffc4 serial status register ssr r/(w) * 2 h'84 h'fffc5 receive data register rdr r h'00 h'fffc6 smart card mode register scmr r/w h'f2 notes: 1. lower 20 bits of the address in advanced mode. 2. only 0 can be written in bits 7 to 3, to clear the flags. 14. smart card interface rev.5.00 sep. 12, 2007 page 490 of 764 rej09b0396-0500 14.2 register descriptions this section describes the new or modified registers and bit functi ons in the smart card interface. 14.2.1 smart card mode register (scmr) scmr is an 8-bit readable/writable register that selects smart card interface functions. 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value read/write reserved bits reserved bit smart card interface mode select enables or disables the smart card interface function smart card data invert inverts data logic levels smart card data transfer direction selects the serial/parallel conversion format scmr is initialized to h'f2 by a reset and in standby mode. bits 7 to 4 ? reserved: read-only bits, always read as 1. bit 3 ? smart card data tran sfer direction (sdir): selects the serial/parallel conversion format.* 1 bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored lsb-first in rdr 1 tdr contents are transmitted msb-first receive data is stored msb-first in rdr 14. smart card interface rev.5.00 sep. 12, 2007 page 491 of 764 rej09b0396-0500 bit 2 ? smart card data invert (sinv): specifies inversion of the data logic level. this function is used in combination with the sdir bit to communicate with inverse-convention cards.* 2 the sinv bit does not affect the logic level of the parity bit. for parity settings, see section 14.3.4, register settings. bit 2 sinv description 0 unmodified tdr contents are transmitted (initial value) receive data is stored unmodified in rdr 1 inverted tdr contents are transmitted receive data is inverted before storage in rdr bit 1 ? reserved: read-only bit, always read as 1. bit 0 ? smart card interface mode select (smif): enables the smart car d interface function. bit 0 smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled notes: 1. the function for switching between lsb-first and msb-first mode can also be used with the normal serial communication inte rface. note that when the communication format data length is set to 7 bits and msb-first mode is selected for the serial data to be transferred, bit 0 of tdr is not transmitted, and only bits 7 to 1 of the received data are valid. 2. the data logic level inversion function can also be used with the normal serial communication interface. note th at, when inverting the serial data to be transferred, parity transmission and parity checking is based on the number of high-level periods at the serial data i/o pin, and not on the register value. 14. smart card interface rev.5.00 sep. 12, 2007 page 492 of 764 rej09b0396-0500 14.2.2 serial status register (ssr) the function of ssr bit 4 is modified in smart ca rd interface mode. this change also causes a modification to the setting conditions for bit 2 (tend). 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write transmit end status fla g indicatin g end of transmission error signal status (ers) status fla g indicatin g that an error si g nal has been received note: * only 0 can be written, to clear the fla g . bits 7 to 5: these bits operate as in normal serial co mmunication. for details see section 13.2.7, serial status register (ssr). bit 4 ? error signal status (ers): in smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device. the smart card interface does not detection framing errors. bit 4 ers description 0 indicates normal transmission, with no error signal returned (initial value) [clearing conditions] ? the chip is reset, or enters standby mode or module stop mode ? software reads ers while it is set to 1, then writes 0. 1 indicates that the receiving device sent an error signal reporting a parity error [setting condition] a low error signal was sampled. note: clearing the te bit to 0 in scr does not affect the ers flag, which retains its previous value. 14. smart card interface rev.5.00 sep. 12, 2007 page 493 of 764 rej09b0396-0500 bits 3 to 0: these bits operate as in normal serial co mmunication. for details see section 13.2.7, serial status register (ssr). the setting conditions for transmit end (tend, bit 2), however, are modified as follows. bit 2 tend description 0 transmission is in progress [clearing conditions] ? software reads tdre while it is set to 1, then writes 0 in the tdre flag. ? the dmac writes data in tdr. 1 end of transmission [setting conditions] (initial value) ? the chip is reset or enters standby mode. ? the te bit and fer/ers bit are both cleared to 0 in scr. ? tdre is 1 and ers is 0 at a time 2.5 etu after the last bit of a 1-byte serial character is transmitted (normal transmission). note: an etu (elementary time unit) is the time needed to transmit one bit. 14. smart card interface rev.5.00 sep. 12, 2007 page 494 of 764 rej09b0396-0500 14.2.3 serial mode register (smr) the function of smr bit 7 is modified in smart card interface mode. this change also causes a modification to the function of bits 1 and 0 in the serial control register (scr). 7 gm 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value read/write bit 7 ? gsm mode (gm): with the normal smart card interface, this bit is cleared to 0. setting this bit to 1 selects gsm mode, an additional mode for controlling the timing for setting the tend flag that indicates completion of transmission, and the type of clock output used. the details of the additional clock output control mode are specified by the cke1 and cke0 bits in the serial control register (scr). bit 7 gm description 0 normal smart card interface mode operation ? the tend flag is set 12.5 etu after the beginning of the start bit. ? clock output on/off control only. (initial value) 1 gsm mode smart card interface mode operation ? the tend flag is set 11.0 etu after the beginning of the start bit. ? clock output on/off and fixed-high/fixed-low control. bits 6 to 0: these bits operate as in normal serial co mmunication. for details see section 13.2.5, serial mode register (smr). 14.2.4 serial control register (scr) the function of scr bits 1 and 0 is modified in smart card interface mode. 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value read/write bits 7 to 2: these bits operate as in normal serial co mmunication. for details see section 13.2.6, serial control register (scr). 14. smart card interface rev.5.00 sep. 12, 2007 page 495 of 764 rej09b0396-0500 bits 1 and 0 ? clock enable 1 and 0 (cke1, cke0): these bits select the sci clock source and enable or disable clock output from the sck pin. in smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. bit 7 gm bit 1 cke1 bit 0 cke0 description 0 0 0 internal clock/sck pin is i/o port (initial value) 1 internal clock/sck pin is clock output 1 0 internal clock/sck pin is fixed at low output 1 internal clock/sck pin is clock output 1 0 internal clock/sck pin is fixed at high output 1 internal clock/sck pin is clock output 14.3 operation 14.3.1 overview the main features of the smar t card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for a1 etu period 10.5 etu after the start bit. ? if an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. ? only asynchronous communication is supported; there is no synchronous communication function. 14.3.2 pin connections figure 14.2 shows a pin connection diag ram for the smart card interface. in communication with a smart card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should both be connected to this line. the data transmission line should be pulled up to v cc with a resistor. 14. smart card interface rev.5.00 sep. 12, 2007 page 496 of 764 rej09b0396-0500 when the smart card uses the clock generated on the smart card interface, the sck pin output is input to the clk pin of the smart card. if the smart card uses an internal clock, this connection is unnecessary. the reset signal should be output from one of this lsi's generic ports. in addition to these pin connections, power and ground connections will normally also be necessary. txd rxd sck px (port) this chip v cc i/o data line clock line reset line clk rst card-processin g device smart card figure 14.2 smart card interface connection diagram note: if a smart card is not connected, and both te and re are set to 1, closed transmission/ reception is possible, enabling sel f-diagnosis to be carried out. 14.3.3 data format figure 14.3 shows the smart card interface data format . in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data. in transmission, the error signal is sampled and the same data is retransmitted if the error signal is low. 14. smart card interface rev.5.00 sep. 12, 2007 page 497 of 764 rej09b0396-0500 ds d0 d1 d2 d3 d4 d5 d6 d7 dp no parity error output from transmittin g device ds d0 d1 d2 d3 d4 d5 d6 d7 dp parity error output from transmittin g device de output from receivin g device le g end: ds: d0 to d7: data bits start bit parity bit error si g nal dp: de: figure 14.3 smart card interface data format the operating sequence is as follows. 1. when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. 2. the transmitting device starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). 3. with the smart card interface, the data line then retu rns to the high-impedance state. the data line is pulled high with a pull-up resistor. 4. the receiving device carries out a parity check . if there is no parity error and the data is received normally, the receiving device waits for r eception of the next data. if a parity error occurs, however, the receiving device outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving device places the signal line in the high-impedance state again. the signal line is pulled high again by a pull-up resistor. 5. if the transmitting device does not receive an er ror signal, it proceeds to transmit the next data frame. if it receives an error signal, however, it re turns to step 2 and transmits the same data again. 14. smart card interface rev.5.00 sep. 12, 2007 page 498 of 764 rej09b0396-0500 14.3.4 register settings table 14.3 shows a bit map of the registers used in the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described in this section. table 14.3 smart card int erface register settings bit register address * 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smr h'fffb0 gm 0 1 o/ e 1 0 cks1 cks0 brr h'fffb1 brr7 brr6 brr5 b rr4 brr3 brr2 brr1 brr0 scr h'fffb2 tie rie te re 0 0 cke1 * 2 cke0 tdr h'fffb3 tdr7 tdr6 tdr5 t dr4 tdr3 tdr2 tdr1 tdr0 ssr h'fffb4 tdre rdrf orer ers per tend 0 0 rdr h'fffb5 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scmr h'fffb6 ? ? ? ? sdir sinv ? smif notes: ? unused bit. 1. lower 20 bits of the address in advanced mode. 2. when gm is cleared to 0 in smr, the cke1 bit must also be cleared to 0. serial mode regist er (smr) settings: clear the gm bit to 0 when using the normal smart card interface mode, or set to 1 when using gsm mode. clear the o/ e bit to 0 if the smart card is of the direct convention type, or set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the built-in baud rate generator. see section 14.3.5, clock. bit rate register (brr) settings: brr is used to set the bit rate. see section 14.3.5, clock, for the method of calculating the value to be set. serial control register (scr) settings: the tie, rie, te, and re bits have their normal serial communication functions. see section 13, serial communication interface, for details. the cke1 and cke0 bits specify clock output. to disable clock output, clear these bits to 00; to enable clock output, set these bits to 01. clock output is not performed when the gm bit is set to 1 in smr. clock output can also be fixed low or high. smart card mode register (scmr) settings: clear both the sdir bit and sinv bit cleared to 0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention type. to use the smart card inte rface, set the smif bit to 1. 14. smart card interface rev.5.00 sep. 12, 2007 page 499 of 764 rej09b0396-0500 the register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention. 1. direct convention (sdir = sinv = o/ e = 0) ds d0 d1 d2 d3 d4 d5 d6 d7 dp azzazzzaaz (z) (z) state with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. in the example ab ove, the first character data is h'3b. the parity bit is 1, following the even parity rule designated for smart cards. 2. indirect convention (sdir = sinv = o/ e = 1) ds d7 d6 d5 d4 d3 d2 d1 d0 dp azzaaaaaaz (z) (z) state with the indirect convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in ms b-first order. in the example above, the first character data is h'3f. the par ity bit is 0, corresponding to state z, following the even parity rule designated for smart cards. in the h8/3067 group, inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in smr must be set to odd parity mode. this applies to both transmission and reception. 14.3.5 clock only an internal clock generated by the on-c hip baud rate generator can be used as the transmit/receive clock for the smart card interface. the bit rate is set with the bit rate register (brr) and the cks1 and cks0 bits in the serial mode register (smr). the equation for calculating the bit rate is shown below. table 14.5 shows some sample bit rates. if clock output is selected with cke0 set to 1, a clock with a frequency of 372 times the bit rate is output from the sck pin. b = 1488 2 2n?1 (n + 1) 10 6 14. smart card interface rev.5.00 sep. 12, 2007 page 500 of 764 rej09b0396-0500 where, n: brr setting (0 n 255) b: bit rate (bit/s) : operating frequency (mhz) n: see table 14.4 table 14.4 n-values of cks1 and cks0 settings n cks1 cks0 0 0 0 1 1 2 1 0 3 1 note: if the gear function is used to divide the clock frequency, use the divided frequency to calculate the bit rate. the equation above applies directly to 1/1 frequency division. table 14.5 bit rates (bits/s) for various brr settings (when n = 0) (mhz) n 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 26881.7 1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8 13440.9 2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5 8960.6 note: bit rates are rounded off to one decimal place. the following equation calculates the bit rate register (brr) setting from the operating frequency and bit rate. n is an integer from 0 to 255, specifying the value with the smaller error. n = 1488 2 2n?1 b 10 6 ? 1 table 14.6 brr settings for typical bit rates (bits/s) (when n = 0) (mhz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 bit/s n error n error n error n error n error n error n error n error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.66 14. smart card interface rev.5.00 sep. 12, 2007 page 501 of 764 rej09b0396-0500 table 14.7 maximum bit rates for various f requencies (smart ca rd interface mode) (mhz) maximum bit rate (bits/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 the bit rate error is given by the following equation: error ( % ) = 1488 2 2n-1 b (n + 1) 10 6 ? 1 100 14.3.6 transmitting and receiving data initialization: before transmitting or receiving data, the sm art card interface must be initialized as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. clear the te and re bits to 0 in the serial control register (scr). 2. clear error flags ers, per, and orer to 0 in the serial status register (ssr). 3. set the parity bit (o/ e ) and baud rate generator select bits (cks1 and cks0) in the serial mode register (smr). clear the c/ a , chr, and mp bits to 0, and set the stop and pe bits to 1. 4. set the smif, sdir, and sinv bits in the smart card mode register (scmr). when the smif bit is set to 1, the txd pin and rxd pin are both switched from port to sci pin functions and go to the high-impedance state. 5. set a value corresponding to the desired bit rate in the bit rate register (brr). 6. set the cke0 bit in scr. clear the tie, rie, te, re, mpie, teie, and cke1 bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis. 14. smart card interface rev.5.00 sep. 12, 2007 page 502 of 764 rej09b0396-0500 transmitting serial data: as data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal sci. figure 14.5 shows a sample transmission processing flowchart. 1. perform smart card interface mode initializa tion as described in initialization above. 2. check that the ers error fl ag is cleared to 0 in ssr. 3. repeat steps 2 and 3 until it can be confirmed that the tend flag is set to 1 in ssr. 4. write the transmit data in tdr, clear the tdre flag to 0, and perform the transmit operation. the tend flag is cleared to 0. 5. to continue transmitting data, go back to step 2. 6. to end transmission, clear the te bit to 0. the above processing may include interrupt handling dma transfer. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (txi) will be requested. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (eri) will be requested. the timing of tend flag setting depends on the gm bit in smr (see figure 14.4). if the txi interrupt activates the dmac, the number of bytes designated in the dmac can be transmitted automatically, including automatic retransmission. for details, see interrupt operations and da ta transfer by dmac in this section. serial data (1) gm = 0 tend (2) gm = 1 tend ds dp de guard time 11.0 etu 12.5 etu figure 14.4 timing of tend flag setting 14. smart card interface rev.5.00 sep. 12, 2007 page 503 of 764 rej09b0396-0500 initialization no yes clear te bit to 0 start transmittin g start no no no yes yes yes yes no end write transmit data in tdr, and clear tdre fla g to 0 in ssr error handlin g error handlin g tend = 1? all data transmitted? tend = 1? fer/ers = 0? fer/ers = 0? figure 14.5 sample transmission processing flowchart 14. smart card interface rev.5.00 sep. 12, 2007 page 504 of 764 rej09b0396-0500 1. data write tdr tsr (shift register) data 1 2. transfer from tdr to tsr data 1 data 1 data remains in tdr data 1 3. serial data output note: when the ers flag is set, it should be cleared until transfer of the last bit (d7 in lsb-first transmission, d0 in msb-first transmission) of the retransmit data to be transmitted next has been completed. in case of normal transmission: tend flag is set in case of transmit error: ers flag is set steps 2 and 3 above are repeated until the tend flag is set. i/o signal output data 1 figure 14.6 relation between transmit operation and internal registers i/o data when gm = 0 guard time de ds da db dc dd de df dg dh dp 12.5 etu 11.0 etu when gm = 1 txi (tend interrupt) figure 14.7 timing of tend flag setting receiving serial data: data reception in smart card mode uses the same processing procedure as for the normal sci. figure 14.8 shows a sample reception processing flowchart. 1. perform smart card interface mode initializa tion as described in initialization above. 2. check that the orer flag and per flag are cleared to 0 in ssr. if either is set, perform the appropriate receive error handling, then cl ear both the orer and the per flag to 0. 3. repeat steps 2 and 3 until it can be confirmed that the rdrf flag is set to 1. 4. read the receive data from rdr. 5. to continue receiving data, clear the rd rf flag to 0 and go back to step 2. 6. to end reception, clear the re bit to 0. 14. smart card interface rev.5.00 sep. 12, 2007 page 505 of 764 rej09b0396-0500 initialization read rdr and clear rdrf fla g to 0 in ssr clear re bit to 0 start receivin g start error handlin g no no no yes yes orer = 0 and per = 0? rdrf = 1? all data received? yes figure 14.8 sample recepti on processing flowchart the above procedure may include interrupt handling and dma transfer. if reception ends and the rdrf flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (rxi) w ill be requested. if an error occurs in reception and either the orer flag or the per flag is se t to 1, a transmit/receive-error interrupt (eri) will be requested. if the rxi interrupt activates the dmac, the number of bytes designated in the dmac will be transferred, skipping receive data in which an error occurred. for details, see interrupt operations and da ta transfer by dmac in this section. 14. smart card interface rev.5.00 sep. 12, 2007 page 506 of 764 rej09b0396-0500 if a parity error occurs during reception and the per flag is set to 1, the received data is transferred to rdr, so the erroneous data can be read. switching modes: when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing re to 0 and setting te to 1. the rdrf, per, or orer flag can be us ed to check that the receive operation has been completed. when switching from transmit mode to receive mode , first confirm that the transmit operation has been completed, then start from initialization, clearing te to 0 and setting re to 1. the tend flag can be used to ch eck that the transmit operation has been completed. fixing clock output: when the gm bit is set to 1 in smr, clock output can be fixed by means of the cke1 and cke0 bits in scr. the minimum clock pulse width can be set to the specified width in this case. figure 14.9 shows the timing for fixing clock output. in this example, gm = 1, cke1 = 0, and the cke0 bit is controlled. specified pulse width cke1 value sck specified pulse width scr write (cke0 = 1) scr write (cke0 = 0) figure 14.9 timing for fixing cock output interrupt operations: the smart card interface has three inte rrupt sources: transmit-data-empty (txi), transmit/receive-error (eri), and receive -data-full (rxi). the transmit-end interrupt request (tei) is not available in smart card mode. a txi interrupt is requested when the tend flag is set to 1 in ssr. an rxi interrupt is requested when the rdrf flag is set to 1 in ssr. an eri interrupt is requested when the orer, per, or ers flag is set to 1 in ssr. these relationships are shown in table 14.8. 14. smart card interface rev.5.00 sep. 12, 2007 page 507 of 764 rej09b0396-0500 table 14.8 smart card interface mode op erating states and interrupt sources operating state flag enable bit interrupt source dmac activation transmit mode normal operation tend tie txi available error ers rie eri not available receive mode normal operation rdrf rie rxi available error per, orer rie eri not available data transfer by dmac: the dmac can be used to transm it and receive data in smart card mode, as in normal sci operations. in transmit mode, when the tend flag is set to 1 in ssr, the tdre flag is set simultaneously, generating a txi interrupt. if the txi request is designated beforehand as a dmac activation source, the dm ac will be activated by the txi request and will transfer the next transmit data. this data transfer by the dmac automatically clears the tdre and tend flags to 0. in the event of an error, the sci automatically retransmits the same data, keeping the tend flag cleared to 0 so that the dmac is not activ ated. the sci and dmac will therefore automatically transmit the designated number of bytes, including retransmission when an error occurs. when an er ror occurs, the ers flag is not cleared automatically, so the rie bit should be set to 1 to enable the error to generate an eri request, and the eri interrupt handler should clear ers. when using the dmac to transmit or receive, fi rst set up and enable the dmac, then make sci settings. dmac settings are described in section 7, dma controller. in receive operations, an rxi interrupt is requested when the rdrf flag is set to 1 in ssr. if the rxi request is designated beforehand as a dmac activation source, the dmac will be activated by the rxi request and will transfer the receive d data. this data transfer by the dmac automatically clears the rd rf flag to 0. when an error occurs , the rdrf flag is not set and an error flag is set instead. the dmac is not activat ed. the eri interrupt request is directed to the cpu. the eri interrupt handler should clear the error flags. examples of operation in gsm mode: when switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. ? switching from smart card interface mode to software standby mode 1. set the p9 4 data register (dr) and data direction register (ddr) to the values for the fixed output state in software standby mode. 14. smart card interface rev.5.00 sep. 12, 2007 page 508 of 764 rej09b0396-0500 2. write 0 in the te and re bits in the serial control register (scr) to stop transmit/receive operations. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. 3. write 0 in the cke0 bit in scr to stop the clock. 4. wait for one serial clock cycle. during this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. write h'00 in the serial mode register (smr) and smart card mode register (scmr). 6. make the transition to the software standby state. ? returning from software standby mode to smart card interface mode 1 . clear the software standby state. 2 . set the cke1 bit in scr to the value for the fixed output state at the start of software standby (the current p9 4 pin state). 3 . set smart card interface mode and output the cloc k. clock signal generation is started with the normal duty cycle. software standby normal operation normal operation 1 2 3 4 5 6 1 2 3 figure 14.10 procedure for stopping and restarting the clock use the following procedure to secure the clock duty cycle after powering on. 1. the initial state is port input and high impedan ce. use pull-up or pull-down resistors to fix the potential. 2. fix at the output specified by the cke1 bit in scr. 3. set smr and scmr, and switch to smart card interface mode operation. 4. set the cke0 bit to 1 in scr to start clock output. 14. smart card interface rev.5.00 sep. 12, 2007 page 509 of 764 rej09b0396-0500 14.4 usage notes the following points should be noted when using the sci as a smart card interface. receive data sampling timing and receive margin in smart card interface mode: in smart card interface mode, the sci operates on a base cloc k with a frequency of 372 times the transfer rate. in reception, the sci synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the 186th ba se clock pulse. the timing is shown in figure 14.11. internal base clock 372 clocks 186 clocks receive data (rxd) synchronization samplin g timin g d0 d1 data samplin g timin g 185 371 0 371 185 0 0 start bit figure 14.11 receive data sampling ti ming in smart card interface mode the receive margin can theref ore be expressed as follows. receive margin in smart card interface mode: m = (0.5 ? 1 2n d ? 0.5 n ) ? (l ? 0.5) f ? (1 + f) 100 % m: receive margin ( % ) n: ratio of clock frequency to bit rate (n = 372) 14. smart card interface rev.5.00 sep. 12, 2007 page 510 of 764 rej09b0396-0500 d: clock duty cycle (d = 0 to 1.0) l: frame length (l =10) f: absolute deviation of clock frequency from the above equation, if f = 0 and d = 0.5, the receive margin is as follows. when d = 0.5 and f = 0: m = (0.5 ? 1/2 372) 100 % = 49.866 % retransmission: retransmission is performed by the sci in receive mode and transmit mode as described below. ? retransmission when sci is in receive mode figure 14.12 illustrates retransmission when the sci is in receive mode. 1. if an error is found when the received parity b it is checked, the per bit is automatically set to 1. if the rie bit in scr is set to the enable st ate, an eri interrupt is requested. the per bit should be cleared to 0 in ssr before the next parity bit sampling timing. 2. the rdrf bit in ssr is not set for the frame in which the error has occurred. 3. if no error is found when the received parity bit is checked, the per bit is not set to 1 in ssr. 4. if no error is found when the received parity b it is checked, the receive operation is assumed to have been completed normally, and the rdrf bit is automatically set to 1 in ssr. if the rie bit in scr is set to the enable state, an rxi in terrupt is requested. if rxi is enabled as a dma transfer activation source, the rdr contents can be read automati cally. when the dmac reads the rdr data, the rdrf flag is automatically cleared to 0. 5. when a normal frame is received, the data pin is held in the high-impe dance state at the error signal transmission timing. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds frame n+1 retransmitted frame frame n rdrf [1] per [2] [3] [4] figure 14.12 retransmission in sci receive mode 14. smart card interface rev.5.00 sep. 12, 2007 page 511 of 764 rej09b0396-0500 ? retransmission when sci is in transmit mode figure 14.13 illustrates retransmission when the sci is in transmit mode. 6. if an error signal is sent back from the r eceiving device after transmission of one frame is completed, the ers bit is set to 1 in ssr. if the rie bit in scr is set to the enable state, an eri interrupt is requested. the ers bit should be cleared to 0 in ssr before the next parity bit sampling timing. 7. the tend bit in ssr is not set for the frame for which the error signal was received. 8. if an error signal is not sent back from the receiving device, the ers flag is not set in ssr. 9. if an error signal is not sent back from the receiving device, transmission of one frame, including retransmission, is assumed to have been completed, and the tend bit is set to 1 in ssr. if the tie bit in scr is set to the enable state, a txi interrupt is requested. if txi is enabled as a dma transfer activation source, the next data can be written in tdr automatically. when the dmac writes data in tdr, the tdre bit is automatically cleared to 0. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds frame n+1 retransmitted frame frame n tdre tend [6] ers transfer from tdr to tsr transfer from tdr to tsr transfer from tdr to tsr [7] [9] [8] figure 14.13 retransmission in sci transmit mode note on block transfer mode support: the smart card interface inst alled in the h8/3006 and h8/3007 support an ic card (smart card) in terface with provision for iso/iec7816-3 t=0 (character transmission). therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data retransmission are not performed). 14. smart card interface rev.5.00 sep. 12, 2007 page 512 of 764 rej09b0396-0500 15. a/d converter rev.5.00 sep. 12, 2007 page 513 of 764 rej09b0396-0500 section 15 a/d converter 15.1 overview the h8/3006 and h8/3007 include a 10-bit succe ssive-approximations a/d converter with a selection of up to eight analog input channels. when the a/d converter is not used, it can be halted independently to conserve power. for details see section 19.6, module standby function. the h8/3006 and h8/3007 support 70/134-state conversion as a high-speed conversion mode. note that it differs in this respect from the h8/3048 group, which supports 134/266-state conversion. 15.1.1 features a/d converter features are listed below. ? 10-bit resolution ? eight input channels ? selectable analog conversion voltage range the analog voltage conversion range can be programmed by input of an analog reference voltage at the v ref pin. ? high-speed conversion conversion time: maximum 3.5 s per channel (with 20 mhz system clock) ? two conversion modes single mode: a/d conversion of one channel scan mode: continuous conversion on one to four channels ? four 16-bit data registers a/d conversion results are transferred for storage into data registers corresponding to the channels. ? sample-and-hold function ? three conversion start sources the a/d converter can be activated by software, an external trigger, or an 8-bit timer compare match. ? a/d interrupt requested at end of conversion at the end of a/d conversion, an a/d end interrupt (adi) can be requested. ? dma controller (dmac) activation the dmac can be activated at the end of a/d conversion. 15. a/d converter rev.5.00 sep. 12, 2007 page 514 of 764 rej09b0396-0500 15.1.2 block diagram figure 15.1 shows a block diagram of the a/d converter. module data bus bus interface on-chip data bus addra addrb addrc addrd adcsr adcr successive- approximations re g ister 10-bit d/a analo g multi- plexer sample-and- hold circuit comparator + ? control circuit /4 /8 adi interrupt si g nal av v av cc ref ss an an an an an an an an 0 1 2 3 4 5 6 7 le g end: adcr: adcsr: addra: addrb: addrc: addrd: a/d control re g ister a/d control/status re g ister a/d data re g ister a a/d data re g ister b a/d data re g ister c a/d data re g ister d adtrg adte compare match a0 8tcsr0 8-bit timer figure 15.1 a/d converter block diagram 15. a/d converter rev.5.00 sep. 12, 2007 page 515 of 764 rej09b0396-0500 15.1.3 pin configuration table 15.1 summarizes the a/d converter's input pins. the eight analog input pins are divided into two groups: group 0 (an 0 to an 3 ), and group 1 (an 4 to an 7 ). av cc and av ss are the power supply for the analog circuits in the a/d converter. v ref is the a/d conversion reference voltage. table 15.1 a/d converter pins pin name abbrevi- ation i/o function analog power supply pin av cc input analog power supply analog ground pin av ss input analog ground and reference voltage reference voltage pin v ref input analog reference voltage analog input pin 0 an 0 input group 0 analog inputs analog input pin 1 an 1 input analog input pin 2 an 2 input analog input pin 3 an 3 input analog input pin 4 an 4 input group 1 analog inputs analog input pin 5 an 5 input analog input pin 6 an 6 input analog input pin 7 an 7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion 15. a/d converter rev.5.00 sep. 12, 2007 page 516 of 764 rej09b0396-0500 15.1.4 register configuration table 15.2 summarizes the a/d converter's registers. table 15.2 a/d converter registers address * 1 name abbreviation r/w initial value h'fffe0 a/d data register ah addrah r h'00 h'fffe1 a/d data register al addral r h'00 h'fffe2 a/d data register bh addrbh r h'00 h'fffe3 a/d data register bl addrbl r h'00 h'fffe4 a/d data register ch addrch r h'00 h'fffe5 a/d data register cl addrcl r h'00 h'fffe6 a/d data register dh addrdh r h'00 h'fffe7 a/d data register dl addrdl r h'00 h'fffe8 a/d control/status register adcsr r/(w) * 2 h'00 h'fffe9 a/d control register adcr r/w h'7e notes: 1. lower 20 bits of the address in advanced mode. 2. only 0 can be written in bit 7, to clear the flag. 15.2 register descriptions 15.2.1 a/d data registers a to d (addra to addrd) bit addrn initial value 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r a/d conversion data 10-bit data giving an a/d conversion result reserved bits read/write (n = a to d) the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of the result are stored in the upper byte of the a/d data register. the lower 2 bits are stored in the lower byte. bits 5 to 0 of an a/d 15. a/d converter rev.5.00 sep. 12, 2007 page 517 of 764 rej09b0396-0500 data register are reserved bits that are always r ead as 0. table 15.3 indicates the pairings of analog input channels and a/d data registers. the cpu can always read the a/d data registers. the upper byte can be read directly, but the lower byte is read through a temporary register (temp). for details see section 15.3, cpu interface. the a/d data registers are initialized to h'0000 by a reset and in standby mode. table 15.3 analog input channels and a/d data registers analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd 15. a/d converter rev.5.00 sep. 12, 2007 page 518 of 764 rej09b0396-0500 15.2.2 a/d control/status register (adcsr) bit initial value read/write 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * note: only 0 can be written, to clear the fla g . * a/d end flag indicates end of a/d conversion a/d interrupt enable enables and disables a/d end interrupts a/d start starts or stops a/d conversion s c an mode selects sin g le mode or scan mode clo c k sele c t selects the a/d conversion time channel sele c t 2 to 0 these bits select analo g input channels adcsr is an 8-bit readable/writable register that selects the mode and controls the a/d converter. adcsr is initialized to h'00 by a reset and in standby mode. bit 7 ? a/d end flag (adf): indicates the end of a/d conversion. bit 7 adf description 0 [clearing conditions] (initial value) ? read adf when adf =1, then write 0 in adf. ? dmac activated by adi interrupt. 1 [setting conditions] ? single mode: a/d conversion ends ? scan mode: a/d conversion ends in all selected channels 15. a/d converter rev.5.00 sep. 12, 2007 page 519 of 764 rej09b0396-0500 bit 6 ? a/d interrupt enable (adie): enables or disables the inte rrupt (adi) requested at the end of a/d conversion. bit 6 adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled bit 5 ? a/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by external trigger input at the adtrg pin, or by an 8-bit timer compare match. bit 5 adst description 0 a/d conversion is stopped (initial value) 1 single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends. scan mode: a/d conversion starts and continues, cycling among the selected channels, until adst is cleared to 0 by software, by a reset, or by a transition to standby mode. bit 4 ? scan mode (scan): selects single mode or scan mode. for further information on operation in these modes, see section 15.4, operation. clear the adst bit to 0 before switching the conversion mode. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3 ? clock select (cks): selects the a/d conversion time. clear the adst bit to 0 before switching the conversion time. bit 3 cks description 0 conversion time = 134 states (maximum) (initial value) 1 conversion time = 70 states (maximum) 15. a/d converter rev.5.00 sep. 12, 2007 page 520 of 764 rej09b0396-0500 bits 2 to 0 ? channel select 2 to 0 (ch2 to ch0): these bits and the scan bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. group selection channel selection description ch2 ch1 ch0 single mode scan mode 0 0 0 an 0 (initial value) an 0 1 an 1 an 0 , an 1 1 0 an 2 an 0 to an 2 1 an 3 an 0 to an 3 1 0 0 an 4 an 4 1 an 5 an 4 , an 5 1 0 an 6 an 4 to an 6 1 an 7 an 4 to an 7 15.2.3 a/d control register (adcr) bit initial value read/write 7 trge 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 0 r/w 2 ? 1 ? 1 ? 1 ? trigger enable enables or disables starting of a/d conversion by an external trigger or 8-bit timer compare match reserved bits adcr is an 8-bit readable/writable register that enables or disables starting of a/d conversion by external trigger input or an 8-bit timer compare match signal. adcr is initialized to h'7e by a reset and in standby mode. 15. a/d converter rev.5.00 sep. 12, 2007 page 521 of 764 rej09b0396-0500 bit 7 ? trigger enable (trge): enables or disables starting of a/d conversion by an external trigger or 8-bit timer compare match. bit 7 trge description 0 starting of a/d conversion by an external trigger or 8-bit timer (initial value) compare match is disabled 1 a/d conversion is started at the falling edge of the external trigger signal ( adtrg ) or by an 8-bit timer compare match external trigger pin and 8-bit timer selection are performed by the 8-bit timer. for details, see section 10, 8-bit timers. bits 6 to 1 ? reserved: these bits cannot be modified and are always read as 1. bit 0 ? reserved: this bit can be read or written, but should not be set to 1. 15. a/d converter rev.5.00 sep. 12, 2007 page 522 of 764 rej09b0396-0500 15.3 cpu interface addra to addrd are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, although the upper byte can be be accesse d directly by the cpu, the lower byte is read through an 8-bit temporary register (temp). an a/d data register is read as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp conten ts are transferred to the cpu. when reading an a/d data register, always read th e upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 15.2 shows the data flow fo r access to an a/d data register. upper-byte read bus interface module data bus cpu (h'aa) addrnh (h'aa) addrnl (h'40) lower-byte read bus interface module data bus cpu (h'40) addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) note: n = a to d figure 15.2 a/d data register a ccess operation (r eading h'aa40) 15. a/d converter rev.5.00 sep. 12, 2007 page 523 of 764 rej09b0396-0500 15.4 operation the a/d converter operates by successive approxi mations with 10-bit resolution. it has two operating modes: single mode and scan mode. 15.4.1 single mode (scan = 0) single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. to clea r the adf flag to 0, first read adcsr, then write 0 in adf. when the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an 1 ) is selected in single mode are described next. figure 15.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an 1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 in the adf flag. 6. the routine reads and proce sses the conversion result (addrb). 7. execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated. 15. a/d converter rev.5.00 sep. 12, 2007 page 524 of 764 rej09b0396-0500 adie adst adf state of channel 0 (an ) set set set clear clear idle idle idle idle a/d conversion (1) a/d conversion (2) idle read conversion result a/d conversion result (1) read conversion result a/d conversion result (2) note: * vertical arrows ( ) indicate instructions executed by software. 0 1 2 3 a/d conversion starts * * * * * addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) idle figure 15.3 example of a/d converter operation (single mode, channel 1 selected) 15. a/d converter rev.5.00 sep. 12, 2007 page 525 of 764 rej09b0396-0500 15.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an 0 when ch2 = 0, an 4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an 1 or an 5 ) starts immediately. a/d convers ion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are tr ansferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selecti on must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, se t the adst bit to 1. a/d conve rsion will start again from the first channel in the group. the adst bit can be set at the same time as the mode or channel selection is changed. typical operations when three channels in group 0 (an 0 to an 2 ) are selected in scan mode are described next. figure 15.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), scan gro up 0 is selected (ch2 = 0), analog input channels an 0 to an 2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. when a/d conversion of the first channel (an 0 ) is completed, the result is transferred into addra. next, conversion of the second channel (an 1 ) starts automatically. 3. conversion proceeds in the same way through the third channel (an 2 ). 4. when conversion of all selected channels (an 0 to an 2 ) is completed, the adf flag is set to 1 and conversion of the first channel (an 0 ) starts again. if the adie bit is set to 1, an adi interrupt is requested at this time. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an 0 ). 15. a/d converter rev.5.00 sep. 12, 2007 page 526 of 764 rej09b0396-0500 adst adf state of channel 0 (an ) 0 1 2 3 continuous a/d conversion set clear * 1 clear * 1 idle a/d conversion (1) idle idle idle a/d conversion (4) idle a/d conversion (2) idle a/d conversion (5) idle a/d conversion (3) idle idle transfer a/d conversion result (1) a/d conversion result (4) a/d conversion result (2) a/d conversion result (3) 1. 2. a/d conversion time notes: * 2 * 1 addra addrb addrc addrd state of channel 1 (an ) state of channel 2 (an ) state of channel 3 (an ) vertical arrows ( ) indicate instructions executed by software. data currently bein g converted is i g nored. figure 15.4 example of a/d converter operation (scan mode, channels 3 an 0 to an 2 selected) 15. a/d converter rev.5.00 sep. 12, 2007 page 527 of 764 rej09b0396-0500 15.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 15.5 shows the a/d conversion timing. table 15.4 indicates the a/d conversion time. as indicated in figure 15.5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 15.4. in scan mode, the values given in table 15.4 apply to the first conversion. in the second and subsequent conversions the conversion time is fixed at 128 states when cks = 0 or 66 states when cks = 1. address bus write si g nal input samplin g timin g adf (1) (2) t d t spl t conv le g end: (1): (2): t : t : t : d spl conv adcsr write cycle adcsr address synchronization delay input samplin g time a/d conversion time figure 15.5 a/d conversion timing 15. a/d converter rev.5.00 sep. 12, 2007 page 528 of 764 rej09b0396-0500 table 15.4 a/d conversion time (single mode) cks = 0 cks = 1 symbol min typ max min typ max synchronization delay t d 6 ? 9 4 ? 5 input sampling time t spl ? 31 ? ? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: values in the table are numbers of states. 15.4.4 external trigger input timing a/d conversion can be externally triggered. when the trge bit is set to 1 in adcr and the 8-bit timer's adte bit is cleared to 0, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as if the adst bit had been set to 1 by software. figure 15.6 shows the timing. adtrg internal tri gg er si g nal adst a/d conversion figure 15.6 external trigger input timing 15.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. the adi interrupt request can be designated as a dmac activation source. in this case, an interrupt request is not sent to the cpu. 15. a/d converter rev.5.00 sep. 12, 2007 page 529 of 764 rej09b0396-0500 15.6 usage notes when using the a/d converter, note the following points: 1. analog input voltage range: during a/d conversion, the voltages input to the analog input pins should be in the range av ss an n v ref . 2. relationships of av cc and av ss to v cc and v ss : av cc , av ss , v cc , and v ss should be related as follows: av ss = v ss . av cc and av ss must not be left open, even if the a/d converter is not used. 3. v ref programming range: the reference voltage input at the v ref pin should be in the range v ref av cc . 4. note on board design: in board layout, separate the digital circuits from the analog circuits as much as possible. particularly avoid layouts in which the signal lines of digital circuits cross or closely approach the signal lines of analog circuits. induction and other effects may cause the analog circuits to operate incorrectly, or may a dversely affect the accuracy of a/d conversion. the analog input signals (an 0 to an 7 ), analog reference voltage (v ref ), and analog supply voltage (av cc ) must be separated from digital circuits by the analog ground (av ss ). the analog ground (av ss ) should be connected to a stable digital ground (v ss ) at one point on the board. 5. note on noise: to prevent damage from surges and other abnormal voltages at the analog input pins (an 0 to an 7 ) and analog reference voltage pin (v ref ), connect a protection circuit like the one in figure 15.7 between av cc and av ss . the bypass capacitors connected to av cc and v ref and the filter capacitors connected to an 0 to an 7 must be connected to av ss . if filter capacitors like the ones in figure 15.7 are conn ected, the voltage values input to the analog input pins (an 0 to an 7 ) will be smoothed, which may give rise to error. error can also occur if a/d conversion is frequently performed in scan mode so that the current that charges and discharges the capacitor in the sample-and-hold circuit of the a/d converter becomes greater than that input to the analog input pins via input impedance r in . the circuit constants should therefore be selected carefully. 15. a/d converter rev.5.00 sep. 12, 2007 page 530 of 764 rej09b0396-0500 av cc * 1 * 1 v ref an 0 to an 7 av ss notes: 1. 2. rin: input impedance rin * 2 100 0.1 f 0.01 f 10 f figure 15.7 example of analog input protection circuit table 15.5 analog input pin ratings item min max unit analog input capacitance ? 20 pf allowable signal-source impedance ? 10 * k note: * when conversion time 134 states, v cc = 4.0 v to 5.5 v and 13 mhz. for details see section 20, electrical characteristics. 20 pf to a/d converter an 0 to an 7 10 k figure 15.8 analog input pin equivalent circuit note: numeric values are appr oximate, except in table 15.5 15. a/d converter rev.5.00 sep. 12, 2007 page 531 of 764 rej09b0396-0500 6. a/d conversion accuracy definitions: a/d conversion accuracy in the h8/3006 and h8/3007 are defined as follows: ? resolution digital output code length of a/d converter ? offset error deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 15.10) ? full-scale error deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111 (figure 15.10) ? quantization error intrinsic error of the a/d converter; 1/2 lsb (figure 15.9) ? nonlinearity error deviation from ideal a/d conversion characteris tic in range from zero volts to full scale, exclusive of offset error, full-s cale error, and quantization error. ? absolute accuracy deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error. 15. a/d converter rev.5.00 sep. 12, 2007 page 532 of 764 rej09b0396-0500 111 110 101 100 011 010 001 000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs quantization error analo g input volta g e di g ital output ideal a/d conversion characteristic figure 15.9 a/d converter accuracy definitions (1) 15. a/d converter rev.5.00 sep. 12, 2007 page 533 of 764 rej09b0396-0500 fs offset error nonlinearity error actual a/d conversion characteristic analo g input volta g e di g ital output ideal a/d conversion characteristic full-scale error figure 15.10 a/d converter accuracy definitions (2) 7. allowable signal-source impedance: the analog inputs of the h8/3006 and h8/3007 are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 k . the reason for this rating is that it enables the input capacitor in the sample- and-hold circuit in the a/d converter to charge within the sampling time. if the sensor output impedance exceeds 10 k , charging may be inadequate and the accuracy of a/d conversion cannot be guaranteed. if a large external capacitor is provided in single mode, then the internal 10-k input resistance becomes the only significant load on th e input. in this case the impedance of the signal source is not a problem. a large external capacitor, however, acts as a low-pass filter. this may make it impossible to track analog signals with high dv/dt (e.g. a variation of 5 mv/ s) (figure 15.11). to convert high-speed analog signals or to use scan mode, insert a low-impedance buffer. 15. a/d converter rev.5.00 sep. 12, 2007 page 534 of 764 rej09b0396-0500 8. effect on absolute accuracy: attaching an ex ternal capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy . the capacitor must be connected to an electrically stable ground, such as av ss . if a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. equivalent circuit of a/d converter h8/3006 and h8/3007 20 pf cin = 15 pf 10 k up to 10 k low-pass filter c up to 0.1 f sensor output impedance sensor input figure 15.11 analog input circuit (example) 16. d/a converter rev.5.00 sep. 12, 2007 page 535 of 764 rej09b0396-0500 section 16 d/a converter 16.1 overview the h8/3006 and h8/3007 include a d/a converter with two channels. 16.1.1 features d/a converter features are listed below. ? eight-bit resolution ? two output channels ? conversion time: maximum 10 s (with 20-pf capacitive load) ? output voltage: 0 v to v ref ? d/a outputs can be sustained in software standby mode 16. d/a converter rev.5.00 sep. 12, 2007 page 536 of 764 rej09b0396-0500 16.1.2 block diagram figure 16.1 shows a block diagram of the d/a converter. dadr0 dadr1 dacr dastcr v av da da av ref cc ss 0 1 le g end: dacr: dadr0: dadr1: dastcr: 8-bit d/a module data bus bus interface on-chip data bus control circuit d/a control re g ister d/a data re g ister 0 d/a data re g ister 1 d/a standby control re g ister figure 16.1 d/a converter block diagram 16.1.3 pin configuration table 16.1 summarizes the d/a converter's input and output pins. table 16.1 d/a converter pins pin name abbreviation i/o function analog power supply pin av cc input analog power supply and reference voltage analog ground pin av ss input analog ground and reference voltage analog output pin 0 da 0 output analog output, channel 0 analog output pin 1 da 1 output analog output, channel 1 reference voltage input pin v ref input analog reference voltage 16. d/a converter rev.5.00 sep. 12, 2007 page 537 of 764 rej09b0396-0500 16.1.4 register configuration table 16.2 summarizes the d/a converter's registers. table 16.2 d/a converter registers address * name abbreviation r/w initial value h'fff9c d/a data register 0 dadr0 r/w h'00 h'fff9d d/a data register 1 dadr1 r/w h'00 h'fff9e d/a control register dacr r/w h'1f h'ee01a d/a standby control register dastcr r/w h'fe note: * lower 20 bits of the address in advanced mode. 16.2 register descriptions 16.2.1 d/a data registers 0 and 1 (dadr0/1) bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w the d/a data registers (dadr0 and dadr1) are 8-b it readable/writable registers that store the data to be converted. when analog output is enabled, the d/a data register values are constantly converted and output at the analog output pins. the d/a data registers are initialized to h'00 by a reset and in standby mode. when the daste bit is set to 1 in the d/a standby control register (dastcr), the d/a registers are not initialized in software standby mode. 16. d/a converter rev.5.00 sep. 12, 2007 page 538 of 764 rej09b0396-0500 16.2.2 d/a control register (dacr) bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? d/a output enable 1 d/a output enable 0 d/a enable controls d/a conversion and analog output controls d/a conversion and analog output controls d/a conversion dacr is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset and in standby mode. when the daste bit is set to 1 in dastcr, the dacr is not initialized in software standby mode. bit 7 ? d/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7 daoe1 description 0 da 1 analog output is disabled 1 channel-1 d/a conversion and da 1 analog output are enabled bit 6 ? d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6 daoe0 description 0 da 0 analog output is disabled 1 channel-0 d/a conversion and da 0 analog output are enabled 16. d/a converter rev.5.00 sep. 12, 2007 page 539 of 764 rej09b0396-0500 bit 5 ? d/a enable (dae): controls d/a convers ion, together with bits daoe0 and daoe1. when the dae bit is cleared to 0, analog conversion is controlled independently in channels 0 and 1. when the dae bit is set to 1, analog conversion is controlled together in channels 0 and 1. output of the conversion results is always controlled independently by daoe0 and daoe1. bit 7 daoe1 bit 6 daoe0 bit 5 dae description 0 0 ? d/a conversion is disabled in channels 0 and 1 1 0 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 1 d/a conversion is enabled in channels 0 and 1 1 0 0 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 1 d/a conversion is enabled in channels 0 and 1 1 ? d/a conversion is enabled in channels 0 and 1 when the dae bit is set to 1, even if bits daoe0 and daoe1 in dacr and the adst bit in adcsr are cleared to 0, the same current is drawn from the analog power supply as during a/d and d/a conversion. bits 4 to 0 ? reserved: these bits cannot be modified and are always read as 1. 16.2.3 d/a standby control register (dastcr) dastcr is an 8-bit readable/writable register th at enables or disables d/a output in software standby mode. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 daste 0 r/w 2 ? 1 ? 1 ? 1 ? reserved bits d/a standby enable enables or disables d/a output in software standby mode dastcr is initialized to h'fe by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 1 ? reserved: these bits cannot be modified and are always read as 1. 16. d/a converter rev.5.00 sep. 12, 2007 page 540 of 764 rej09b0396-0500 bit 0 ? d/a standby enable (daste): enables or disables d/a output in software standby mode. bit 0 daste description 0 d/a output is disabled in software standby mode (initial value) 1 d/a output is enabled in software standby mode 16.3 operation the d/a converter has two built-in d/a convers ion circuits that can perform conversion independently. d/a conversion is performed constantly while enabled in dacr. if the dadr0 or dadr1 value is modified, conversion of the new data begins immediately. the conversion results are output when bits daoe0 and daoe1 are set to 1. an example of d/a conversion on channel 0 is given next. timing is indicated in figure 16.2. 1. data to be converted is written in dadr0. 2. bit daoe0 is set to 1 in dacr. d/a conversi on starts and da0 becomes an output pin. the converted result is output after the conversion time. v re f the o u tp u t val u e i s dadr c ontent s 256 output of this conversion result continues until the value in dadr0 is modified or the daoe0 bit is cleared to 0. 3. if the dadr0 value is modified, conversion star ts immediately, and the result is output after the conversion time. 4. when the daoe0 bit is cleared to 0, da0 becomes an input pin. 16. d/a converter rev.5.00 sep. 12, 2007 page 541 of 764 rej09b0396-0500 dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle address dadr0 daoe0 da 0 conversion data 1 conversion data 2 hi g h-impedance state conversion result 1 conversion result 2 t dconv t dconv le g end: t : d/a conversion time dconv figure 16.2 example of d/a converter operation 16.4 d/a output control in the h8/3006 and h8/3007, d/a converter output can be enabled or disabled in software standby mode. when the daste bit is set to 1 in dastcr, d/a converter output is enabled in software standby mode. the d/a converter registers retain the values they held prior to th e transition to software standby mode. when d/a output is enabled in software standby mode, the reference supply current is the same as during normal operation. 16. d/a converter rev.5.00 sep. 12, 2007 page 542 of 764 rej09b0396-0500 17. ram rev.5.00 sep. 12, 2007 page 543 of 764 rej09b0396-0500 section 17 ram 17.1 overview the h8/3007 has 4 kbytes of high-speed static ram on-chip. the h8/3006 has 2 kbytes. the ram is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in two states, making the ram useful for rapid data transfer. the on-chip ram of the h8/3007 is assigned to a ddresses h'fef20 to h'fff1f in modes 1 and 2, and to addresses h'ffef20 to h'ffff1f in modes 3 and 4. the on-chip ram of the h8/3006 are assigned to addresses h'ff720 to h'fff1f in m odes 1 and 2, and to addresses h'fff720 to h'ffff1f in modes 3 and 4. the ram enable bit (rame) in the system control register (syscr) can enable or disable the on-chip ram. 17.1.1 block diagram figure 17.1 shows a block diagram of the on-chip ram. h'fef20 * h'fef22 * h'fff1e * h'fef21 * h'fef23 * h'fff1f * on-chip data bus (upper 8 bits) on-chip data bus (lower 8 bits) bus interface syscr on-chip ram even addresses odd addresses le g end: syscr: system control re g ister note: * this example is of the h8/3007 operatin g in mode 1 and 2. the lower 20 bits of the address are shown. figure 17.1 ram block diagram 17. ram rev.5.00 sep. 12, 2007 page 544 of 764 rej09b0396-0500 17.1.2 register configuration the on-chip ram is controlled by syscr. table 17.1 gives the address and initial value of syscr. table 17.1 system control register address * name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 note: * lower 20 bits of the address in advanced mode. 17.2 system control register (syscr) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w 0 rame 1 r/w software standby standby timer select 2 to 0 user bit enable nmi edge select software standby output port enable ram enable bit enables or disables on-chip ram one function of syscr is to enable or disabl e access to the on-chip ram. the on-chip ram is enabled or disabled by the rame bit in syscr. for details about the other bits, see section 3.3, system control register (syscr). 17. ram rev.5.00 sep. 12, 2007 page 545 of 764 rej09b0396-0500 bit 0 ? ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized at the rising e dge of the input at the res pin. it is not initialized in software standby mode. bit 0 rame des c ription 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 17.3 operation when the rame bit is set to 1, the on-chip ram is enabled. accesses to addresses h'fef20 to h'fff1f in the h8/3007 in modes 1 and 2, a nd to addresses h'ffef20 to h'ffff1f in the h8/3007 in modes 3 and 4, are directed to th e on-chip ram. in the h8/3006, accesses to addresses h'ff720 to h'fff1f in modes 1 and 2, to addresses h'fff720 to h'ffff1f in modes 3 and 4, are directed to the on-chip ram. in modes 1 to 4, when the rame bit is cleared to 0, the off-chip address space is accessed. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written and read by word access. it can also be written and read by byte access. byte data is accessed in two states using the upper 8 bits of the data bus. word data starting at an even address is accessed in two states using all 16 bits of the data bus. 17. ram rev.5.00 sep. 12, 2007 page 546 of 764 rej09b0396-0500 18. clock pulse generator rev.5.00 sep. 12, 2007 page 547 of 764 rej09b0396-0500 section 18 clock pulse generator 18.1 overview the h8/3006 and h8/3007 have a built-in clock puls e generator (cpg) that generates the system clock ( ) and other internal clock signals ( /2 to /4096). after duty adjustment, a frequency divider divides the clock frequency to generate the system clock ( ). the system clock is output at the pin* 1 and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules. frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by settings in a division control register (divcr)* 2 . power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. notes: 1. usage of the pin differs depending on the chip operating mode and the pstop bit setting in the module standby control register (mstcr). for details, see section 19.7, system clock output disabling function. 2. the division ratio of the frequency divider can be changed dynamically during operation. the clock output at the pin also changes when the division ratio is changed. the frequency output at the pin is shown below. = extal n where, extal:frequency of crystal resonator or external clock signal n: frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8) 18.1.1 block diagram figure 18.1 shows a block diagram of the clock pulse generator. xtal extal cpg ? /2 to /4096 oscillator duty adjustment circuit frequency divider division control re g ister prescalers data bus figure 18.1 block diagram of clock pulse generator 18. clock pulse generator rev.5.00 sep. 12, 2007 page 548 of 764 rej09b0396-0500 18.2 oscillator circuit clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 18.2.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as in the example in figure 18.2. the damping resistance rd should be selected according to table 18.1. an at-cut parallel- resonance crystal should be used. extal xtal c c c = c = 10 pf to 22 pf l1 l2 l1 l2 rd figure 18.2 connection of crystal resonator (example) table 18.1 damping resistance value frequency f (mhz) damping resistance value 2 2 < f 4 4 < f 8 8 < f 10 10 < f 13 13 < f 16 16 < f 18 18 < f 20 rd ( ) 1 k 500 200 0 0 0 0 0 note: a crystal resonator between 2 mhz and 20 mhz can be used. if the chip is to be operated at less than 2 mhz, the on-chip frequency divider should be used. (a crystal resonator of less than 2 mhz cannot be used.) crystal resonator: figure 18.3 shows an equivalent circuit of the crystal resonator. the crystal resonator should have the characteristics listed in table 18.2. 18. clock pulse generator rev.5.00 sep. 12, 2007 page 549 of 764 rej09b0396-0500 xtal lrs c l c 0 extal at-cut parallel-resonance type figure 18.3 crystal resonator equivalent circuit table 18.2 crystal resonator parameters frequency (mhz) 2 4 8 10 12 16 18 20 rs max ( ) 500 120 80 70 60 50 40 40 co (pf) 7 pf max use a crystal resonator with a frequency equal to the system clock frequency ( ). notes on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from th e oscillator circuit to prevent induction from interfering with correct oscillation. see figure 18.4. when the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the xtal and extal pins. xtal extal c l2 c l1 h8/3006 and h8/3007 avoid si g nal a si g nal b figure 18.4 example of incorrect board design 18. clock pulse generator rev.5.00 sep. 12, 2007 page 550 of 764 rej09b0396-0500 18.2.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 18.5. if the xtal pin is left open, the stray ca pacitance should not exceed 10 pf. if the stray capacitance at the xtal pin exceeds 10 pf, use conf iguration b instead and hold the clock high in standby mode. extal xtal extal xtal external clock input open external clock input a. xtal pin left open b. complementary clock input at xtal pin figure 18.5 external clock input (examples) external clock: the external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. table 18.3 shows the clock timing, figure 18.6 shows the external clock input tim ing, and figure 18.7 shows th e external clock output settling delay timing. when the appropriate external clock is input via the extal pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. when the appropriate external clock is input via the extal pin, its waveform is corrected by the on-chip oscillator and duty adjustment circuit. the resulting stable clock is output to external devices after the external clock settling time (t dext ) has passed after the clock input. the system must remain reset with the reset signal low during t dext , while the clock output is unstable. 18. clock pulse generator rev.5.00 sep. 12, 2007 page 551 of 764 rej09b0396-0500 table 18.3 clock timing v cc = 2.7 v to 5.5 v v cc = 3.0 v to 5.5 v v cc = 5.0 v 10 % item symbol min max min max min max unit test conditions external clock input low pulse width t exl 40 ? 30 ? 15 ? ns figure 18.6 external clock input high pulse width t exh 40 ? 30 ? 15 ? ns external clock rise time t exr ? 10 ? 8 ? 5 ns external clock fall time t exf ? 10 ? 8 ? 5 ns t cl 0.4 0.6 0.4 0.6 0.4 0.6 t cyc 5 mhz clock low pulse width 80 ? 80 ? 80 ? ns < 5 mhz figure 20.3 t ch 0.4 0.6 0.4 0.6 0.4 0.6 t cyc 5 mhz clock high pulse width 80 ? 80 ? 80 ? ns < 5 mhz external clock output settling delay time t dext * 500 ? 500 ? 500 ? s figure 18.7 note: * t dext includes a 10 t cyc of res pulse width (t resw ). extal t exr t exf v cc 0.7 0.3 v t exh t exl v cc 0.5 figure 18.6 external clock input timing 18. clock pulse generator rev.5.00 sep. 12, 2007 page 552 of 764 rej09b0396-0500 v cc stby extal (internal or external) res t dext * note: * t dext includes a 10 t cyc res pulse width (t resw ). v ih figure 18.7 external clock output settling delay timing 18.3 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate . 18.4 prescalers the prescalers divide the system clock ( ) to generate internal clocks ( /2 to /4096). 18.5 frequency divider the frequency divider divides the duty-adjusted clock signal to generate the system clock ( ). the frequency division ratio can be changed dynamically by modifying the value in divcr, as described below. power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. the system clock generate d by the frequency divider can be output at the pin. 18. clock pulse generator rev.5.00 sep. 12, 2007 page 553 of 764 rej09b0396-0500 18.5.1 register configuration table 18.4 summarizes the frequency division register. table 18.4 frequency division register address * name abbreviation r/w initial value h'ee01b division control register divcr r/w h'fc note: * lower 20 bits of the address in advanced mode. 18.5.2 division control register (divcr) divcr is an 8-bit readable/writable register that selects the division ratio of the frequency divider. bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 div0 0 r/w 2 ? 1 ? 1 div1 0 r/w reserved bits divide bits 1 and 0 these bits select the frequency division ratio divcr is initialized to h'fc by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 2 ? reserved: these bits cannot be modified and are always read as 1. bits 1 and 0 ? divide (div1, div0): these bits select the frequency division ratio, as follows. bit 1 div1 bit 0 div0 frequency division ratio 0 0 1/1 (initial value) 1 1/2 1 0 1/4 1 1/8 18. clock pulse generator rev.5.00 sep. 12, 2007 page 554 of 764 rej09b0396-0500 18.5.3 usage notes the divcr setting changes the frequency, so note the following points. ? select a frequency division ratio that stays within the assured operation range specified for the clock cycle time t cyc in the ac electrical characteristics. set min to the lower limit of the operating frequency range, and ensure that does not fall below this lower limit. ? all on-chip module operations are based on . note that the timing of timer operations, serial communication, and other time-dependent processing differs before and after any change in the division ratio. the waiting tim e for exit from software standby mode also changes when the division ratio is changed. for details, see section 19.4.3, selection of waiting time for exit from software standby mode. 19 . power-down state rev.5.00 sep. 12, 2007 page 555 of 764 rej09b0396-0500 section 19 power-down state 19.1 overview the h8/3006 and h8/3007 have a power-down state that greatly reduces power consumption by halting the cpu, and a module standby function that reduces power consumption by selectively halting on-chip modules. the power-down state includes the following three modes: ? sleep mode ? software standby mode ? hardware standby mode the module standby function can halt on-chip supporting modules independently of the power- down state. the modules that can be halted are the 16-bit timer, 8-bit timer, sci0, sci1, sci2, dmac, dram interface, and a/d converter. table 19.1 indicates the methods of entering and exiting the power-down modes and module standby mode, and gives the status of the cpu and on-chip supporting modules in each mode. 19. power-down state rev.5.00 sep. 12, 2007 page 556 of 764 rej09b0396-0500 table 19.1 power-down state and module standby function clock active halted halted active exiting conditions ? interrupt ? res ? stby ? nmi ? irq 0 to irq 2 ? res ? stby ? stby ? res ? stby ? res ? clear mstcr bit to 0 * 5 i/o ports held held hi g h impedance ? clock output output hi g h output hi g h impedance hi g h impedance * 2 ram held held held * 3 ? other modules active halted and reset halted and reset active dram interface active halted and held * 1 halted and reset halted * 2 and held * 1 dmac active halted and reset halted and reset halted * 2 and reset cpu registers held held undeter- mined ? cpu halted halted halted active entering conditions sleep instruc- tion executed while ssby = 0 in syscr sleep instruc- tion executed while ssby = 1 in syscr low input at stby pin correspondin g bit set to 1 in mstcrh and mstcrl sleep mode software standby mode hardware standby mode module standby 16-bit timer active halted and reset halted and reset halted * 2 and reset 8-bit timer active halted and reset halted and reset halted * 2 and reset sci0 active halted and reset halted and reset halted * 2 and reset sci1 active halted and reset halted and reset halted * 2 and reset sci2 active halted and reset halted and reset halted * 2 and reset a/d active halted and reset halted and reset halted * 2 and reset state notes: 1. rtcnt and bits 7 and 6 of rtmcsr are initialized. other bits and re g isters hold their previous states. 2. state in which the correspondin g mstcr bit was set to 1. for details see section 19.2.2, module standby control re g ister h (mstcrh) and section 19.2.3, module standby control re g ister l (mstcrl). 3. the rame bit must be cleared to 0 in syscr before the transition from the pro g ram execution state to hardware standby mode. 4. when p6 7 is used as the output pin. 5. when a mstcr bit is set to 1, the re g isters of the correspondin g on-chip supportin g module are initialized. to restart the module, first clear the mstcr bit to 0, then set up the module re g isters a g ain. le g end: syscr: system control re g ister ssby: software standby bit mstcrh: module standby control re g ister h mstcrl: module standby control re g ister l * 4 mode/ function 19 . power-down state rev.5.00 sep. 12, 2007 page 557 of 764 rej09b0396-0500 19.2 register configuration the h8/3006 and h8/3007 have a system control register (syscr) that controls the power-down state, and module standby control registers h (mstcrh) and l (mstcrl) that control the module standby function. table 19.2 summarizes these registers. table 19.2 control register address * name abbreviation r/w initial value h'ee012 system control register syscr r/w h'09 h'ee01c module standby control register h mstcrh r/w h'78 h'ee01d module standby control register l mstcrl r/w h'00 note: * lower 20 bits of the address in advanced mode. 19.2.1 system control register (syscr) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ue 1 r/w 0 rame 1 r/w 2 nmieg 0 r/w 1 ssoe 0 r/w software standby enables transition to software standby mode ram enable standby timer select 2 to 0 these bits select the waitin g time of the cpu and peripheral functions user bit enable nmi edge select software standby output port enable syscr is an 8-bit readable/writable register. bit 7 (ssby), bits 6 to 4 (sts2 to sts0), and bit 1 (ssoe) control the power-down state. for information on the other syscr bits, see section 3.3, system control register (syscr). 19. power-down state rev.5.00 sep. 12, 2007 page 558 of 764 rej09b0396-0500 bit 7?software standby (ssby): enables transition to software standby mode. when software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. to clear this bit, write 0. bit 7 ssby des c ription 0 sleep instruction causes transition to sleep mode (initial value) 1 sleep instruction causes transition to software standby mode bits 6 to 4?standby timer select (sts2 to sts0): these bits select the length of time the cpu and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. if the cl ock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). see table 19.3. if an external clock is used, any setting is permitted. bit 6 sts2 bit 5 sts1 bit 4 sts0 des c ription 0 0 0 waiting time = 8,192 states (initial value) 1 waiting time = 16,384 states 1 0 waiting time = 32,768 states 1 waiting time = 65,536 states 1 0 0 waiting time = 131,072 states 1 waiting time = 262,144 states 1 0 waiting time = 1,024 states 1 illegal setting bit 1?software standby output port enable (ssoe): specifies whether the address bus and bus control signals ( cs 0 to cs 7 , as , rd , hwr , lwr , ucas , lcas , and rfsh ) are kept as outputs or fixed hi gh, or placed in the high-impedan ce state in software standby mode. bit 1 ssoe des c ription 0 in software standby mode, the address bus and bus control signals are all high-impedance (initial value) 1 in software standby mode, the address bus retains its output state and bus control signals are fixed high 19 . power-down state rev.5.00 sep. 12, 2007 page 559 of 764 rej09b0396-0500 19.2.2 module standby control register h (mstcrh) mstcrh is an 8-bit readable/w ritable register that controls output of the system clock ( ). it also controls the module standby function, which places individual on-chip s upporting modules in the standby state. module standby can be designated for the sci0, sci1, sci2. bit initial value read/write 7 pstop 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 mstph0 0 r/w 2 mstph2 0 r/w 1 mstph1 0 r/w c lo c k stop enables or disables output of the system clock module standby h2 to 0 these bits select modules to be placed in standby reserved bit mstcrh is initialized to h'78 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock stop (pstop): enables or disables output of the system clock ( ). bit 1 pstop des c ription 0 system clock output is enabled (initial value) 1 system clock output is disabled bits 6 to 3?reserved: these bits cannot be modified and are always read as 1. bit 2?module standby h2 (mstph2): selects whether to place the sci2 in standby. bit 2 mstph2 des c ription 0 sci2 operates normally (initial value) 1 sci2 is in standby state 19. power-down state rev.5.00 sep. 12, 2007 page 560 of 764 rej09b0396-0500 bit 1?module standby h1 (mstph1): selects whether to place the sci1 in standby. bit 1 mstph1 des c ription 0 sci1 operates normally (initial value) 1 sci1 is in standby state bit 0?module standby h0 (mstph0): selects whether to place the sci0 in standby. bit 0 mstph0 des c ription 0 sci0 operates normally (initial value) 1 sci0 is in standby state 19.2.3 module standby control register l (mstcrl) mstcrl is an 8-bit readable/writable register that controls the module standby function, which places individual on-chi p supporting modules in the stan dby state. module standby can be designated for the dmac, 16-bit timer, dram inte rface, 8-bit timer, and a/d converter modules. 2 mstpl2 0 r/w 1 ? 0 r/w 0 mstpl0 0 r/w reserved bits module standby l7, l5 to l2, l0 these bits select modules to be placed in standby bit initial value read/write 7 mstpl7 0 r/w 6 ? 0 r/w 5 mstpl5 0 r/w 4 mstpl4 0 r/w 3 mstpl3 0 r/w mstcrl is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 19 . power-down state rev.5.00 sep. 12, 2007 page 561 of 764 rej09b0396-0500 bit 7?module standby l7 (mstpl7): selects whether to place the dmac in standby. bit 7 mstpl7 des c ription 0 dmac operates normally (initial value) 1 dmac is in standby state bit 6?reserved: this bit can be written and read. bit 5?module standby l5 (mstpl5): selects whether to pl ace the dram interface in standby. bit 5 mstpl5 des c ription 0 dram interface operates normally (initial value) 1 dram interface is in standby state bit 4?module standby l4 (mstpl4): selects whether to place th e 16-bit timer in standby. bit 4 mstpl4 des c ription 0 16-bit timer operates normally (initial value) 1 16-bit timer is in standby state bit 3?module standby l3 (mstpl3): selects whether to place 8-bit timer channels 0 and 1 in standby. bit 3 mstpl3 des c ription 0 8-bit timer channels 0 and 1 operate normally (initial value) 1 8-bit timer channels 0 and 1 are in standby state bit 2?module standby l2 (mstpl2): selects whether to place 8-bit timer channels 2 and 3 in standby. bit 2 mstpl2 des c ription 0 8-bit timer channels 2 and 3 operate normally (initial value) 1 8-bit timer channels 2 and 3 are in standby state 19. power-down state rev.5.00 sep. 12, 2007 page 562 of 764 rej09b0396-0500 bit 1?reserved: this bit can be written and read. bit 0?module standby l0 (mstpl0): selects whether to place th e a/d converter in standby. bit 0 mstpl0 des c ription 0 a/d converter operates normally (initial value) 1 a/d converter is in standby state 19.3 sleep mode 19.3.1 transition to sleep mode when the ssby bit is cleared to 0 in syscr, execution of the sleep instruction causes a transition from the program execution state to sleep mode. immediately after executing the sleep instruction the cpu halts, but the contents of its internal registers are retained. the dma controller (dmac), dram interface, and on-chip supporting modules do not halt in sleep mode. modules which have been placed in standby by the module standby function, however, remain halted. 19.3.2 exit from sleep mode sleep mode is exited by an interrupt, or by input at the res or stby pin. exit by interrupt: an interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. sleep mode is not exited by an interrupt other than nmi if the interrupt is masked by interrupt priority settings and the settings of the i and ui bits in ccr, ipr. exit by res input: low input at the res pin exits from sleep mode to the reset state. exit by stby input: low input at the stby pin exits from sleep mode to hardware standby mode. 19 . power-down state rev.5.00 sep. 12, 2007 page 563 of 764 rej09b0396-0500 19.4 software standby mode 19.4.1 transition to software standby mode to enter software standby mode, execute the sleep instruction while the ssb y bit is set to 1 in syscr. in software standby mode, current dissipation is reduced to an extremel y low level because the cpu, clock, and on-chip supporting modules all halt. the dmac and on-chip supporting modules are reset and halted. as long as the specified voltage is supplied, however, cpu register contents and on-chip ram data are retained. the settings of the i/o ports and dram interface * are also held. when the wdt is used as a watchdog timer (wt/ it = 1), the tme bit must be cleared to 0 before setting ssby. also, when setting tme to 1, ssby should be cleared to 0. clear the brle bit in brcr (inhibiting bus release) before making a transition to software standby mode. note: * rtcnt and bits 7 and 6 of rtmcsr are initialized. other bits and registers hold their previous states. 19.4.2 exit from software standby mode software standby mode can be exited by input of an external interrupt at the nmi, irq 0 , irq 1 , or irq 2 pin, or by input at the res or stby pin. exit by interrupt: when an nmi, irq 0 , irq 1 , or irq 2 interrupt request signal is received, the clock oscillator begins operating. after the oscillator settling time selected by bits sts2 to sts0 in syscr, stable clock signals are supplied to the entire chip, software standby mode ends, and interrupt exception handling begins. software standby mode is not exited if the interrupt enable bits of interrupts irq 0 , irq 1 , and irq 2 are cleared to 0, or if thes e interrupts are masked in the cpu. exit by res input: when the res input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire chip. the res signal must be held low long enough for the clock oscillator to stabilize. when res goes high, the cpu starts reset exception handling. exit by stby input: low input at the stby pin causes a transition to hardware standby mode. 19. power-down state rev.5.00 sep. 12, 2007 page 564 of 764 rej09b0396-0500 19.4.3 selection of waiting time for exit from software standby mode bits sts2 to sts0 in syscr and bits div1 and div0 in divcr should be set as follows. crystal resonator: set sts2 to sts0, div1, and div0 so that the waiting time (for the clock to stabilize) is at least 7 ms. tabl e 19.3 indicates the waiting times that are selected by sts2 to sts0, div1, and div0 settings at various system clock frequencies. external clock: any values may be set. table 19.3 clock frequency and waiting time for clock to settle div1 div0 sts2 sts1 sts0 waiting time 20 mhz 18 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 0 0 0 0 0 8192 states 0.4 0.46 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2 * 0 0 1 16384 states 0.8 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2 * 16.4 0 1 0 32768 states 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2 * 16.4 32.8 0 1 1 65536 states 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 32.8 65.5 1 0 0 131072 states 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 131.1 1 0 1 262144 states 13.1 * 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 1 1 0 1024 states 0.05 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1.0 1 1 1 illegal setting 0 1 0 0 0 8192 states 0.8 0.91 1.02 1.4 1.6 2.0 2.7 4.1 8.2 * 16.4 * 0 0 1 16384 states 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2 * 16.4 32.8 0 1 0 32768 states 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 32.8 65.5 0 1 1 65536 states 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 131.1 1 0 0 131072 states 13.1 * 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 1 0 1 262144 states 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3 1 1 0 1024 states 0.10 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 2.0 1 1 1 illegal setting 1 0 0 0 0 8192 states 1.6 1.8 2.0 2.7 3.3 4.1 5.5 8.2 * 16.4 * 32.8 * 0 0 1 16384 states 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 32.8 65.5 0 1 0 32768 states 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 131.1 0 1 1 65536 states 13.1 * 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 1 0 0 131072 states 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3 1 0 1 262144 states 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6 1 1 0 1024 states 0.20 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0 4.1 1 1 1 illegal setting 1 1 0 0 0 8192 states 3.3 3.6 4.1 5.5 6.6 8.2 * 10.9 * 16.4 * 32.8 * 65.5 0 0 1 16384 states 6.6 7.3 * 8.2 * 10.9 * 13.1 * 16.4 21.8 32.8 65.5 131.1 0 1 0 32768 states 13.1 * 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1 0 1 1 65536 states 26.2 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3 1 0 0 131072 states 52.4 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6 1 0 1 262144 states 104.9 116.5 131.1 174.8 209.7 262.1 349.5 524.3 1048.6 2097.1 1 1 0 1024 states 0.41 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1 8.2 * 1 1 1 illegal setting unit ms ms ms ms note: * recommended setting 19 . power-down state rev.5.00 sep. 12, 2007 page 565 of 764 rej09b0396-0500 19.4.4 sample application of software standby mode figure 19.1 shows an example in which software standby mode is entered at the fall of nmi and exited at the rise of nmi. with the nmi edge select bit (nmieg) cleared to 0 in syscr (selecting the falling edge), an nmi interrupt occurs. next the nmieg bit is set to 1 (selecting the rising edge) and the ssby bit is set to 1; then the sleep instruction is executed to enter software standby mode. software standby mode is exited at the next rising edge of the nmi signal. nmi nmieg ssby nmi interrupt handler nmieg = 1 ssby = 1 software standby mode (power- down state) oscillator settlin g time (t osc2 ) sleep instruction nmi exception handlin g clock oscillator figure 19.1 nmi timing for software standby mode (example) 19.4.5 note the i/o ports retain their existing states in software standby mode. if a port is in the high output state, its output current is not reduced. 19. power-down state rev.5.00 sep. 12, 2007 page 566 of 764 rej09b0396-0500 19.5 hardware standby mode 19.5.1 transition to hardware standby mode regardless of its current state, the chip enters hardware standby mode whenever the stby pin goes low. hardware standby mode reduces power consumption drastically by halting all functions of the cpu, dmac, dram interface, and on-chip supporting modules. all modules are reset except the on-chip ram. as long as the specified voltage is supplied, on-chip ram data is retained. i/o ports are placed in the high-impedance state. clear the rame bit to 0 in syscr before stby goes low to retain on-chip ram data. the inputs at the mode pins (md2 to md0) should not be changed during hardware standby mode. 19.5.2 exit from hardware standby mode hardware standby mode is exited by inputs at the stby and res pins. while res is low, when stby goes high, the clock oscillator starts running. res should be held low long enough for the clock oscillator to settle. when res goes high, reset exception handling begins, followed by a transition to the program execution state. 19.5.3 timing for hardware standby mode figure 19.2 shows the timing relationships for hardware standby mode. to enter hardware standby mode, first drive res low, then drive stby low. to exit hardware standby mode, first drive stby high, wait for the clock to settle, then bring res from low to high. res stby clock oscillator oscillator settlin g time reset exception handlin g figure 19.2 hardware standby mode timing 19 . power-down state rev.5.00 sep. 12, 2007 page 567 of 764 rej09b0396-0500 19.6 module standby function 19.6.1 module standby timing the module standby function can halt several of the on-chip supporting modules (sci2, sci1, sci0, the dmac, 16-bit timer, 8-b it timer, dram interface, and a/d converter) independently in the power-down state. this standby function is controlled by bits mstph2 to mstph0 in mstcrh and bits mstpl7 to mstpl0 in mstcrl . when one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the mstcr write cycle. 19.6.2 read/write in module standby when an on-chip supporting module is in module standby, read/write access to its registers is disabled. read access always results in h'ff data. write access is ignored. 19.6.3 usage notes when using the module standby function, note the following points. dmac: when setting a bit in mstcr to 1 to place the dmac or dram interface in module standby, make sure that the dmac or dram inte rface is not currently requesting the bus right. if the corresponding bit in mstcr is set to 1 when a bus request is present, operation of the bus arbiter becomes ambiguous and a malfunction may occur. dram interface: when the module standby function is used on the dram interface, set the mstcr bit to 1 while dram space is deselected. cancellation of interrupt handling: before setting a module standby bit, first disable interrupts by that module. when an on-chip supporting module is placed in standby by the module standby function, its registers are initialized, including registers with interrupt request flags. pin states: pins used by an on-chip supporting module lose their module functions when the module is placed in module standby. what happens after that depends on the particular pin. for details, see section 8, i/o ports. pins that change from the input to the out put state require special care. for example, if sci1 is pl aced in module standby, the receive data pin loses its receive data function and becomes a port pin. if its port ddr bit is set to 1, the pin becomes a data output pin, and its output may collide with external sci tran smit data. data collision should be prevented by clearing the port ddr bit to 0 or taking other appropriate action. register resetting: when an on-chip supporting module is halted by the module standby function, all its registers are initialized. to restart the module, after its mstcr bit is cleared to 0, its registers must be set up again. it is not possible to write to the registers while the mstcr bit is set to 1. 19. power-down state rev.5.00 sep. 12, 2007 page 568 of 764 rej09b0396-0500 mstcr access from dmac disabled: to prevent malfunctions, mstcr can only be accessed from the cpu. it can be read by the dmac, but it cannot be written by the dmac. 19.7 system clock output disabling function output of the system clock ( ) can be controlled by the pstop bit in mstcrh. when the pstop bit is set to 1, output of the system clock halts and the pin is placed in the high- impedance state. figure 19.3 shows the timing of the stopping and starting of system clock output. when the pstop bit is cleared to 0, output of th e system clock is enabled. table 19.4 indicates the state of the pin in various operating states. t1 t2 (pstop = 1) t3 t1 t2 (pstop = 0) mstcrh write cycle mstcrh write cycle hi g h impedance pin t3 figure 19.3 starting and stopping of system clock output table 19.4 pin state in variou s operating states operating state pstop = 0 pstop = 1 hardware standby high impedance high impedance software standby always high high impedance sleep mode system clock output high impedance normal operation system clock output high impedance 20. electrical characteristics rev.5.00 sep. 12, 2007 page 569 of 764 rej09b0396-0500 section 20 electrical characteristics 20.1 absolute maximum ratings table 20.1 lists the absolute maximum ratings. table 20.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v input voltage (except for port 7) v in ?0.3 to v cc +0.3 v input voltage (port 7) v in ?0.3 to av cc +0.3 v reference voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 570 of 764 rej09b0396-0500 20.2 electrical characteristics 20.2.1 dc characteristics tables 20.2, 20.3 and 20.4 list the dc characteristics. table 20.4 lists the permissible output currents. table 20.2 dc characteristics (1) conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 v to av cc * 1 , v ss = av ss = 0 v* 1 , t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min typ max unit test conditions v t ? 1.0 ? ? v port a, p8 2 to p8 0 v t + ? ? v cc 0.7 v schmitt trigger input voltages v t + ? v t ? 0.4 ? ? v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc ?0.7 ? v cc +0.3 v extal v cc 0.7 ? v cc +0.3 v port 7 2.0 ? av cc +0.3 v ports 4, 6, p8 3 , p8 4 , p9 5 to p9 0 , port b, d 15 to d 8 2.0 ? v cc +0.3 v input low voltage res , stby , md 2 to md 0 v il ?0.3 ? 0.5 v nmi, extal, ports 4, 6, 7, p8 3 , p8 4 , p9 5 to p9 0 , port b, d 15 to d 8 ?0.3 ? 0.8 v v oh v cc ?0.5 ? ? v i oh = ?200 a output high voltage all output pins (except reso ) 3.5 ? ? v i oh = ?1 ma output low voltage all output pins (except reso ) v ol ? ? 0.4 v i ol = 1.6 ma a 19 to a 0 ? ? 1.0 v i ol = 10 ma reso ? ? 0.4 v i ol = 2.6 ma 20. electrical characteristics rev.5.00 sep. 12, 2007 page 571 of 764 rej09b0396-0500 item symbol min typ max unit test conditions input leakage current stby , nmi, res , md 2 to md 0 |i in | ? ? 1.0 a v in = 0.5 v to v cc ?0.5 v port 7 ? ? 1.0 a v in = 0.5 v to av cc ?0.5 v three-state leakage current ports 4, 6, 8 to b, a 19 to a 0 , d 15 to d 8 |i tsi | ? ? 1.0 a v in = 0.5 v to v cc ?0.5 v reso ? ? 10.0 a v in = 0 v input pull-up mos current port 4 ?i p 50 ? 300 a v in = 0 v nmi c in ? ? 50 pf input capacitance all input pins except nmi ? ? 15 pf v in = 0 v f = 1 mhz t a = 25c current dissipation * 2 normal operation i cc * 3 ? 45 (5.0 v) 100 ma f = 20 mhz sleep mode ? 35 (5.0 v) 73 ma f = 20 mhz module standby mode ? 18 (5.0 v) 51 ma f = 20 mhz standby mode ? 0.01 5.0 a t a 50c ? ? 20.0 a 50c t a analog power supply current during a/d conversion ai cc ? 0.6 1.5 ma during a/d and d/a conversion ? 0.6 1.5 ma idle ? 0.01 5.0 a daste = 0 reference current during a/d conversion ai cc ? 0.5 0.8 ma during a/d and d/a conversion ? 2.0 3.0 ma idle ? 0.01 5.0 a daste = 0 ram standby voltage v ram 2.0 ? ? v notes: 1. do not open the pin connections of the av cc , v ref and av ss pins while the a/d converter is not in use. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 572 of 764 rej09b0396-0500 connect the av cc and v ref pins to the v cc and connect the av ss pin to the v ss , respectively. 2. given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up mos is turned off under conditions that v ih min = v cc ? 0.5 v and v il max = 0.5 v. also, the aforesaid current consumption values are when v ih min = v cc 0.9 and v il max = 0.3 v under the condition of v ram v cc < 4.5 v. 3. i cc max. (under normal operations) = 1.0 (ma) + 0.90 (ma/(mhz v)) v cc f i cc max. (when using the sleeve) = 1.0 (ma) + 0.65 (ma/(mhz v)) v cc f i cc max. (when the sleeve + module are standing by) = 1.0 (ma) + 0.45 (ma/(mhz v)) v cc f also, the typ. values for current dissipation are reference values. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 573 of 764 rej09b0396-0500 table 20.3 dc characteristics (2) conditions: vcc = 2.7 to 5.5 v, avcc = 2.7 to 5.5 v, vref = 2.7 v to avcc*1, vss = avss = 0 v* 1 , ta = ?20c to +75c (regular specifications), ta = ?40c to +85c (wide-range specifications) item symbol min typ max unit test conditions v t ? v cc 0.2 ? ? v port a, p8 2 to p8 0 v t + ? ? v cc 0.7 v schmitt trigger input voltages v t + ? v t ? v cc 0.07 ? ? v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc 0.9 ? v cc +0.3 v extal v cc 0.7 ? v cc +0.3 v port 7 v cc 0.7 ? av cc +0.3 v ports 4, 6, p8 3 , p8 4 , p9 5 to p9 0 , port b, d 15 to d 8 v cc 0.7 ? v cc +0.3 v input low voltage res , stby , md 2 to md 0 v il ?0.3 ? v cc 0.1 v nmi, extal, ports 4, 6, 7, d 15 to d 8 ?0.3 ? v cc 0.2 v v cc < 4.0 v p8 3 , p8 4 , p9 5 to p9 0 , port b 0.8 v v cc = 4.0 to 5.5 v v oh v cc ?0.5 ? ? v i oh = ?200 a output high voltage all output pins (except reso ) v cc ?1.0 ? ? v i oh = ?1 ma output low voltage all output pins (except reso ) v ol ? ? 0.4 v i ol = 1.6 ma a 19 to a 0 ? ? 1.0 v i ol = 5 ma (v cc < 4.0 v) i ol = 10 ma (v cc = 4.0 to 5.5 v) reso ? ? 0.4 v i ol = 1.6 ma 20. electrical characteristics rev.5.00 sep. 12, 2007 page 574 of 764 rej09b0396-0500 item symbol min typ max unit test conditions input leakage current stby , nmi, res , md 2 to md 0 |i in | ? ? 1.0 a v in = 0.5 v to v cc ?0.5 v port 7 ? ? 1.0 a v in = 0.5 v to av cc ?0.5 v three-state leakage current ports 4, 6, 8 to b, a 19 to a 0 , d 15 to d 8 |i tsi | ? ? 1.0 a v in = 0.5 v to v cc ?0.5 v reso ? ? 10.0 a v in = 0 v input pull-up mos current port 4 ?i p 10 ? 300 a v in = 0 v nmi c in ? ? 50 pf input capacitance all input pins except nmi ? ? 15 pf vin = 0 v f = 1 mhz ta = 25c current dissipation * 2 normal operation i cc * 3 ? 15 (3.0 v) 51 ma f = 10 mhz sleep mode ? 9 (3.0 v) 37 ma f = 10 mhz module standby mode ? 6 (3.0 v) 26 ma f = 10 mhz standby mode ? 0.01 5.0 a t a 50c ? ? 20.0 a 50c t a ai cc ? 0.2 0.5 ma av cc = 3.0 v analog power supply current during a/d conversion ? 0.6 ? ma av cc = 5.0 v ? 0.2 0.5 ma av cc = 3.0 v during a/d and d/a conversion ? 0.6 ? ma av cc = 5.0 v idle ? 0.01 5.0 a daste = 0 ai cc ? 0.3 0.5 ma v ref = 3.0 v reference current during a/d conversion ? 0.5 ? ma v ref = 5.0 v ? 1.2 2.0 ma v ref = 3.0 v during a/d and d/a conversion ? 2.0 ? ma v ref = 5.0 v idle ? 0.01 5.0 a daste = 0 ram standby voltage v ram 2.0 ? ? v notes: 1. do not open the pin connections of the av cc , v ref and av ss pins while the a/d converter is not in use. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 575 of 764 rej09b0396-0500 connect the av cc and v ref pins to the v cc and connect the av ss pin to the v ss , respectively. 2. given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up mos is turned off under conditions that v ih min = v cc ? 0.5 v and v il max = 0.5 v. also, the aforesaid current consumption values are when v ih min = v cc 0.9 and v il max = 0.3 v under the condition of v ram v cc < 2.7 v. 3. i cc max. (under normal operations) = 1.0 (ma) + 0.90 (ma/(mhz v)) v cc f i cc max. (when using the sleeve) = 1.0 (ma) + 0.65 (ma/(mhz v)) v cc f i cc max. (when the sleeve + module are standing by) = 1.0 (ma) + 0.45 (ma/(mhz v)) v cc f also, the typ. values for current dissipation are reference values. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 576 of 764 rej09b0396-0500 table 20.4 dc characteristics (3) conditions: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 v to av cc * 1 , v ss = av ss = 0 v* 1 , t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min typ max unit test conditions v t ? v cc 0.2 ? ? v port a, p8 2 to p8 0 v t + ? ? v cc 0.7 v schmitt trigger input voltages v t + ? v t ? v cc 0.07 ? ? v input high voltage res , stby , nmi, md 2 to md 0 v ih v cc 0.9 ? v cc +0.3 v extal v cc 0.7 ? v cc +0.3 v port 7 v cc 0.7 ? av cc +0.3 v ports 4, 6, p8 3 , p8 4 , p9 5 to p9 0 , port b, d 15 to d 8 v cc 0.7 ? v cc +0.3 v input low voltage res , stby , md 2 to md 0 v il ?0.3 ? v cc 0.1 v nmi, extal, ports 4, 6, 7 ?0.3 ? v cc 0.2 v v cc < 4.0 v p8 3 , p8 4 , p9 5 to p9 0 , port b, d 15 to d 8 0.8 v v cc = 4.0 to 5.5 v v oh v cc ?0.5 ? ? v i oh = ?200 a output high voltage all output pins (except reso ) v cc ?1.0 ? ? v i oh = ?1 ma output low voltage all output pins (except reso ) v ol ? ? 0.4 v i ol = 1.6 ma a 19 to a 0 ? ? 1.0 v i ol = 5 ma (v cc < 4.0 v) i ol = 10 ma (v cc = 4.0 to 5.5 v) reso ? ? 0.4 v i ol = 1.6 ma 20. electrical characteristics rev.5.00 sep. 12, 2007 page 577 of 764 rej09b0396-0500 item symbol min typ max unit test conditions input leakage current stby , nmi, res , md 2 to md 0 |i in | ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v port 7 ? ? 1.0 a v in = 0.5 v to av cc ? 0.5 v three-state leakage current ports 4, 6, 8 to b, a 19 to a 0 , d 15 to d 8 |i tsi | ? ? 1.0 a v in = 0.5 v to v cc ? 0.5 v reso ? ? 10.0 a v in = 0 v input pull-up mos current port 4 ?i p 10 ? 300 a v in = 0 v nmi c in ? ? 50 pf input capacitance all input pins except nmi ? ? 15 pf v in = 0 v f = 1 mhz t a = 25c current dissipation * 2 normal operation i cc * 3 ? 20 (3.5 v) 66 ma f = 13 mhz sleep mode ? 15 (3.5 v) 48 ma f = 13 mhz module standby mode ? 9 (3.5 v) 34 ma f = 13 mhz standby mode ? 0.01 5.0 a t a 50c ? ? 20.0 a 50c t a ai cc ? 0.2 0.5 ma av cc = 3.0 v analog power supply current during a/d conversion ? 0.6 ? ma av cc = 5.0 v ? 0.2 0.5 ma av cc = 3.0 v during a/d and d/a conversion ? 0.6 ? ma av cc = 5.0 v idle ? 0.01 5.0 a daste = 0 ai cc ? 0.3 0.5 ma v ref = 3.0 v reference current during a/d conversion ? 0.5 ? ma v ref = 5.0 v ? 1.2 2.0 ma v ref = 3.0 v during a/d and d/a conversion ? 2.0 ? ma v ref = 5.0 v idle ? 0.01 5.0 a daste = 0 ram standby voltage v ram 2.0 ? ? v notes: 1. do not open the pin connections of the av cc , v ref and av ss pins while the a/d converter is not in use. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 578 of 764 rej09b0396-0500 connect the av cc and v ref pins to the v cc and connect the av ss pin to the v ss , respectively. 2. given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up mos is turned off under conditions that v ih min = v cc ? 0.5 v and v il max = 0.5 v. also, the aforesaid current consumption values are when v ih min = v cc 0.9 and v il max = 0.3 v under the condition of v ram v cc < 3.0 v. 3. i cc max. (under normal operations) = 1.0 (ma) + 0.90 (ma/(mhz v)) v cc f i cc max. (when using the sleeve) = 1.0 (ma) + 0.65 (ma/(mhz v)) v cc f i cc max. (when the sleeve + module are standing by) = 1.0 (ma) + 0.45 (ma/(mhz v)) v cc f also, the typ. values for current dissipation are reference values. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 579 of 764 rej09b0396-0500 table 20.5 permissible output currents conditions: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) item symbol min typ max unit a 19 to a 0 i ol ? ? 10 ma permissible output low current (per pin) other output pins ? ? 2.0 ma permissible output low current (total) total of 20 pins in a 19 to a 0 i ol ? ? 80 ma total of all output pins, including the above ? ? 120 ma permissible output high current (per pin) all output pins |?i oh | ? ? 2.0 ma permissible output high current (total) total of all output pins | ?i oh | ? ? 40 ma notes: 1. to protect chip reliability, do not exceed the output current values in table 20.5. 2. when driving a darlington pair, always insert a current-limiting resistor in the output line, as shown in figures 20.1. h8/3006 and h8/3007 port 2 k darlin g ton pair figure 20.1 darlington pair drive circuit (example) 20. electrical characteristics rev.5.00 sep. 12, 2007 page 580 of 764 rej09b0396-0500 20.2.2 ac characteristics clock timing parameters are listed in table 20.6, control signal timing parameters in table 20.7, and bus timing parameters in table 20.8. timing parameters of the on-chip supporting modules are listed in table 20.9. table 20.6 clock timing condition: t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to av cc , v ss = av ss = 0 v, = 1 to 10 mhz condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, = 1 to 13 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, = 1 to 20 mhz condition a condition b condition c test item symbol min max min max min max unit conditions clock cycle time t cyc 100 1000 76.9 1000 50 1000 ns figure 20.3 clock pulse low width t cl 30 ? 20 ? 15 ? ns clock pulse high width t ch 30 ? 20 ? 15 ? ns clock rise time t cr ? 20 ? 15 ? 10 ns clock fall time t cf ? 20 ? 15 ? 10 ns clock oscillator settling time at reset t osc1 20 ? 20 ? 20 ? ms figure 20.4 clock oscillator settling time in software standby t osc2 7 ? 7 ? 7 ? ms figure 19.1 20. electrical characteristics rev.5.00 sep. 12, 2007 page 581 of 764 rej09b0396-0500 table 20.7 control signal timing condition: t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to av cc , v ss = av ss = 0 v, = 1 to 10 mhz condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, = 1 to 13 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, = 1 to 20 mhz condition a condition b condition c test item symbol min max min max min max unit conditions res setup time t ress 200 ? 200 ? 150 ? ns figure 20.5 res pulse width t resw 10 ? 10 ? 10 ? t cyc mode programming setup time t mds 200 ? 200 ? 200 ? ns reso output delay time t resd ? 100 ? 100 ? 50 ns figure 20.6 reso output pulse width t resow 132 ? 132 ? 132 ? t cyc nmi, irq setup time t nmis 200 ? 200 ? 150 ? ns figure 20.7 nmi, irq hold time t nmih 10 ? 10 ? 10 ? ns nmi, irq pulse width (in recovery from software standby mode) t nmiw 200 ? 200 ? 200 ? ns 20. electrical characteristics rev.5.00 sep. 12, 2007 page 582 of 764 rej09b0396-0500 table 20.8 bus timing condition: t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to av cc , v ss = av ss = 0 v, = 1 to 10 mhz condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, = 1 to 13 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, = 1 to 20 mhz condition a condition b condition c test item symbol min max min max min max unit conditions address delay time t ad ? 50 ? 40 ? 25 ns address hold time t ah 0.5 t cyc ? 45 ? 0.5 t cyc ? 35 ? 0.5 t cyc ? 20 ? ns figure 20.8, figure 20.9, figure 20.11, figure 20.12 read strobe delay time t rsd ? 60 ? 50 ? 25 ns address strobe delay time t asd ? 60 ? 50 ? 25 ns write strobe delay time t wsd ? 60 ? 50 ? 25 ns strobe delay time t sd ? 60 ? 50 ? 25 ns write strobe pulse width 1 t wsw1 1.0 t cyc ? 50 ? 1.0 t cyc ? 40 ? 1.0 t cyc ? 25 ? ns write strobe pulse width 2 t wsw2 1.5 t cyc ? 50 ? 1.5 t cyc ? 40 ? 1.5 t cyc ? 25 ? ns address setup time 1 t as1 0.5 t cyc ? 45 ? 0.5 t cyc ? 35 ? 0.5 t cyc ? 20 ? ns address setup time 2 t as2 1.0 t cyc ? 45 ? 1.0 t cyc ? 35 ? 1.0 t cyc ? 20 ? ns read data setup time t rds 50 ? 40 ? 25 ? ns read data hold time t rdh 0 ? 0 ? 0 ? ns write data delay time t wdd ? 60 ? 50 ? 35 ns 20. electrical characteristics rev.5.00 sep. 12, 2007 page 583 of 764 rej09b0396-0500 condition a condition b condition c test item symbol min max min max min max unit conditions write data setup time 1 t wds1 1.0 t cyc ? 50 ? 1.0 t cyc ? 40 ? 1.0 t cyc ? 30 ? ns write data setup time 2 t wds2 2.0 t cyc ? 50 ? 2.0 t cyc ? 40 ? 2.0 t cyc ? 30 ? ns figure 20.8, figure 20.9, figure 20.11, figure 20.12 write data hold time t wdh 0.5 t cyc ? 30 ? 0.5 t cyc ? 25 ? 0.5 t cyc ? 15 ? ns read data access time 1 t acc1 ? 2.0 t cyc ? 100 ? 2.0 t cyc ? 80 ? 2.0 t cyc ? 45 ns read data access time 2 t acc2 ? 3.0 t cyc ? 100 ? 3.0 t cyc ? 80 ? 3.0 t cyc ? 45 ns read data access time 3 t acc3 ? 1.5 t cyc ? 100 ? 1.5 t cyc ? 80 ? 1.5 t cyc ? 45 ns read data access time 4 t acc4 ? 2.5 t cyc ? 100 ? 2.5 t cyc ? 80 ? 2.5 t cyc ? 45 ns precharge time 1 t pch1 1.0 t cyc ? 40 ? 1.0 t cyc ? 30 ? 1.0 t cyc ? 20 ? ns precharge time 2 t pch2 0.5 t cyc ? 40 ? 0.5 t cyc ? 30 ? 0.5 t cyc ? 20 ? ns wait setup time t wts 40 ? 40 ? 25 ? ns figure 20.10 wait hold time t wth 5 ? 5 ? 5 ? ns bus request setup time t brqs 40 ? 40 ? 25 ? ns figure 20.13 bus acknowledge delay time 1 t bacd1 ? 60 ? 50 ? 30 ns bus acknowledge delay time 2 t bacd2 ? 60 ? 50 ? 30 ns bus-floating time t bzd ? 60 ? 50 ? 30 ns ras precharge time t rp 1.5 t cyc ? 50 ? 1.5 t cyc ? 40 ? 1.5 t cyc ? 25 ? ns cas precharge time t cp 0.5 t cyc ? 30 ? 0.5 t cyc ? 25 ? 0.5 t cyc ? 15 ? ns figure 20.14 to figure 20.16 low address hold time t rah 0.5 t cyc ? 30 ? 0.5 t cyc ? 25 ? 0.5 t cyc ? 15 ? ns ras delay time 1 t rad1 ? 60 ? 50 ? 25 ns ras delay time 2 t rad2 ? 60 ? 50 ? 30 ns 20. electrical characteristics rev.5.00 sep. 12, 2007 page 584 of 764 rej09b0396-0500 condition a condition b condition c test item symbol min max min max min max unit conditions cas delay time 1 t casd1 ? 60 ? 50 ? 25 ns cas delay time 2 t casd2 ? 60 ? 50 ? 25 ns figure 20.14 to figure 20.16 we delay time t wcd ? 60 ? 50 ? 25 ns cas pulse width 1 t cas1 1.5 t cyc ? 50 ? 1.5 t cyc ? 40 ? 1.5 t cyc ? 20 ? ns cas pulse width 2 t cas2 1.0 t cyc ? 50 ? 1.0 t cyc ? 40 ? 1.0 t cyc ? 20 ? ns cas pulse width 3 t cas3 1.0 t cyc ? 50 ? 1.0 t cyc ? 40 ? 1.0 t cyc ? 20 ? ns ras access time t rac ? 2.5 t cyc ? 80 ? 2.5 t cyc ? 70 ? 2.5 t cyc ? 40 ns address access time t aa ? 2.0 t cyc ? 100 ? 2.0 t cyc ? 80 ? 2.0 t cyc ? 50 ns cas access time t cac ? 1.5 t cyc ? 100 ? 1.5 t cyc ? 80 ? 1.5 t cyc ? 50 ns we setup time t wcs 0.5 t cyc ? 45 ? 0.5 t cyc ? 35 ? 0.5 t cyc ? 20 ? ns we hold time t wch 0.5 t cyc ? 40 ? 0.5 t cyc ? 28 ? 0.5 t cyc ? 15 ? ns write data setup time t wds 0.5 t cyc ? 45 ? 0.5 t cyc ? 35 ? 0.5 t cyc ? 20 ? ns we write data hold time t wdh 0.5 t cyc ? 30 ? 0.5 t cyc ? 25 ? 0.5 t cyc ? 15 ? ns cas setup time 1 t csr1 0.5 t cyc ? 30 ? 0.5 t cyc ? 25 ? 0.5 t cyc ? 20 ? ns cas setup time 2 t csr2 0.5 t cyc ? 30 ? 0.5 t cyc ? 25 ? 0.5 t cyc ? 15 ? ns cas hold time t chr 0.5 t cyc ? 30 ? 0.5 t cyc ? 25 ? 0.5 t cyc ? 15 ? ns ras pulse width t ras 1.5 t cyc ? 30 ? 1.5 t cyc ? 25 ? 1.5 t cyc ? 15 ? ns 20. electrical characteristics rev.5.00 sep. 12, 2007 page 585 of 764 rej09b0396-0500 table 20.9 timing of on-chip supporting modules condition: t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to av cc , v ss = av ss = 0 v, = 1 to 10 mhz condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, = 1 to 13 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, = 1 to 20 mhz condition a condition b condition c item symbol min max min max min max unit test conditions output data delay time t pwd ? 100 ? 100 ? 50 ns figure 20.17 ports and tpc input data setup time t prs 50 ? 50 ? 50 ? ns input data hold time t prh 50 ? 50 ? 50 ? ns 16-bit timer timer output delay time t tocd ? 100 ? 100 ? 50 ns figure 20.18 timer input setup time t tics 50 ? 50 ? 50 ? ns timer clock input setup time t tcks 50 ? 50 ? 50 ? ns figure 20.19 single edge t tckwh 1.5 ? 1.5 ? 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? 2.5 ? 2.5 ? t cyc 8-bit timer timer output delay time t tocd ? 100 ? 100 ? 50 ns figure 20.18 timer input setup time t tics 50 ? 50 ? 50 ? ns timer clock input setup time t tcks 50 ? 50 ? 50 ? ns figure 20.19 single edge t tckwh 1.5 ? 1.5 ? 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? 2.5 ? 2.5 ? t cyc 20. electrical characteristics rev.5.00 sep. 12, 2007 page 586 of 764 rej09b0396-0500 condition a condition b condition c item symbol min max min max min max unit test conditions sci asyn- chronous t scyc 4 ? 4 ? 4 ? t cyc figure 20.20 input clock cycle syn- chronous 6 ? 6 ? 6 ? t cyc input clock rise time t sckr 1.5 ? 1.5 ? 1.5 ? t cyc input clock fall time t sckf 1.5 ? 1.5 ? 1.5 ? t cyc input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc transmit data delay time t txd ? 100 ? 100 ? 100 ns figure 20.21 receive data setup time (synchronous) t rxs 100 ? 100 ? 100 ? ns clock input t rxh 100 ? 100 ? 100 ? ns receive data hold time (syn- chronous) clock output 0 ? 0 ? 0 ? ns dmac tend delay time 1 t ted1 ? 100 ? 100 ? 50 ns figure 20.22, figure 20.23 tend delay time 2 t ted2 ? 100 ? 100 ? 50 ns dreq setup time t drqs 40 ? 40 ? 25 ? ns figure 20.24 dreq hold time t drqh 10 ? 10 ? 10 ? ns 20. electrical characteristics rev.5.00 sep. 12, 2007 page 587 of 764 rej09b0396-0500 cr h r l h8/3006 and h8/3007 output pin c = 90 pf: ports 4, 6, 8, a 19 to a 0 , d 15 to d 8 c = 30 pf: ports 9, a, b, reso input/output timing measurement levels ? low: 0.8 v ? high: 2.0 v r = 2.4 k r = 12 k l h figure 20.2 output load circuit 20. electrical characteristics rev.5.00 sep. 12, 2007 page 588 of 764 rej09b0396-0500 20.2.3 a/d conversion characteristics table 20.10 lists the a/d conversion characteristics. table 20.10 a/d conversion characteristics condition: t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to av cc , v ss = av ss = 0 v, fmax = 10 mhz condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 13 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 20 mhz condition a condition b condition c item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time: 134 states conversion time (single mode) ? ? 134 ? ? 134 ? ? 134 t cyc analog input capacitance ? ? 20 ? ? 20 ? ? 20 pf 13 mhz ? ? ? ? ? ? ? ? 10 k > 13 mhz ? ? ? ? ? ? ? ? 5 k permissible signal- source impedance 4.0 v av cc 5.5 v ? ? 10 ? ? 10 ? ? ? k 2.7 v av cc < 4.0 v ? ? 5 ? ? 5 ? ? ? k nonlinearity error ? ? 7.5 ? ? 7.5 ? ? 3.5 lsb offset error ? ? 7.5 ? ? 7.5 ? ? 3.5 lsb full-scale error ? ? 7.5 ? ? 7.5 ? ? 3.5 lsb quantization error ? ? 0.5 ? ? 0.5 ? ? 0.5 lsb absolute accuracy ? ? 8.0 ? ? 8.0 ? ? 4.0 lsb 20. electrical characteristics rev.5.00 sep. 12, 2007 page 589 of 764 rej09b0396-0500 condition a condition b condition c item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time: 70 states conversion time (single mode) ? ? 70 ? ? 70 ? ? 70 t cyc analog input capacitance ? ? 20 ? ? 20 ? ? 20 pf 13 mhz ? ? ? ? ? ? ? ? 5 k > 13 mhz ? ? ? ? ? ? ? ? 3 k permissible signal- source impedance 4.0 v av cc 5.5 v ? ? 5 ? ? 5 ? ? ? k 2.7 v av cc < 4.0 v ? ? 3 ? ? 3 ? ? ? k nonlinearity error ? ? 15.5 ? ? 15.5 ? ? 7.5 lsb offset error ? ? 15.5 ? ? 15.5 ? ? 7.5 lsb full-scale error ? ? 15.5 ? ? 15.5 ? ? 7.5 lsb quantization error ? ? 0.5 ? ? 0.5 ? ? 0.5 lsb absolute accuracy ? ? 16 ? ? 16 ? ? 8.0 lsb 20. electrical characteristics rev.5.00 sep. 12, 2007 page 590 of 764 rej09b0396-0500 20.2.4 d/a conversion characteristics table 20.11 lists the d/a conversion characteristics. table 20.11 d/a conversion characteristics condition: t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to av cc , v ss = av ss = 0 v, fmax = 10 mhz condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to av cc , v ss = av ss = 0 v, fmax = 13 mhz condition c: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , v ref = 4.5 to av cc , v ss = av ss = 0 v, fmax = 20 mhz condition a condition b condition c test item min typ max min typ max min typ max unit conditions resolution 8 8 8 8 8 8 8 8 8 bits conversion time (centering time) ? ? 10 ? ? 10 ? ? 10 s 20 pf capacitive load absolute accuracy ? 2.0 3.0 ? 2.0 3.0 ? 1.5 2.0 lsb 2 m resistive load ? ? 2.0 ? ? 2.0 ? ? 1.5 lsb 4 m resistive load 20. electrical characteristics rev.5.00 sep. 12, 2007 page 591 of 764 rej09b0396-0500 20.3 operational timing this section shows timing diagrams. 20.3.1 clock timing clock timing is shown as follows: ? system clock timing figure 20.3 shows the system clock timing. ? oscillator settling timing figure 20.4 shows the oscillator settling timing. t cr t cl t cf t ch t cyc figure 20.3 system clock timing v cc stby res t osc1 t osc1 figure 20.4 oscillator settling timing 20. electrical characteristics rev.5.00 sep. 12, 2007 page 592 of 764 rej09b0396-0500 20.3.2 control signal timing control signal timing is shown as follows: ? reset input timing figure 20.5 shows the reset input timing. ? reset output timing figure 20.6 shows the reset output timing. ? interrupt input timing figure 20.7 shows the interrupt input timing for nmi and irq 5 to irq 0 . t ress t ress t resw t mds res md 2 to md 0 figure 20.5 reset input timing reso t resd t resow t resd figure 20.6 reset output timing 20. electrical characteristics rev.5.00 sep. 12, 2007 page 593 of 764 rej09b0396-0500 nmi irq irq e l t nmis t nmih t nmis t nmih t nmis t nmiw nmi irq j irq : ed g e-sensitive irq : level-sensitive irq (i = 0 to 5) e l i i irq (j = 0 to 5) figure 20.7 interrupt input timing 20.3.3 bus timing bus timing is shown as follows: ? basic bus cycle: two-state access figure 20.8 shows the timing of the external two-state access cycle. ? basic bus cycle: three-state access figure 20.9 shows the timing of the external three-state access cycle. ? basic bus cycle: three-state access with one wait state figure 20.10 shows the timing of the external three-state access cycle with one wait state inserted. ? burst rom access timing: burst cycle two-state figure 20.11 shows the timing of th e burst cycle two-state access. ? burst rom access timing: burst cycle three-state figure 20.12 shows the timing of the burst cycle three-state access. ? bus-release mode timing figure 20.13 shows the bus-release mode timing. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 594 of 764 rej09b0396-0500 t 1 t 2 t ch t ad t cl t cr t cf t asd t acc3 t as1 t cyc t cyc t sd t rds t ah t pch1 t pch2 t rdh * t pch1 t sd t ah t asd t acc3 t as1 t acc1 t asd t as1 t wsw1 t wds1 t wdh t wdd a 23 to a 0 , cs n as rd (read) d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) note: * specification from the earliest ne g ation timin g of a 23 to a 0 , csn , and rd . t rsd figure 20.8 basic bus cycle: two-state access 20. electrical characteristics rev.5.00 sep. 12, 2007 page 595 of 764 rej09b0396-0500 t 1 t 2 t 3 t acc4 t acc4 t as2 t wdd t wds2 t wsw2 t wsd t acc2 t rds a 23 to a 0 , cs n as rd (read) d 15 to d 0 (read) hwr, lwr (write) d 15 to d 0 (write) figure 20.9 basic bus cycle: three-state access 20. electrical characteristics rev.5.00 sep. 12, 2007 page 596 of 764 rej09b0396-0500 t 1 t 2 t w t 3 t wts t wts t wth as rd (read) d 15 to d 0 (read) hwr , lwr (write) d 15 to d 0 (write) wait t wth a 23 to a 0 , cs n figure 20.10 basic bus cycle: th ree-state access with one wait state 20. electrical characteristics rev.5.00 sep. 12, 2007 page 597 of 764 rej09b0396-0500 t ad t asd t as1 t acc4 t rds t rds t 3 t 1 t 2 t 2 t 1 t asd t sd t ah t as1 t ah t sd t asd t as1 t acc4 t acc2 t rsd t rdh * t acc1 t ad a 23 to a 3 , csn a 2 to a 0 as rd d 15 to d 0 note: * specification from the earliest ne g ation timin g of a 23 to a 0 , csn , and rd . figure 20.11 burst rom access timing: two-state access 20. electrical characteristics rev.5.00 sep. 12, 2007 page 598 of 764 rej09b0396-0500 t ad t asd t as1 t acc4 t rds t rds t 3 t 1 t 2 t 3 t 2 t 1 t asd t sd t ah t as1 t ah t sd t asd t as1 t acc4 t acc2 t rsd t rdh * t acc2 t ad a 23 to a 3 , csn a 2 to a 0 as rd d 15 to d 0 note: * specification from the earliest ne g ation timin g of a 23 to a 0 , csn , and rd . figure 20.12 burst rom access timing: three-state access breq back a 23 to a 0 , as , rd , hwr , lwr t brqs t brqs t bacd1 t bzd t bacd2 t bzd figure 20.13 bus-release mode timing 20. electrical characteristics rev.5.00 sep. 12, 2007 page 599 of 764 rej09b0396-0500 20.3.4 dram interface bus timing dram interface bus timing is shown as follows: ? dram bus timing: read and write access figure 20.14 shows the timing of the read and write access. ? dram bus timing: cas before ras refresh figure 20.15 shows the timing of the cas before ras refresh. ? dram bus timing: self-refresh figure 20.16 shows the timing of the self-refresh. 20. electrical characteristics rev.5.00 sep. 12, 2007 page 600 of 764 rej09b0396-0500 t p t ad t r t c1 t c2 t rp t ad t as1 t rad1 t rad2 t casd2 t cp t asd t cas1 t rdh * t casd2 t cas2 t cp t casd1 t cac t rds t rac t aa t rah t ad t wcd t wch t wcs t wdd t wds t wdh t asd a 23 to a 0 cs 5 to cs 2 ( ras 5 to ras 2 ) ucas , lcas (read) rd ( we ) (read) (hi g h) (hi g h) ucas , lcas (write) rd ( we ) (write) d 15 to d 0 (read) d 15 to d 0 (write) rfsh note: * specification from the earliest ne g ation timin g of ras and cas . figure 20.14 dram bus timing (read/write) 20. electrical characteristics rev.5.00 sep. 12, 2007 page 601 of 764 rej09b0396-0500 tr p tr 1 tr 2 t rp t rad1 t casd1 t casd2 t rad2 t ras cs 5 to cs 2 ( ras 5 to ras 2 ) ucas , lcas rd ( we ) (hi g h) rfsh t csr1 t rad1 t csr1 t chr t ras t rad2 t chr t cas3 figure 20.15 dram bus timing (cas before ras refresh) 20. electrical characteristics rev.5.00 sep. 12, 2007 page 602 of 764 rej09b0396-0500 t csr2 t csr2 cs 5 to cs 2 ( ras 5 to ras 2 ) ucas , lcas rd ( we ) (hi g h) rfsh figure 20.16 dram bus timing (self-refresh) 20.3.5 tpc and i/o port timing figure 20.17 shows the tpc and i/o port input/output timing. t 1 t 2 t 3 port 4, 6 to b (read) port 4, 6, 8 to b (write) t prs t prh t pwd figure 20.17 tpc and i/o port input/output timing 20. electrical characteristics rev.5.00 sep. 12, 2007 page 603 of 764 rej09b0396-0500 20.3.6 timer input/output timing the timings of 16-bit and 8-bit timer are shown as follows: ? timer input/output timing figure 20.18 shows the timer input/output timing. ? timer external clock input timing figure 20.19 shows the timer external clock input timing. output compare * 1 input capture * 2 t tocd t tics notes: 1. tioca to tioca , tiocb to tiocb , tmo 0 , tmo 2 , tmio 1 ,tmio 3 2. tioca to tioca , tiocb to tiocb , tmio 1 , tmio 3 0202 0202 figure 20.18 timer input/output timing t tcks t tcks t tckwh t tckwl tclka to tclkd figure 20.19 timer external clock input timing 20. electrical characteristics rev.5.00 sep. 12, 2007 page 604 of 764 rej09b0396-0500 20.3.7 sci input/output timing sci timing is shown as follows: ? sci input clock timing figure 20.20 shows the sci input clock timing. ? sci input/output timing (synchronous mode) figure 20.21 shows the sci input/output timing in synchronous mode. sck 0 to sck 2 t sckw t scyc t sckr t sckf figure 20.20 sci input clock timing t scyc t txd t rxs t rxh sck 0 to sck 2 txd 0 to txd 2 (transmit data) rxd 0 to rxd 2 (receive data) figure 20.21 sci input/output timing in synchronous mode 20. electrical characteristics rev.5.00 sep. 12, 2007 page 605 of 764 rej09b0396-0500 20.3.8 dmac timing dmac timing is shown as follows. ? dmac tend output timing for 2 state access figure 20.22 shows the dmac tend output timing for 2 state access. ? dmac tend output timing for 3 state access figure 20.23 shows the dmac tend output timing for 3 state access. ? dmac dreq input timing figure 20.24 shows dmac dreq input timing. t 1 t 2 t ted1 t ted2 tend figure 20.22 dmac tend output timing for 2 state access t 1 t 2 t 3 t ted1 t ted2 tend figure 20.23 dmac tend output timing for 3 state access t drqh t drqs dreq figure 20.24 dmac dreq input timing 20. electrical characteristics rev.5.00 sep. 12, 2007 page 606 of 764 rej09b0396-0500 appendix a instruction set rev.5.00 sep. 12, 2007 page 607 of 764 rej09b0396-0500 appendix a instruction set a.1 instruction list operand notation symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (address register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the operand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides exclusive logical or of the operands on both sides ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7). appendix a instruction set rev.5.00 sep. 12, 2007 page 608 of 764 rej09b0396-0500 condition code notation symbol description changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction varies depending on conditions, described in notes appendix a instruction set rev.5.00 sep. 12, 2007 page 609 of 764 rej09b0396-0500 table a.1 instruction set 1. data transfer instructions mnemoni c operation condition code operand size #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd b b b b b b b b b b b b b b b b w w w w w w w 2 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 4 2 2 4 8 2 4 #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32?1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? appendix a instruction set rev.5.00 sep. 12, 2007 page 610 of 764 rej09b0396-0500 mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn w pop.l ern l w w w w w w w l l l l l l l l l l l l l l w l 6 2 4 8 2 4 6 6 2 4 6 10 4 6 8 4 6 10 4 6 8 2 4 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 rd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp 8 4 6 10 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? appendix a instruction set rev.5.00 sep. 12, 2007 page 611 of 764 rej09b0396-0500 mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 w l b b 2 4 4 4 sp?2 sp rn16 @sp sp?4 sp ern32 @sp cannot be used in the h8/3006 and h8/3007 cannot be used in the h8/3006 and h8/3007 6 10 ? ? 0 ? ? ? 0 ? cannot be used in the h8/3006 and h8/3007 cannot be used in the h8/3006 and h8/3007 2. arithmetic instructions mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd b b w w l l b b l l l b w w 2 2 4 2 6 2 2 2 2 2 2 2 2 2 rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 2 2 4 2 6 2 2 2 2 2 2 2 2 2 ? ? ? (1) ? (1) ? (2) ? (2) ? (3) ? (3) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.5.00 sep. 12, 2007 page 612 of 764 rej09b0396-0500 mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd l l b b w w l l b b l l l b w w l l b b w b w b 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8?rs8 rd8 rd16?#xx:16 rd16 rd16?rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8?#xx:8?c rd8 rd8?rs8?c rd8 erd32?1 erd32 erd32?2 erd32 erd32?4 erd32 rd8?1 rd8 rd16?1 rd16 rd16?2 rd16 erd32?1 erd32 erd32?2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 14 22 16 24 14 ? ? ? ? ? ? ? * * ? ? ? (1) ? (1) ? (2) ? (2) ? (3) ? (3) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (6) (7) ? ? appendix a instruction set rev.5.00 sep. 12, 2007 page 613 of 764 rej09b0396-0500 mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd w b w b b w w l l b w l w l w l 2 4 4 2 2 4 2 6 2 2 2 2 2 2 2 2 erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8?#xx:8 rd8?rs8 rd16?#xx:16 rd16?rs16 erd32?#xx:32 erd32?ers32 0?rd8 rd8 0?rd16 rd16 0?erd32 erd32 0 ( appendix a instruction set rev.5.00 sep. 12, 2007 page 614 of 764 rej09b0396-0500 3. logic instructions mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd b b w w l l b b w w l l b b w w l l b w l 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ? rd8 rd8 ? rd16 rd16 ? rd32 rd32 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? ? ? 0 ? appendix a instruction set rev.5.00 sep. 12, 2007 page 615 of 764 rej09b0396-0500 4. shift instructions mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 c msb lsb c msb lsb c msb lsb c msb lsb msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb appendix a instruction set rev.5.00 sep. 12, 2007 page 616 of 764 rej09b0396-0500 5. bit manipulation instructions mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd b b b b b b b b b b b b b b b b b b b b b b b b b 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @erd) ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @erd) ? (rn8 of @erd) (rn8 of @aa:8) ? (rn8 of @aa:8) ? (#xx:3 of rd8) z ? (#xx:3 of @erd) z ? (#xx:3 of @aa:8) z ? (rn8 of @rd8) z ? (rn8 of @erd) z ? (rn8 of @aa:8) z (#xx:3 of rd8) c 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.5.00 sep. 12, 2007 page 617 of 764 rej09b0396-0500 mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 (#xx:3 of @erd) c (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @erd24) ? c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a instruction set rev.5.00 sep. 12, 2007 page 618 of 764 rej09b0396-0500 6. branching instructions mnemonic operation branch condition condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 if condition is true then pc pc+d else next; 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 appendix a instruction set rev.5.00 sep. 12, 2007 page 619 of 764 rej09b0396-0500 mnemoni c operation operation condition code operand size #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? addressing mode and instru c tion length (bytes) normal advan c ed no. of states * 1 i h n z v c ble d:8 ble d:16 jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts ? ? ? ? ? ? ? ? ? ? ? 2 4 2 4 2 2 4 2 4 2 2 pc ern pc aa:24 pc @aa:8 pc @?sp pc pc+d:8 pc @?sp pc pc+d:16 pc @?sp pc @ern pc @?sp pc @aa:24 pc @?sp pc @aa:8 pc @sp+ 4 6 4 6 8 6 8 6 8 8 8 10 8 10 8 10 12 10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bran c h condition if condition is true then pc pc+d else next; z (n v) = 0 z (n v) = 1 appendix a instruction set rev.5.00 sep. 12, 2007 page 620 of 764 rej09b0396-0500 7. system control instructions mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop ? ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 4 6 10 4 6 8 2 4 6 10 4 6 8 2 2 2 2 pc @?sp ccr @?sp appendix a instruction set rev.5.00 sep. 12, 2007 page 621 of 764 rej09b0396-0500 8. block transfer instructions mnemonic operation condition code operand size #xx rn @ ern @ (d, ern) @ ?ern/ @ ern+ @ aa @ (d, pc) @@ aa ? addressing mode and instruction length (bytes) normal advanced no. of states * 1 i h n z v c eepmov. b eepmov. w ? ? 4 4 if r4l 0 repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l?1 r4l until r4l=0 else next; if r4 0 repeat @r5 @r6 r5+1 r5 r6+1 r6 r4?1 r4 until r4=0 else next; 8+ 4n * 2 8+ 4n * 2 ? ? ? ? ? ? ? ? ? ? ? ? notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. for other cases see appendix a.3, number of states required for execution. normal mode is not available in the h8/3006 and h8/3007. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for execution of an instruction that transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0. appendix a instruction set rev.5.00 sep. 12, 2007 page 622 of 764 rej09b0396-0500 a.2 operation code maps table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc bnq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov in s tr uc tion when m o s t s ignifi c ant bit of bh i s 0. in s tr uc tion when m o s t s ignifi c ant bit of bh i s 1. in s tr uc tion c o d e: table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) bvs blt bge bsr table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (3) 1 s t b y te 2n d b y te ah bh al bl add sub mov cmp mov.b appendix a instruction set rev.5.00 sep. 12, 2007 page 623 of 764 rej09b0396-0500 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt in s tr uc tion c o d e: bvs sleep bvc bge table a.2 (3) table a.2 (3) table a.2 (3) bne and and inc extu dec beq inc extu dec bcs xor xor brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1 s t b y te 2n d b y te ah bh al bl subs adds add mov sub cmp shll shlr rotxl rotxr not shal shar rotl rotr neg shll shlr rotxl rotxr not bls sub sub appendix a instruction set rev.5.00 sep. 12, 2007 page 624 of 764 rej09b0396-0500 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divixs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc appendix a instruction set rev.5.00 sep. 12, 2007 page 625 of 764 rej09b0396-0500 a.3 number of states required for execution the tables in this section can be used to calculate the number of states required for instruction execution by the h8/300h cpu. table a.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instru ction. table a.3 indicates the number of states required per cycle according to the bus size. the number of states required for execution of an instruction can be calculated from these two tables as follows: number of states = i s i + j s j + k s k + l s l + m s m + n s n examples of calculation of number of states required for execution examples: advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices acce ssed in three states with one wait state and 16-bit bus width. bset #0, @ffffc7:8 from table a.4, i = l = 2 and j = k = m = n = 0 from table a.3, s i = 4 and s l = 3 number of states = 2 4 + 2 3 = 14 jsr @@30 from table a.4, i = j = k = 2 and l = m = n = 0 from table a.3, s i = s j = s k = 4 number of states = 2 4 + 2 4 + 2 4 = 24 appendix a instruction set rev.5.00 sep. 12, 2007 page 626 of 764 rej09b0396-0500 table a.3 number of states per cycle access conditions external device on-chip supporting module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 2 6 3 4 6 + 2m 2 3 + m branch address read s j stack operation s k byte data access s l 3 2 3 + m word data access s m 6 4 6 + 2m internal operation s n 1 legend: m: number of wait states inserted into external device access appendix a instruction set rev.5.00 sep. 12, 2007 page 627 of 764 rej09b0396-0500 table a.4 number of cycles per instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @ band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 appendix a instruction set rev.5.00 sep. 12, 2007 page 628 of 764 rej09b0396-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc bra d:16 (bt d:16) brn d:16 (bf d:16) bhi d:16 bls d:16 bcc d:16 (bhs d:16) bcs d:16 (blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1 bior bior #xx:8, rd bior #xx:8, @ bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @ bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 appendix a instruction set rev.5.00 sep. 12, 2007 page 629 of 764 rej09b0396-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bnot bnot #xx:3, bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 normal * 1 2 1 advanced 2 2 bsr d:16 normal * 1 2 1 2 advanced 2 2 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2 btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 appendix a instruction set rev.5.00 sep. 12, 2007 page 630 of 764 rej09b0396-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 divxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n + 2 * 2 2n + 2 * 2 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1 inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 jmp jmp @ern 2 jmp @aa:24 2 2 jmp @@aa:8 normal * 1 2 1 2 advanced 2 2 2 jsr jsr @ern normal * 1 2 1 advanced 2 2 jsr @aa:24 normal * 1 2 1 2 advanced 2 2 2 jsr @@aa:8 normal * 1 2 1 1 advanced 2 2 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 appendix a instruction set rev.5.00 sep. 12, 2007 page 631 of 764 rej09b0396-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 appendix a instruction set rev.5.00 sep. 12, 2007 page 632 of 764 rej09b0396-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n movfpe movfpe @aa:16, rd * 1 2 1 movtpe movtpe rs, @aa:16 * 1 2 1 mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1 rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 appendix a instruction set rev.5.00 sep. 12, 2007 page 633 of 764 rej09b0396-0500 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rts rts normal * 1 2 1 2 advanced 2 2 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1 subx subx #xx:8, rd subx rs, rd 1 1 trapa trapa #x:2 normal * 1 2 1 2 4 advanced 2 2 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. not available in the h8/3006 and h8/3007. 2. n is the value set in register r4l or r4. the source and destination are accessed n + 1 times each. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 634 of 764 rej09b0396-0500 appendix b internal i/o registers b.1 addresses register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee000 reserved area (access prohibited) h'ee001 h'ee002 h'ee003 p4ddr 8 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'ee004 reserved area (access prohibited) h'ee005 p6ddr 8 ? p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'ee006 ? ? ? ? ? ? ? ? ? h'ee007 p8ddr 8 ? ? ? p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'ee008 p9ddr 8 ? ? p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'ee009 paddr 8 pa 7 ddr pa 6 ddr pa 5 ddr pa 4 ddr pa 3 ddr pa 2 ddr pa 1 ddr pa 0 ddr port a h'ee00a pbddr 8 pb 7 ddr pb 6 ddr pb 5 ddr pb 4 ddr pb 3 ddr pb 2 ddr pb 1 ddr pb 0 ddr port b h'ee00b ? ? ? ? ? ? ? ? ? h'ee00c ? ? ? ? ? ? ? ? ? h'ee00d ? ? ? ? ? ? ? ? ? h'ee00e ? ? ? ? ? ? ? ? ? h'ee00f ? ? ? ? ? ? ? ? ? h'ee010 ? ? ? ? ? ? ? ? ? h'ee011 mdcr 8 ? ? ? ? ? mds2 mds1 mds0 system h'ee012 syscr 8 ssby sts2 sts1 sts0 ue nmieg ssoe rame control h'ee013 brcr 8 a23e a22e a21e a20e ? ? ? brle bus controller h'ee014 iscr 8 ? ? irq5sc irq4sc irq3sc irq2sc irq1sc irq0sc interrupt h'ee015 ier 8 ? ? irq5e irq4e irq3e irq2e irq1e irq0e controller h'ee016 isr 8 ? ? irq5f irq4f irq3f irq2f irq1f irq0f h'ee017 ? ? ? ? ? ? ? ? ? h'ee018 ipra 8 ipra7 ipra6 ipra5 ipra4 ipra3 ipra2 ipra1 ipra0 h'ee019 iprb 8 iprb7 iprb6 iprb5 ? iprb3 iprb2 iprb1 ? h'ee01a dastcr 8 ? ? ? ? ? ? ? daste d/a converter h'ee01b divcr 8 ? ? ? ? ? ? div1 div0 system h'ee01c mstcrh 8 pstop ? ? ? ? mstph2 mstph1 mstph0 control h'ee01d mstcrl 8 mstpl7 ? mstpl5 mstpl4 mstpl3 mstpl2 ? mstpl0 h'ee01e ? ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 635 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'ee01f cscr 8 cs7e cs6e cs5e cs4e ? ? ? ? bus controller h'ee020 abwcr 8 abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 h'ee021 astcr 8 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'ee022 wcrh 8 w71 w70 w61 w60 w51 w50 w41 w40 h'ee023 wcrl 8 w31 w30 w21 w20 w11 w10 w01 w00 h'ee024 bcr 8 icis1 icis0 brome brsts1 brsts0 ? rdea waite h'ee025 ? ? ? ? ? ? ? ? ? h'ee026 drcra 8 dras2 dras1 dras0 ? be rdm srfmd rfshe dram h'ee027 drcrb 8 mxc1 mxc0 csel rcyce ? tpc rcw rlw interface h'ee028 rtmcsr 8 cmf cmie cks2 cks1 cks0 ? ? ? h'ee029 rtcnt 8 h'ee02a rtcor 8 h'ee02b reserved area (access prohibited) h'ee02c h'ee02d h'ee02e h'ee02f h'ee030 ? ? ? ? ? ? ? ? ? h'ee031 ? ? ? ? ? ? ? ? ? h'ee032 ? ? ? ? ? ? ? ? ? h'ee033 ? ? ? ? ? ? ? ? ? h'ee034 ? ? ? ? ? ? ? ? ? h'ee035 ? ? ? ? ? ? ? ? ? h'ee036 ? ? ? ? ? ? ? ? ? h'ee037 ? ? ? ? ? ? ? ? ? h'ee038 ? ? ? ? ? ? ? ? ? h'ee039 ? ? ? ? ? ? ? ? ? h'ee03a ? ? ? ? ? ? ? ? ? h'ee03b ? ? ? ? ? ? ? ? ? h'ee03c reserved area (access prohibited) h'ee03d ? ? ? ? ? ? ? ? ? h'ee03e p4pcr 8 p4 7 pcr p4 6 pcr p4 5 pcr p4 4 pcr p4 3 pcr p4 2 pcr p4 1 pcr p4 0 pcr port 4 h'ee03f reserved area (access prohibited) appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 636 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff20 mar0ar 8 dmac channel 0a h'fff21 mar0ae 8 h'fff22 mar0ah 8 h'fff23 mar0al 8 h'fff24 etcr0ah 8 h'fff25 etcr0al 8 h'fff26 ioar0a 8 h'fff27 dtcr0a 8 dte dtsz dtid rpe dtie dts2 dts1 dts0 short address mode dte dtsz said saide dtie dts2a dts1a dts0a full address mode h'fff28 mar0br 8 dmac channel 0b h'fff29 mar0be 8 h'fff2a mar0bh 8 h'fff2b mar0bl 8 h'fff2c etcr0bh 8 h'fff2d etcr0bl 8 h'fff2e ioar0b 8 h'fff2f dtcr0b 8 dte dtsz dtid rpe dtie dts2 dts1 dts0 short address mode dtme ? daid daide tms dts2b dts1b dts0b full address mode h'fff30 mar1ar 8 dmac channel 1a h'fff31 mar1ae 8 h'fff32 mar1ah 8 h'fff33 mar1al 8 h'fff34 etcr1ah 8 h'fff35 etcr1al 8 h'fff36 ioar1a 8 h'fff37 dtcr1a 8 dte dtsz dtid rpe dtie dts2 dts1 dts0 short address mode dte dtsz said saide dtie dts2a dts1a dts0a full address mode h'fff38 mar1br 8 dmac channel 1b h'fff39 mar1be 8 h'fff3a mar1bh 8 h'fff3b mar1bl 8 h'fff3c etcr1bh 8 h'fff3d etcr1bl 8 h'fff3e ioar1b 8 h'fff3f dtcr1b 8 dte dtsz dtid rpe dtie dts2 dts1 dts0 short address mode dtme ? daid daide tms dts2b dts1b dts0b full address mode appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 637 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff40 ? ? ? ? ? ? ? ? ? h'fff41 ? ? ? ? ? ? ? ? ? h'fff42 ? ? ? ? ? ? ? ? ? h'fff43 ? ? ? ? ? ? ? ? ? h'fff44 ? ? ? ? ? ? ? ? ? h'fff45 ? ? ? ? ? ? ? ? ? h'fff46 ? ? ? ? ? ? ? ? ? h'fff47 ? ? ? ? ? ? ? ? ? h'fff48 ? ? ? ? ? ? ? ? ? h'fff49 ? ? ? ? ? ? ? ? ? h'fff4a ? ? ? ? ? ? ? ? ? h'fff4b ? ? ? ? ? ? ? ? ? h'fff4c ? ? ? ? ? ? ? ? ? h'fff4d ? ? ? ? ? ? ? ? ? h'fff4e ? ? ? ? ? ? ? ? ? h'fff4f ? ? ? ? ? ? ? ? ? h'fff50 ? ? ? ? ? ? ? ? ? h'fff51 ? ? ? ? ? ? ? ? ? h'fff52 ? ? ? ? ? ? ? ? ? h'fff53 ? ? ? ? ? ? ? ? ? h'fff54 ? ? ? ? ? ? ? ? ? h'fff55 ? ? ? ? ? ? ? ? ? h'fff56 ? ? ? ? ? ? ? ? ? h'fff57 ? ? ? ? ? ? ? ? ? h'fff58 ? ? ? ? ? ? ? ? ? h'fff59 ? ? ? ? ? ? ? ? ? h'fff5a ? ? ? ? ? ? ? ? ? h'fff5b ? ? ? ? ? ? ? ? ? h'fff5c ? ? ? ? ? ? ? ? ? h'fff5d ? ? ? ? ? ? ? ? ? h'fff5e ? ? ? ? ? ? ? ? ? h'fff5f ? ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 638 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff60 tstr 8 ? ? ? ? ? str2 str1 str0 h'fff61 tsnc 8 ? ? ? ? ? sync2 sync1 sync0 h'fff62 tmdr 8 ? mdf fdir ? ? pwm2 pwm1 pwm0 16-bit timer, (all channels) h'fff63 tolr 8 ? ? tob2 toa2 tob1 toa1 tob0 toa0 h'fff64 tisra 8 ? imiea2 imiea1 imiea0 ? imfa2 imfa1 imfa0 h'fff65 tisrb 8 ? imieb2 imieb1 imieb0 ? imfb2 imfb1 imfb0 h'fff66 tisrc 8 ? ovie2 ovie1 ovie0 ? ovf2 ovf1 ovf0 h'fff67 h'fff68 16tcr0 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff69 tior0 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 0 h'fff6a 16tcnt0h 16 h'fff6b 16tcnt0l h'fff6c gra0h 16 h'fff6d gra0l h'fff6e grb0h 16 h'fff6f grb0l h'fff70 16tcr1 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff71 tior1 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 1 h'fff72 16tcnt1h 16 h'fff73 16tcnt1l h'fff74 gra1h 16 h'fff75 gra1l h'fff76 grb1h 16 h'fff77 grb1l h'fff78 16tcr2 8 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 16-bit timer h'fff79 tior2 8 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 channel 2 h'fff7a 16tcnt2h 16 h'fff7b 16tcnt2l h'fff7c gra2h 16 h'fff7d gra2l h'fff7e grb2h 16 h'fff7f grb2l appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 639 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fff80 8tcr0 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer h'fff81 8tcr1 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channels 0 h'fff82 8tcsr0 8 cmfb cmfa ovf adte ois3 ois2 os1 os0 and 1 h'fff83 8tcsr1 8 cmfb cmfa ovf ice ois3 ois2 os1 os0 h'fff84 tcora0 8 h'fff85 tcora1 8 h'fff86 tcorb0 8 h'fff87 tcorb1 8 h'fff88 8tcnt0 8 h'fff89 8tcnt1 8 h'fff8a ? ? ? ? ? ? ? ? ? h'fff8b ? ? ? ? ? ? ? ? ? h'fff8c tcsr * 1 8 ovf wt/i t tme ? ? cks2 cks1 cks0 wdt h'fff8d tcnt * 1 8 h'fff8e ? ? ? ? ? ? ? ? ? h'fff8f rstcsr * 1 8 wrst rstoe ? ? ? ? ? ? h'fff90 8tcr2 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer h'fff91 8tcr3 8 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channels 2 h'fff92 8tcsr2 8 cmfb cmfa ovf ? ois3 ois2 os1 os0 and 3 h'fff93 8tcsr3 8 cmfb cmfa ovf ice ois3 ois2 os1 os0 h'fff94 tcora2 8 h'fff95 tcora3 8 h'fff96 tcorb2 8 h'fff97 tcorb3 8 h'fff98 8tcnt2 8 h'fff99 8tcnt3 8 h'fff9a ? ? ? ? ? ? ? ? ? h'fff9b ? ? ? ? ? ? ? ? ? h'fff9c dadr0 8 d/a h'fff9d dadr1 8 converter h'fff9e dacr 8 daoe1 daoe0 dae ? ? ? ? ? h'fff9f ? 8 ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 640 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffa0 tpmr 8 ? ? ? ? g3nov g2nov g1nov g0nov tpc h'fffa1 tpcr 8 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 h'fffa2 nderb 8 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'fffa3 ndera 8 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'fffa4 ndrb * 2 8 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 nder15 nder14 nder13 nder12 ? ? ? ? h'fffa5 ndra * 2 8 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 nder7 nder6 nder5 nder4 ? ? ? ? h'fffa6 ndrb * 2 8 ? ? ? ? ? ? ? ? ? ? ? ? nder11 nder10 nder9 nder8 h'fffa7 ndra * 2 8 ? ? ? ? ? ? ? ? ? ? ? ? nder3 nder2 nder1 nder0 h'fffa8 ? ? ? ? ? ? ? ? ? h'fffa9 ? ? ? ? ? ? ? ? ? h'fffaa ? ? ? ? ? ? ? ? ? h'fffab ? ? ? ? ? ? ? ? ? h'fffac ? ? ? ? ? ? ? ? ? h'fffad ? ? ? ? ? ? ? ? ? h'fffae ? ? ? ? ? ? ? ? ? h'fffaf ? ? ? ? ? ? ? ? ? h'fffb0 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci h'fffb1 brr 8 channel 0 h'fffb2 scr 8 tie rie te re mpie teie cke1 cke0 h'fffb3 tdr 8 h'fffb4 ssr 8 tdre rdrf orer fer/ers per tend mpb mpbt h'fffb5 rdr 8 h'fffb6 scmr 8 ? ? ? ? sdir sinv ? smif h'fffb7 reserved area (access prohibited) h'fffb8 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci h'fffb9 brr 8 channel 1 h'fffba scr 8 tie rie te re mpie teie cke1 cke0 h'fffbb tdr 8 h'fffbc ssr 8 tdre rdrf orer fer/ers per tend mpb mpbt h'fffbd rdr 8 h'fffbe scmr 8 ? ? ? ? sdir sinv ? smif h'fffbf reserved area (access prohibited) appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 641 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffc0 smr 8 c/ a chr pe o/ e stop mp cks1 cks0 sci h'fffc1 brr 8 channel 2 h'fffc2 scr 8 tie rie te re mpie teie cke1 cke0 h'fffc3 tdr 8 h'fffc4 ssr 8 tdre rdrf orer fer/ers per tend mpb mpbt h'fffc5 rdr 8 h'fffc6 scmr 8 ? ? ? ? sdir sinv ? smif h'fffc7 reserved area (access prohibited) h'fffc8 ? ? ? ? ? ? ? ? ? h'fffc9 ? ? ? ? ? ? ? ? ? h'fffca ? ? ? ? ? ? ? ? ? h'fffcb ? ? ? ? ? ? ? ? ? h'fffcc ? ? ? ? ? ? ? ? ? h'fffcd ? ? ? ? ? ? ? ? ? h'fffce ? ? ? ? ? ? ? ? ? h'fffcf ? ? ? ? ? ? ? ? ? h'fffd0 reserved area (access prohibited) h'fffd1 h'fffd2 h'fffd3 p4dr 8 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'fffd4 reserved area (access prohibited) h'fffd5 p6dr 8 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'fffd6 p7dr 8 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'fffd7 p8dr 8 ? ? ? p8 4 p8 3 p8 2 p8 1 p8 0 port 8 h'fffd8 p9dr 8 ? ? p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 port 9 h'fffd9 padr 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 port a h'fffda pbdr 8 pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 port b h'fffdb ? ? ? ? ? ? ? ? ? h'fffdc ? ? ? ? ? ? ? ? ? h'fffdd ? ? ? ? ? ? ? ? ? h'fffde ? ? ? ? ? ? ? ? ? h'fffdf ? ? ? ? ? ? ? ? ? appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 642 of 764 rej09b0396-0500 register name address (low) register name data bus width bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'fffe0 addrah 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d h'fffe1 addral 8 ad1 ad0 ? ? ? ? ? ? converter h'fffe2 addrbh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe3 addrbl 8 ad1 ad0 ? ? ? ? ? ? h'fffe4 addrch 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe5 addrcl 8 ad1 ad0 ? ? ? ? ? ? h'fffe6 addrdh 8 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fffe7 addrdl 8 ad1 ad0 ? ? ? ? ? ? h'fffe8 adcsr 8 adf adie adst scan cks ch2 ch1 ch0 h'fffe9 adcr 8 trge ? ? ? ? ? ? ? legend: wdt: watchdog timer tpc: programmable timing pattern controller sci: serial communication interface notes: 1. for write access to tcsr, tcnt, and rstcsr, see section 12.2.4, notes on register access. 2. the address depends on the output trigger setting. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 643 of 764 rej09b0396-0500 b.2 functions bit initial value r/w: 0 r/w 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 ocide 0 r/w 3 ociae 1 r/w 2 ocibe 1 r/w 1 ovie 0 ? 1 ? timer overflow interrupt enable 0 1 interrupt requested by ovf fla g is disabled interrupt requested by ovf fla g is enabled output compare interrupt b enable 0 1 interrupt requested by ocfb fla g is disabled interrupt requested by ocfb fla g is enabled output compare interrupt a enable 0 1 interrupt requested by ocfa fla g is disabled interrupt requested by ocfa fla g is enabled input capture interrupt d enable 0 1 interrupt requested by icfd fla g is disabled interrupt requested by icfd fla g is enabled tier?timer interrupt enable re g ister h' 90 frt re g ister abbreviation re g ister name address to which re g ister is mapped name of on-chip supportin g module names of the bits. dashes ( ? ) indicate reserved bits. full name of bit descriptions of bit settin g s bit numbers initial bit values possible types of access r w r/w read only write only read and write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 644 of 764 rej09b0396-0500 p4ddr ? port 4 data direction register h'ee003 port 4 bit initial value read/write 0 w 7 p4 7 ddr 0 w 6 p4 6 ddr 0 w 5 p4 5 ddr 0 w 4 p4 4 ddr 0 w 3 p4 3 ddr 0 w 2 p4 2 ddr 0 w 1 p4 1 ddr 0 w 0 p4 0 ddr port 4 input/output select 0 1 generic input generic output p6ddr ? port 6 data direction register h'ee005 port 6 bit 7 ? 6 p6 6 ddr 5 p6 5 ddr 4 p6 4 ddr 3 p6 3 ddr 2 p6 2 ddr 1 p6 1 ddr 0 p6 0 ddr initial value read/write 0 w 1 ? 0 w 0 w 0 w 0 w 0 w 0 w port 6 input/output select 0 1 generic input generic output appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 645 of 764 rej09b0396-0500 p8ddr ? port 8 data direction register h'ee007 port 8 bit 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 p8 4 ddr 3 p8 3 ddr 2 p8 2 ddr 1 p8 1 ddr 0 p8 0 ddr port 8 input/output select 0 1 generic input cs output initial value read/write 0 w 0 w 0 w 0 w modes 1 to 4 1 w port 8 input/output select 0 1 generic input generic output p9ddr ? port 9 data direction register h'ee008 port 9 bit initial value read/write 7 ? 1 ? 6 ? 1 ? 0 w 5 p9 5 ddr 0 w 4 p9 4 ddr 0 w 3 p9 3 ddr 0 w 2 p9 2 ddr 0 w 1 p9 1 ddr 0 w 0 p9 0 ddr port 9 input/output select 0 1 generic input generic output appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 646 of 764 rej09b0396-0500 paddr ? port a data direction register h'ee009 port a bit initial value read/write 7 pa 7 ddr 6 pa 6 ddr 5 pa 5 ddr 4 pa 4 ddr 0 w 3 pa 3 ddr 0 w 2 pa 2 ddr 0 w 1 pa 1 ddr 0 w 0 pa 0 ddr initial value read/write 1 ? 0 w 0 w 0 w 0 w modes 3, 4 modes 1, 2 0 w 0 w port a input/output select 0 1 generic input pin generic output pin 0 w 0 w 0 w 0 w 0 w pbddr ? port b data direction register h'ee00a port b bit initial value read/write 7 pb 7 ddr 0 w 6 pb 6 ddr 0 w 5 pb 5 ddr 0 w 4 pb 4 ddr 0 w 3 pb 3 ddr 0 w 2 pb 2 ddr 0 w 1 pb 1 ddr 0 w 0 pb 0 ddr port b input/output select 0 1 generic input generic output 0 w appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 647 of 764 rej09b0396-0500 mdcr ? mode control register h'ee011 system control bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? ? * r ? * r ? * r 2 mds2 1 mds1 0 mds0 mode select 2 to 0 0 1 0 1 operatin g mode bit 2 md 2 bit 1 md 1 bit 0 md 0 0 1 0 1 ? mode 1 mode 2 mode 3 mode 4 ? ? ? 0 1 0 1 0 1 note: * determined by the state of the mode pins (md2 to md0). appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 648 of 764 rej09b0396-0500 syscr ? system control register h'ee012 system control bit initial value read/write 0 r/w 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 1 r/w 3 ue 0 r/w 2 nmieg 0 r/w 1 ssoe 1 r/w 0 rame nmi ed g e select 0 1 an interrupt is requested at the fallin g ed g e of nmi an interrupt is requested at the risin g ed g e of nmi ram enable 0 1 on-chip ram is disabled on-chip ram is enabled user bit enable 0 1 ccr bit 6 (ui) is used as an interrupt mask bit ccr bit 6 (ui) is used as a user bit standby timer select 2 to 0 bit 6 sts2 waitin g time = 8,192 states waitin g time = 16,384 states waitin g time = 32,768 states waitin g time = 65,536 states waitin g time = 131,072 states waitin g time = 26,2144 states waitin g time = 1,024 states ille g al settin g bit 5 sts1 bit 4 sts0 standby timer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 software standby 0 1 sleep instruction causes transition to sleep mode sleep instruction causes transition to software standby mode software standby output port enable 0 1 in software standby mode, all address bus and bus control si g nals are hi g h- impedance in software standby mode, address bus retains output state and bus control si g nals are fixed hi g h appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 649 of 764 rej09b0396-0500 brcr ? bus release control register h'ee013 bus controller bit 7 a23e 6 a22e 5 a21e 4 a20e 3 ? 2 ? 1 ? 0 brle initial value read/write 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 0 r/w modes 1, 2 address 23 to 20 enable 0 1 address output other input/output bus release enable 0 1 the bus cannot be released to an external device the bus can be released to an external device initial value read/write 1 r/w 1 r/w 1 r/w 0 ? 1 ? 1 ? 1 ? 0 r/w modes 3, 4 iscr ? irq sense control register h'ee014 interrupt controller bit initial value read/write 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 irq5sc 0 r/w 4 irq4sc 0 r/w 3 irq3sc 0 r/w 2 irq2sc 0 r/w 1 irq1sc 0 r/w 0 irq0sc irq 5 to irq 0 sense control 0 1 interrupts are requested when irq 5 to irq 0 are low interrupts are requested by fallin g -ed g e input at irq 5 to irq 0 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 650 of 764 rej09b0396-0500 ier ? irq enable register h'ee015 interrupt controller bit initial value read/write 0 r/w 7 ? 0 r/w 6 ? 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w 0 irq0e irq 5 to irq 0 enable 0 1 irq 5 to irq 0 interrupts are disabled irq 5 to irq 0 interrupts are enabled isr ? irq status register h'ee016 interrupt controller bit initial value read/write 7 ? 0 ? 6 ? 0 ? 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * 0 irq0f irq5 to irq0 flags 0 note: * only 0 can be written, to clear the flag. bits 5 to 0 irq5f to irq0f setting and clearing conditions 1 note: n = 5 to 0 [clearing conditions] ? read irqnf when irqnf = 1, then write 0 in irqnf. ? irqnsc = 0, irqn input is high, and interrupt exception handling is being carried out. ? irqnsc = 1 and irqn interrupt exception handling is being carried out. [setting conditions] ? irqnsc = 0 and irqn input is low. ? irqnsc = 1 and irqn input changes from high to low. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 651 of 764 rej09b0396-0500 ipra ? interrupt priority register a h'ee018 interrupt controller bit initial value read/write 0 r/w 7 ipra7 0 r/w 6 ipra6 0 r/w 5 ipra5 0 r/w 4 ipra4 0 r/w 3 ipra3 0 r/w 2 ipra2 0 r/w 1 ipra1 0 r/w 0 ipra0 priority level a7 to a0 0 1 priority level 0 (low priority) priority level 1 (hi g h priority) ? interrupt sources controlled by each bit ipra bit interrupt source bit 7 ipra7 irq 0 bit 6 ipra6 irq 1 bit 5 ipra5 irq 2 , irq 3 bit 4 ipra4 irq 4 , irq 5 bit 3 ipra3 bit 2 ipra2 bit 1 ipra1 bit 0 ipra0 wdt, dram interface, a/d converter 16-bit timer channel 0 16-bit timer channel 1 16-bit timer channel 2 iprb ? interrupt priority register b h'ee019 interrupt controller bit initial value read/write 0 r/w 7 iprb7 0 r/w 6 iprb6 0 r/w 5 iprb5 0 r/w 4 0 r/w 3 iprb3 0 r/w 2 iprb2 0 r/w 1 iprb1 0 r/w 0 priority level b7 to b5, b3 to b1 0 1 priority level 0 (low priority) priority level 1 (hi g h priority) bit 7 iprb7 bit 6 iprb6 bit 5 iprb5 bit 4 bit 3 iprb3 bit 2 iprb2 bit 1 iprb1 bit 0 8-bit timer channels 0 and 1 8-bit timer channels 2 and 3 dmac sci channel 0 sci channel 1 sci channel 2 ? interrupt sources controlled by each bit iprb bit interrupt source ? ? ? ? ? ? appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 652 of 764 rej09b0396-0500 dastcr ? d/a standby control register h'ee01a d/a converter bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 r/w 0 daste d/a standby enable 0 1 d/a output is disabled in software standby mode d/a output is enabled in software standby mode (initial value) divcr ? division control register h'ee01b system control bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 0 r/w 1 div1 0 r/w 0 div0 divide 1 and 0 frequency division ratio bit 1 div1 bit 0 div0 1/1 1/2 1/4 1/8 0 1 0 1 0 1 (initial value) appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 653 of 764 rej09b0396-0500 mstcrh ? module standby control register h h'ee01c system control 76 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 21 0 pstop mstph2 mstph1 mstph0 r/w r/w r/w r/w 0 00 0 module standby h2 to h0 selection bits for placing modules in standby state. bit initial value read/write reserved bits clock stop enables or disables clock output. mstcrl ? module standby control regist er l h'ee01d system control 76 ? 5 4321 ? 0 mstpl7 mstpl2 mstpl3 mstpl4 mstpl5 mstpl0 r/w r/w r/w r/w r/w r/w r/w r/w 000 0 000 0 module standby l7, l5 to l2, l0 selection bits for placin g modules in standby state. reserved bits bit initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 654 of 764 rej09b0396-0500 cscr ? chip select control regi ster h'ee01f bus controller bit initial value read/write 0 r/w 7 cs7e note: n = 7 to 4 0 r/w 6 cs6e 0 r/w 5 cs5e 0 r/w 4 cs4e 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? chip select 7 to 4 enable description bit n csne output of chip select signal csn is disabled (initial value) output of chip select signal csn is enabled 0 1 abwcr ? bus width control register h'ee020 bus controller bit initial value initial value read/write 1 0 r/w 7 abw7 1 0 r/w 6 abw6 1 0 r/w 5 abw5 1 0 r/w 4 abw4 1 0 r/w 3 abw3 1 0 r/w 2 abw2 1 0 r/w 1 abw1 1 0 r/w 0 abw0 area 7 to 0 bus width control bus width of access area bits 7 to 0 abw7 to abw0 areas 7 to 0 are 16-bit access areas areas 7 to 0 are 8-bit access areas 0 1 modes 1, 3 modes 2, 4 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 655 of 764 rej09b0396-0500 astcr ? access state control regi ster h'ee021 bus controller bit initial value read/write 1 r/w 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w 0 ast0 area 7 to 0 access state control number of states in access area bits 7 to 0 ast7 to ast0 areas 7 to 0 are two-state access areas areas 7 to 0 are three-state access areas 0 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 656 of 764 rej09b0396-0500 wcrh ? wait control register h h'ee022 bus controller 1 r/w 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 2 w50 1 r/w 1 w41 1 r/w 0 w40 0 area 4 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 0 area 5 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 0 area 6 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 0 area 7 wait control 1 and 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 bit initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 657 of 764 rej09b0396-0500 wcrl ? wait control register l h'ee023 bus controller bit initial value read/write 1 r/w 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 2 w10 1 r/w 1 w01 1 r/w 0 w00 area 0 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 area 1 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 area 2 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 area 3 wait control 1 and 0 0 0 1 0 1 no pro g ram wait is inserted 1 pro g ram wait state is inserted 2 pro g ram wait states are inserted 3 pro g ram wait states are inserted 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 658 of 764 rej09b0396-0500 bcr ? bus control register h'ee024 bus controller bit initial value read/write 1 r/w 7 icis1 1 r/w 6 icis0 0 r/w 5 brome 0 r/w 4 brsts1 0 r/w 3 brsts0 1 ? 2 ? 1 r/w 1 rdea 0 r/w 0 waite 0 1 wait pin wait input is disabled wait pin wait input is enabled burst cycle select 1 0 1 burst access cycle comprises 2 states burst access cycle comprises 3 states burst rom enable 0 1 area 0 is a basic bus interface area area 0 is a burst rom interface area idle cycle insertion 0 0 1 no idle cycle is inserted in case of consecutive external read and write cycles idle cycle is inserted in case of consecutive external read and write cycles idle cycle insertion 1 0 1 no idle cycle is inserted in case of consecutive external read cycles for different areas idle cycle is inserted in case of consecutive external read cycles for different areas burst cycle select 0 0 1 max. 4 words in burst access max. 8 words in burst access area division unit select 0 1 area divisions are as follows: areas 0 to 7 are the same size (2 mbytes ) wait pin enable area 0: 2 mbytes area 4: 1.93 mbytes area 1: 2 mbytes area 5: 4 kbytes area 2: 8 mbytes area 6: 23.75 kbytes area 3: 2 mbytes area 7: 22 bytes appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 659 of 764 rej09b0396-0500 drcra ? dram control register a h'ee026 dram interface 7 dras2 0 r/w 6 dras1 0 r/w 5 dras0 0 r/w 4 ? 1 ? 3 be 0 r/w 2 rdm 0 r/w 1 srfmd 0 r/w 0 rfshe 0 r/w bit initial value read/write refresh pin enable 0 1 self-refresh mode 0 1 ras down mode 0 1 burst access enable 0 1 rfsh pin refresh signal output is disabled rfsh pin refresh signal output is enabled dram self-refreshing is disabled in software standby mode dram interface: ras up mode selected dram interface: ras down mode selected burst disabled (always full access) dram space access performed in fast page mode dram area select note: * a single cs n pin serves as a common ras output pin for a number of areas. unused cs n pins can be used as input/output ports. 00 0 10 1 1 10 0 10 1 1 dras2 dras1 dras0 area 5 normal normal normal normal normal dram space ( cs 5 ) area 4 normal normal normal normal dram space ( cs 4 ) dram space ( cs 4 ) area 3 normal normal dram space ( cs 3 ) dram space ( cs 3) dram space ( cs 3 ) area 2 normal dram space ( cs 2 ) dram space ( cs 2 ) dram space ( cs 2 ) dram space ( cs 2 ) dram space( cs 2 ) * dram space( cs 4 ) * dram space( cs 2 ) * dram space( cs 2 ) * dram self-refreshing is enabled in software standby modev appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 660 of 764 rej09b0396-0500 drcrb ? dram control register b h'ee027 dram interface 7 mxc1 0 r/w 6 mxc0 0 r/w 5 csel 0 r/w 4 rcyce 0 r/w 3 ? 1 ? 2 tpc 0 r/w 1 rcw 0 r/w 0 rlw 0 r/w bit initial value read/write refresh cycle wait control 0 1 ras-cas wait tp cycle control 0 1 refresh cycle enable 0 1 wait state (t rw ) insertion is disabled 1 wait state (t rw ) is inserted 1-state precharge cycle is inserted 2-state precharge cycle is inserted refresh cycles are disabled dram refresh cycles are enabled multiplex control 1 and 0 0 0 1 0 1 1 mxc1 mxc0 wait state (t rw ) insertion is disabled 1 wait state (t rw ) is inserted 0 1 cas output pin select 0 1 pb4 and pb5 selected as ucas and lcas output pins hwr and lwr selected as ucas and lcas output pins column address: 8 bits compared address: modes 1, 2 8-bit access space a 19 to a 8 16-bit access space a 19 to a 9 modes 3, 4 8-bit access space a 23 to a 8 16-bit access space a 23 to a 9 column address: 9 bits compared address: modes 1, 2 8-bit access space a 19 to a 9 16-bit access space a 19 to a 10 modes 3, 4 8-bit access space a 23 to a 9 16-bit access space a 23 to a 10 column address: 10 bits compared address: modes 1, 2 8-bit access space a 19 to a 10 16-bit access space a 19 to a 11 modes 3, 4 8-bit access space a 23 to a 10 16-bit access space a 23 to a 11 illegal setting description appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 661 of 764 rej09b0396-0500 rtmcsr ? refresh timer control/status register h'ee028 dram interface 7 cmf 0 r/( w) * 6 cmie 0 r/w 5 cks2 0 4 cks1 0 3 cks0 0 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? bit initial value read/write r/w r/w r/w refresh counter clock select 00 1 0 1 0 1 0 1 0 1 0 1 1 cks2 cks1 cks0 count operation halted /2 used as counter clock /8 used as counter clock /32 used as counter clock /128 used as counter clock /512 used as counter clock /2048 used as counter clock /4096 used as counter clock compare match interrupt enable 0 1 the cmi interrupt requested by the cmf fla g is disabled the cmi interrupt requested by the cmf fla g is enabled compare match fla g 0 1 [clearin g conditions] ? cleared by a reset and in standby mode ? cleared by readin g cmf when cmf = 1, then writin g 0 in cmf [settin g condition] when rtcnt = rtcor description note: * only 0 can be written to clear the fla g . appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 662 of 764 rej09b0396-0500 rtcnt ? refresh timer counter h'ee029 dram interface 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w bit initial value read/write incremented by internal clock selected by bits cks2 to cks0 in rtmcsr rtcor ? refresh time constant register h'ee02a dram interface 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w bit initial value read/write rtcnt compare match period note: only byte a ccess should be used with this register. p4pcr ? port 4 input pull-up control register h'ee03e port 4 bit initial value read/write 0 r/w 7 p4 7 pcr 0 r/w 6 p4 6 pcr 0 r/w 5 p4 5 pcr 0 r/w 4 p4 4 pcr 0 r/w 3 p4 3 pcr 0 r/w 2 p4 2 pcr 0 r/w 1 p4 1 pcr 0 r/w 0 p4 0 pcr port 4 input pull-up control 7 to 0 0 1 input pull-up transistor is off input pull-up transistor is on note: valid when the correspondin g p4ddr bit is cleared to 0 (desi g natin g g eneric input). appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 663 of 764 rej09b0396-0500 mar0a r/e/h/l ? memory address register 0a r/e/h/l h'fff20 h'fff21 dmac0 h'fff22 h'fff23 bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? mar0ar mar0ae undetermined bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mar0ah mar0al undetermined r/w r/w r/w r/w r/w r/w r/w r/w undetermined source or destination address appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 664 of 764 rej09b0396-0500 etcr0a h/l ? execute transfer count register 0a h/l h'fff24 h'fff25 dmac0 ? short address mode ? i/o mode and idle mode bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 undetermined r/w r/w r/w r/w r/w r/w r/w r/w transfer counter ? repeat mode bit initial value read/write 76543210 undetermined r/w r/w r/w r/w r/w r/w r/w r/w transfer counter 76543210 etcr0ah undetermined r/w r/w r/w r/w r/w r/w r/w r/w initial count etcr0al ? full address mode ? normal mode bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w undetermined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w transfer counter ? block transfer mode bit initial value read/write 76543210 undetermined r/w r/w r/w r/w r/w r/w r/w r/w block size counter 76543210 etcr0ah undetermined r/w r/w r/w r/w r/w r/w r/w r/w initial block size etcr0al appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 665 of 764 rej09b0396-0500 ioar0a ? i/o address register 0a h'fff26 dmac0 bit initial value read/write r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 short address mode : source or destination address full address mode : not used undetermined appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 666 of 764 rej09b0396-0500 dtcr0a ? data transfer control register 0a h'fff27 dmac0 ? short address mode bit initial value read/write 0 r/w 7 dte 0 r/w 6 dtsz 0 r/w 5 dtid 0 r/w 4 rpe 0 r/w 3 dtie 0 r/w 2 dts2 0 r/w 1 dts1 0 r/w 0 dts0 data transfer interrupt enable 0 interrupt requested by dte bit is disabled 1 interrupt requested by dte bit is enabled repeat enable 0 i/o mode 1 repeat mode idle mode 0 1 rpe dtie description 0 1 data transfer increment/decrement 0 incremented: if dtsz = 0, mar is incremented by 1 after each transfer if dtsz = 1, mar is incremented by 2 after each transfer 1 decremented: if dtsz = 0, mar is decremented by 1 after each transfer if dtsz = 1, mar is decremented by 2 after each transfer data transfer size 0 1 byte-size transfer word-size transfer data transfer enable 0 1 data transfer is disabled data transfer is enabled data transfer select bit 2 dts2 bit 1 dts1 bit 0 dts0 0 1 compare match/input capture a interrupt from 16-bit timer channel 0 compare match/input capture a interrupt from 16-bit timer channel 1 compare match/input capture a interrupt from 16-bit timer channel 2 a/d converter conversion end interrupt sci0 transmit-data-empty interrupt sci0 receive-data-full interrupt transfer in full address mode transfer in full address mode 0 1 0 1 0 1 0 1 data transfer activation source 0 1 0 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 667 of 764 rej09b0396-0500 dtcr0a ? data transfer control register 0a (cont) h'fff27 dmac0 ? full address mode bit initial value read/write 0 r/w 7 dte 0 r/w 6 dtsz 0 r/w 5 said 0 r/w 4 saide 0 r/w 3 dtie 0 r/w 2 dts2a 0 r/w 1 dts1a 0 r/w 0 dts0a data transfer select 0a bit 4 saide 0 mara is held fixed incremented: if dtsz = 0, mara is incremented by 1 after each transfer if dtsz = 1, mara is incremented by 2 after each transfer 0 1 increment/decrement enable data transfer size 0 1 byte-size transfer word-size transfer data transfer enable 0 1 data transfer is disabled data transfer is enabled 0 1 normal mode block transfer mode data transfer select 2a and 1a set both bits to 1 data transfer interrupt enable 0 1 interrupt requested by dte bit is disabled interrupt requested by dte bit is enabled source address increment/decrement (bit 5) source address increment/decrement enable (bit 4) 1 0 1 mara is held fixed decremented: if dtsz = 0, mara is decremented by 1 after each transfer if dtsz = 1, mara is decremented by 2 after each transfer bit 5 said appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 668 of 764 rej09b0396-0500 mar0b r/e/h/l ? memory address register 0b r/e/h/l h'fff28 h'fff29 dmac0 h'fff2a h'fff2b bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? mar0br mar0be undetermined bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mar0bh mar0bl undetermined r/w r/w r/w r/w r/w r/w r/w r/w undetermined source or destination address appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 669 of 764 rej09b0396-0500 etcr0b h/l ? execute transfer count register 0b h/l h'fff2c, h'fff2d dmac0 ? short address mode ? i/o mode and idle mode r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write undetermined transfer counter ? repeat mode : 76543210 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write undetermined transfer counter etcr0bh undetermined initial count etcr0bl ? full address mode ? normal mode bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w undetermined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w not used ? block transfer mode bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w undetermined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w block transfer counter appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 670 of 764 rej09b0396-0500 ioar0b ? i/o address register 0b h'fff2e dmac0 bit initial value read/write r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 short address mode : source or destination address full address mode : not used undetermined appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 671 of 764 rej09b0396-0500 dtcr0b ? data transfer control register 0b h'fff2f dmac0 ? short address mode bit initial value read/write 0 r/w 7 dte 0 r/w 6 dtsz 0 r/w 5 dtid 0 r/w 4 rpe 0 r/w 3 dtie 0 r/w 2 dts2 0 r/w 1 dts1 0 r/w 0 dts0 data transfer select bit 2 dts2 bit 1 dts1 bit 0 dts0 1 0 1 0 1 compare match/input capture a interrupt from 16-bit timer channel 0 compare match/input capture a interrupt from 16-bit timer channel 1 compare match/input capture a interrupt from 16-bit timer channel 2 a/d converter conversion end interrupt sci0 transmit-data-empty interrupt sci0 receive-data-full interrupt falling edge of dreq input low level of dreq input 0 1 0 1 0 1 data transfer activation source data transfer interrupt enable 0 interrupt requested by dte bit is disabled 1 interrupt requested by dte bit is enabled repeat enable 0 i/o mode 1 repeat mode idle mode 0 1 rpe dtie description 0 1 data transfer increment/decrement 0 incremented: if dtsz = 0, mar is incremented by 1 after each transfer if dtsz = 1, mar is incremented by 2 after each transfer 1 decremented: if dtsz = 0, mar is decremented by 1 after each transfer if dtsz = 1, mar is decremented by 2 after each transfer data transfer size 0 1 byte-size transfer word-size transfer data transfer enable 0 1 data transfer is disabled data transfer is enabled 0 1 0 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 672 of 764 rej09b0396-0500 dtcr0b ? data transfer control register 0b (cont) h'fff2f dmac0 ? full address mode bit initial value read/write 0 r/w 7 dtme 0 r/w 6 ? 0 r/w 5 daid 0 r/w 4 daide 0 r/w 3 tms 0 r/w 2 dts2b 0 r/w 1 dts1b 0 r/w 0 dts0b data transfer select 2b to 0b bit 2 dts2b bit 1 dts1b bit 0 dts0b 0 0 1 0 1 data transfer activation source transfer mode select 0 1 destination is the block area in block transfer mode source is the block area in block transfer mode data transfer master enable 0 1 data transfer is disabled data transfer is enabled compare match/input capture a interrupt from 16-bit timer channel 0 normal mode block transfer mode auto-request (burst mode) compare match/input capture a interrupt from 16-bit timer channel 1 not available compare match/input capture a interrupt from 16-bit timer channel 2 auto-request (cycle-steal mode) a/d converter conversion end interrupt not available not available fallin g ed g e of dreq input not available not available not available not available fallin g ed g e of dreq input low level input at dreq input 0 1 0 1 0 bit 4 daide 0 marb is held fixed incremented: if dtsz = 0, marb is incremented by 1 after each transfer if dtsz = 1, marb is incremented by 2 after each transfer marb is held fixed decremented: if dtsz = 0, marb is decremented by 1 after each transfer if dtsz = 1, marb is decremented by 2 after each transfer 0 1 increment/decrement enable destination address increment/decrement (bit 5) destination address increment/decrement enable (bit 4) 1 0 1 bit 5 daid 1 0 1 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 673 of 764 rej09b0396-0500 mar1a r/e/h/l ? memory address register 1a r/e/h/l h'fff30 h'fff31 dmac1 h'fff32 h'fff33 bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? mar1ar mar1ae undetermined bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mar1ah mar1al undetermined r/w r/w r/w r/w r/w r/w r/w r/w undetermined note: bit functions are the same as for dmac0. etcr1a h/l ? execute transfer count register 1a h/l h'fff34 h'fff35 dmac1 bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 undetermined note: bit functions are the same as for dmac0. r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write 76543210 undetermined r/w r/w r/w r/w r/w r/w r/w r/w 76543210 etcr1ah undetermined r/w r/w r/w r/w r/w r/w r/w r/w etcr1al appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 674 of 764 rej09b0396-0500 ioar1a ? i/o address register 1a h'fff36 dmac1 bit initial value read/write r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 note: bit functions are the same as for dmac0. undetermined dtcr1a ? data transfer control register 1a h'fff37 dmac1 ? short address mode bit initial value read/write 0 r/w 7 dte 0 r/w 6 dtsz 0 r/w 5 dtid 0 r/w 4 rpe 0 r/w 3 dtie 0 r/w 2 dts2 0 r/w 1 dts1 0 r/w 0 dts0 ? full address mode bit initial value read/write 0 r/w 7 dte 0 r/w 6 dtsz 0 r/w 5 said 0 r/w 4 saide 0 r/w 3 dtie 0 r/w 2 dts2a 0 r/w 1 dts1a 0 r/w 0 dts0a note: bit functions are the same as for dmac0. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 675 of 764 rej09b0396-0500 mar1b r/e/h/l ? memory address register 1b r/e/h/l h'fff38 h'fff39 dmac1 h'fff3a h'fff3b bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? mar1br mar1be undetermined bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mar1bh mar1bl undetermined r/w r/w r/w r/w r/w r/w r/w r/w undetermined note: bit functions are the same as for dmac0. etcr1b h/l ? execute transfer count register 1b h/l h'fff3c h'fff3d dmac1 bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 undetermined note: bit functions are the same as for dmac0. r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write 76543210 undetermined r/w r/w r/w r/w r/w r/w r/w r/w 76543210 etcr1bh undetermined r/w r/w r/w r/w r/w r/w r/w r/w etcr1bl appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 676 of 764 rej09b0396-0500 ioar1b ? i/o address register 1b h'fff3e dmac1 note: bit functions are the same as for dmac0. r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 bit initial value read/write undetermined dtcr1b ? data transfer control register 1b h'fff3f dmac1 ? short address mode r/w 7 dte 0 r/w 6 dtsz 0 r/w 5 dtid 0 r/w 4 rpe 0 r/w 3 dtie 0 r/w 2 dts2 0 r/w 1 dts1 0 r/w 0 dts0 0 bit initial value read/write ? full address mode note: bit functions are the same as for dmac0. r/w 7 dtme 0 r/w 6 0 r/w 5 daid 0 r/w 4 daide 0 r/w 3 tms 0 r/w 2 dts2b 0 r/w 1 dts1b 0 0 r/w 0 dts0b bit initial value read/write ? appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 677 of 764 rej09b0396-0500 tstr ? timer start register h'fff60 16-bit timer (common) 7 ? 1 ? 6 ? 1 ? reserved bits 0 1 0 1 0 1 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? r/w 2 str2 0 r/w 1 str1 0 r/w 0 str0 0 bit counter start 1 counter start 2 counter start 0 16tcnt0 count halted (initial value) 16tcnt0 countin g 16tcnt1 count halted (initial value) 16tcnt1 countin g 16tcnt2 count halted (initial value) 16tcnt2 countin g initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 678 of 764 rej09b0396-0500 tsnc ? timer syncro register h'fff61 16-bit timer (common) 7 ? 1 ? 6 ? 1 ? reserved bits 0 1 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? r/w 2 sync2 0 r/w 1 sync1 0 r/w 0 sync0 0 bit timer sync 0 channel 0 timer counter (16tcnt0) operates independently (16tcnt0 presettin g /clearin g unrelated to other channels) (initial value) channel 0 operates synchronously 16tcnt0 synchronous presettin g /synchronous clearin g possible initial value read/write 0 1 timer sync 1 channel 1 timer counter (16tcnt1) operates independently (16tcnt1 presettin g /clearin g unrelated to other channels) (initial value) channel 1 operates synchronously 16tcnt1 synchronous presettin g /synchronous clearin g possible 0 1 timer sync 2 channel 2 timer counter (16tcnt2) operates independently (16tcnt2 presettin g /clearin g unrelated to other channels) (initial value) channel 2 operates synchronously 16tcnt2 synchronous presettin g /synchronous clearin g possible appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 679 of 764 rej09b0396-0500 tmdr ? timer mode register h'fff62 16-bit timer (common) 7 ? 1 ? r/w 6 mdf 0 r/w 0 1 5 fdir 0 4 ? 1 ? 3 ? 1 ? 0 r/w 2 pwm2 r/w 1 pwm1 0 r/w 0 pwm0 0 bit pwm mode 0 normal operation selected for channel 0 (initial value) pwm mode selected for channel 0 initial value read/write 0 1 pwm mode 1 normal operation selected for channel 1 (initial value) pwm mode selected for channel 1 0 1 pwm mode 2 normal operation selected for channel 2 (initial value) pwm mode selected for channel 2 fla g direction tisrc ovf fla g set to 1 when 16tcnt2 overflows or underflows (initial value) tisrc ovf fla g set to 1 when 16tcnt2 overflows 0 1 phase countin g mode normal operation selected for channel 2 (initial value) phase countin g mode selected for channel 2 0 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 680 of 764 rej09b0396-0500 tolr ? timer output level setting register h'fff63 16-bit timer (common) 7 ? 1 ? 6 ? 1 ? w 0 1 5 tob2 0 w 4 toa2 0 w 3 tob1 0 0 w 2 toa1 w 1 tob0 0 w 0 toa0 0 bit output level settin g a0 tioca0 set to 0 output (initial value) tioca0 set to 1 output initial value read/write 0 1 output level settin g b0 tiocb0 set to 0 output (initial value) tiocb0 set to 1 output 0 1 output level settin g a1 tioca1 set to 0 output (initial value) tioca1 set to 1 output 0 1 output level settin g b1 tiocb1 set to 0 output (initial value) tiocb1 set to 1 output 0 1 output level settin g a2 tioca2 set to 0 output (initial value) tioca2 set to 1 output 0 1 output level settin g b2 tiocb2 set to 0 output (initial value) tiocb2 set to 1 output appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 681 of 764 rej09b0396-0500 tisra ? timer interrupt status register a h'fff64 16-bit timer (common) 7 ? 1 ? 6 imiea2 0 r/w 5 imiea1 0 r/w 4 imiea0 0 3 ? 1 ? 2 imfa2 0 r/(w) * 1 imfa1 0 r/(w) * 0 imfa0 0 r/(w) * bit initial value read/write r/w input capture/compare match flag a0 0 1 [clearing conditions] (initial value) ? read imfa0 when imfa0 =1, then write 0 in imfa0 ? dmac activated by imia0 interrupt [setting conditions] ? 16tcnt0 = gra0 when gra0 functions as an output compare register. ? 16tcnt0 value is transferred to gra0 by an input capture signal when gra0 functions as an input capture register. input capture/compare match flag a1 0 1 [clearing conditions] (initial value) ? read imfa1 when imfa1 =1, then write 0 in imfa1 ? dmac activated by imia1 interrupt [setting conditions] ? 16tcnt1 = gra1 when gra1 functions as an output compare register ? 16tcnt1 value is transferred to gra1 by an input capture signal when gra1 functions as an input capture register input capture/compare match flag a2 0 1 [clearing conditions] (initial value) ? read imfa2 when imfa2 =1, then write 0 in imfa2 ? dmac activated by imia2 interrupt [setting conditions] ? 16tcnt2 = gra2 when gra2 functions as an output compare register ? 16tcnt2 value is transferred to gra2 by an input capture signal when gra2 functions as an input capture register input capture/compare match interrupt enable a0 0 1 imia0 interrupt requested by imfa0 flag is disabled (initial value) imia0 interrupt requested by imfa0 flag is enabled input capture/compare match interrupt enable a1 0 1 imia1 interrupt requested by imfa1 flag is disabled (initial value) imia1 interrupt requested by imfa1 flag is enabled input capture/compare match interrupt enable a2 0 1 imia2 interrupt requested by imfa2 flag is disabled (initial value) imia2 interrupt requested by imfa2 flag is enabled note: * only 0 can be written, to clear the flag. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 682 of 764 rej09b0396-0500 tisrb ? timer interrupt status register b h'fff65 16-bit timer (common) 7 ? 1 ? 6 imieb2 0 r/w 5 imieb1 0 r/w 4 imieb0 0 3 ? 1 ? 2 imfb2 0 r/(w) * 1 imfb1 0 r/(w) * 0 imfb0 0 r/(w) * bit initial value read/write r/w input capture/compare match fla g b0 0 1 [clearin g condition] (initial value) read imfb0 when imfb0 =1, then write 0 in imfb0 [settin g conditions] ? 16tcnt0 = grb0 when grb0 functions as an output compare re g ister. ? 16tcnt0 value is transferred to grb0 by an input capture si g nal when grb0 functions as an input capture re g ister. input capture/compare match fla g b1 0 1 [clearin g condition] (initial value) read imfb1 when imfb1 =1, then write 0 in imfb1 [settin g conditions] ? 16tcnt1 = grb1 when grb1 functions as an output compare re g ister ? 16tcnt1 value is transferred to grb1 by an input capture si g nal when grb1 functions as an input capture re g ister input capture/compare match fla g b2 0 1 [clearin g condition] (initial value) read imfb2 when imfb2 =1, then write 0 in imfb2 [settin g conditions] ? 16tcnt2 = grb2 when grb2 functions as an output compare re g ister ? 16tcnt2 value is transferred to grb2 by an input capture si g nal when grb2 functions as an input capture re g ister input capture/compare match interrupt enable b0 0 1 imib0 interrupt requested by imfb0 fla g is disabled (initial value) imib0 interrupt requested by imfb0 fla g is enabled input capture/compare match interrupt enable b1 0 1 imib1 interrupt requested by imfb1 fla g is disabled (initial value) imib1 interrupt requested by imfb1 fla g is enabled input capture/compare match interrupt enable b2 0 1 imib2 interrupt requested by imfb2 fla g is disabled (initial value) imib2 interrupt requested by imfb2 fla g is enabled note: * only 0 can be written, to clear the fla g . appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 683 of 764 rej09b0396-0500 tisrc ? timer interrupt status register c h'fff66 16-bit timer (common) 7 ? 1 ? 6 ovie2 0 r/w 5 ovie1 0 r/w 4 ovie0 0 3 ? 1 ? 2 ovf2 0 r/(w) * 1 ovf1 0 r/(w) * 0 ovf0 0 r/(w) * bit initial value read/write r/w 0 overflow fla g 0 [clearin g condition] (initial value) read ovf0 when ovf0 =1, then write 0 in ovf0 1 [settin g condition] 16tcnt0 overflowed from h'ffff to h'0000 0 overflow fla g 1 [clearin g condition] (initial value) read ovf1 when ovf1 =1, then write 0 in ovf1 1 [settin g condition] 16tcnt1 overflowed from h'ffff to h'0000 0 overflow fla g 2 [clearin g condition] (initial value) read ovf2 when ovf2 =1, then write 0 in ovf2 1 [settin g condition] 16tcnt2 overflowed from h'ffff to h'0000 or underflowed from h'0000 to h'ffff 0 overflow interrupt enable 0 ovi0 interrupt requested by ovf0 fla g is disabled (initial value) 1 ovi0 interrupt requested by ovf0 fla g is enabled 0 overflow interrupt enable 1 ovi1 interrupt requested by ovf1 fla g is disabled (initial value) 1 ovi1 interrupt requested by ovf1 fla g is enabled 0 overflow interrupt enable 2 ovi2 interrupt requested by ovf2 fla g is disabled (initial value) 1 ovi2 interrupt requested by ovf2 fla g is enabled note: * only 0 can be written, to clear the fla g . appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 684 of 764 rej09b0396-0500 16tcr0 ? timer control register 0 h'fff68 16-bit timer channel 0 7 ? 1 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 3 ckeg0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w 0 tpsc0 0 r/w bit initial value read/write r/w timer prescaler 2 to 0 bit 2 tpsc2 description bit 1 tpsc1 internal clock: counts on (initial value) internal clock: counts on /2 internal clock: counts on /4 internal clock: counts on /8 external clock a: counts on tclka pin input external clock b: counts on tclkb pin input external clock c: counts on tclkc pin input external clock d: counts on tclkd pin input bit 0 tpsc0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 clock ed g e 1 and 0 bit 4 ckeg1 description bit 3 ckeg0 counts on risin g ed g e (initial value) counts on fallin g ed g e counts on both risin g and fallin g ed g es 0 1 ? 0 0 1 counter clear 1 and 0 bit 6 cclr1 description bit 5 cclr0 16tcnt clearin g disabled (initial value) 16tcnt cleared by gra compare match/input capture 16tcnt cleared by grb compare match/input capture synchronous clear. 16tcnt cleared in synchronization with counter clearin g of other timers operatin g synchronously. 0 1 0 1 0 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 685 of 764 rej09b0396-0500 tior0 ? timer i/o control register 0 h'fff69 16-bit timer channel 0 7 ? 1 ? 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 3 ? 1 ? 2 ioa2 0 r/w 1 ioa1 0 r/w 0 ioa0 0 r/w bit initial value read/write r/w i/o control a2 to a0 bit 2 ioa2 description bit 1 ioa1 gra is output compare register pin output at compare match disabled (initial value) 0 output at gra compare match 1 output at gra compare match toggle output at gra compare match (1 output on channel 2 only) bit 0 ioa0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 i/o control b2 to b0 bit 6 iob2 description bit 5 iob1 grb is output compare register pin output at compare match disabled (initial value) 0 output at grb compare match 1 output at grb compare match toggle output at grb compare match (1 output on channel 2 only) bit 4 iob0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 gra is input capture register input capture in gra at rising edge input capture in gra at falling edge input capture at both rising and falling edges grb is input capture register input capture in grb at rising edge input capture in grb at falling edge input capture at both rising and falling edges 16tcnt0h/l ? timer counter 0h/l h'fff6a 16-bit timer channel 0 h'fff6b bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 up-counter 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 686 of 764 rej09b0396-0500 gra0h/l ? general register a0 h/l h'fff6c 16-bit timer channel 0 h'fff6d bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 output compare/input capture dual-function re g ister 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w grb0h/l ? general register b0 h/l h'fff6e 16-bit timer channel 0 h'fff6f bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 output compare/input capture dual-function re g ister 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 16tcr1 ? timer control register 1 h'fff70 16-bit timer channel 1 bit initial value read/write 0 r/w 7 ? 1 ? 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 3 ckeg0 2 tpsc2 1 tpsc1 0 r/w 0 r/w 0 r/w 0 tpsc0 note: bit functions are the same as for 16-bit timer channel 0. tior1 ? timer i/o control register 1 h'fff71 16-bit timer channel 1 bit initial value read/write 7 ? 1 ? 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 3 ? 1 ? 2 ioa2 1 ioa1 0 r/w 0 r/w 0 r/w 0 ioa0 note: bit functions are the same as for 16-bit timer channel 0. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 687 of 764 rej09b0396-0500 16tcnt1h/l ? timer counter 1h/l h'fff72 16-bit timer channel 1 h'fff73 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w note: bit functions are the same as for 16-bit timer channel 0. gra1h/l ? general register a1 h/l h'fff74 16-bit timer channel 1 h'fff75 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. grb1h/l ? general register b1 h/l h'fff76 16-bit timer channel 1 h'fff77 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. 16tcr2 ? timer control register 2 h'fff78 16-bit timer channel 2 bit initial value read/write 0 r/w 7 ? 1 ? 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 3 ckeg0 2 tpsc2 1 tpsc1 0 r/w 0 r/w 0 r/w 0 tpsc0 notes: 1. bit functions are the same as for 16-bit timer channel 0. 2. the settin g s of bits ckeg1 and ckeg0 and bits tpsc2 to tpsc0 in 16tcr2 are invalid when phase countin g mode is selected for channel 2. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 688 of 764 rej09b0396-0500 tior2 ? timer i/o control register 2 h'fff79 16-bit timer channel 2 bit initial value read/write 7 ? 1 ? 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 3 ? 1 ? 2 ioa2 1 ioa1 0 r/w 0 r/w 0 r/w 0 ioa0 note: bit functions are the same as for 16-bit timer channel 0. 16tcnt2h/l ? timer counter 2h/l h'fff7a 16-bit timer channel 2 h'fff7b bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 phase countin g mode: up/down-counter other modes: up-counter 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w gra2h/l ? general register a2 h/l h'fff7c 16-bit timer channel 2 h'fff7d bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. grb2h/l ? general register b2 h/l h'fff7e 16-bit timer channel 2 h'fff7f bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w note: bit functions are the same as for 16-bit timer channel 0. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 689 of 764 rej09b0396-0500 8tcr0 ? timer control register 0 h'fff80 8-bit timer channel 0 8tcr1 ? timer control register 1 h'fff81 8-bit timer channel 1 bit initial value read/write 0 r/w 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 clock select 2 to 0 0 0 0 1 0 1 0 0 1 1 0 1 1 clock input is disabled internal clock, counted on risin g ed g e of /8 internal clock, counted on risin g ed g e of /64 internal clock, counted on risin g ed g e of /8192 external clock, counted on fallin g ed g e external clock, counted on risin g ed g e external clock, counted on both risin g and fallin g ed g es counter clear 1 and 0 0 0 1 0 1 clearin g is disabled cleared by compare match a cleared by compare match b/input capture b cleared by input capture b 1 timer overflow interrupt enable 0 1 ovi interrupt requested by ovf is disabled ovi interrupt requested by ovf is enabled compare match interrupt enable a 0 1 cmia interrupt requested by cmfa is disabled cmia interrupt requested by cmfa is enabled compare match interrupt enable b 0 1 cmib interrupt requested by cmfb is disabled cmib interrupt requested by cmfb is enabled 1 channel 0: count on 8tcnt1 overflow si g nal * channel 1: count on 8tcnt0 compare match a * note: * if the clock input of channel 0 is the 8tcnt1 overflow si g nal and that of channel 1 is the 8tcnt0 compare match si g nal, no incrementin g clock is g enerated. do not use this settin g . appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 690 of 764 rej09b0396-0500 8tcsr0 ? timer control/status register 0 h'fff82 8-bit timer channel 0 output select a1 and a0 0 description description description bit 1 os1 bit 0 os0 ice in 8tcsr1 bit 3 ois3 bit 4 adte trge * bit 2 ois2 1 0 1 no change at compare match a 0 output at compare match a 1 output at compare match a output toggles at compare match a output/input capture edge select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 1 no change at compare match b 0 output at compare match b 1 output at compare match b output toggles at compare match b tcorb input capture on rising edge tcorb input capture on falling edge tcorb input capture on both rising and falling edges 1 a/d trigger enable 0 0 1 0 1 a/d converter start requests by compare match a or an external trigger are disabled a/d converter start requests by compare match a or an external trigger are enabled a/d converter start requests by an external trigger are enabled, and a/d converter start requests by compare match a are disabled a/d converter start requests by compare match a are enabled, and a/d converter start requests by an external trigger are disabled timer overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf. bit initial value read/write 0 r/(w) * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/w 4 adte 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 0 1 1 [setting condition] 8tcnt overflows from h'ff to h'00. compare match flag a 0 [clearing condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [setting condition] 8tcnt = tcora compare match/input capture flag b 0 [clearing condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [setting conditions] ? 8tcnt = tcorb ? the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register. note: * only 0 can be written to bits 7 to 5, to clear these flags. note: * trge is bit 7 of the a/d control register (adcr). 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 691 of 764 rej09b0396-0500 8tcsr1 ? timer control/status register 1 h'fff83 8-bit timer channel 1 output select a1 and a0 0 description description bit 1 os1 bit 0 os0 ice in 8tcsr1 bit 3 ois3 bit 2 ois2 1 0 1 no change at compare match a 0 output at compare match a 1 output at compare match a output toggles at compare match a output/input capture edge select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 1 no change at compare match b 0 output at compare match b 1 output at compare match b output toggles at compare match b tcorb input capture on rising edge tcorb input capture on falling edge tcorb input capture on both rising and falling edges 1 timer overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf. 0 1 1 [setting condition] 8tcnt overflows from h'ff to h'00. compare match flag a 0 [clearing condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [setting condition] 8tcnt = tcora compare match/input capture flag b 0 [clearing condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [setting conditions] ? 8tcnt = tcorb ? the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register. note: * only 0 can be written to bits 7 to 5, to clear these flags. bit initial value read/write 0 r/(w) * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/w 4 ice 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 input capture enable 0 1 tcorb is a compare match register tcorb is an input capture register appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 692 of 764 rej09b0396-0500 tcora0 ? timer constant register a0 h'fff84 8-bit timer channel 0 tcora1 ? timer constant register a1 h'fff85 8-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcora0 tcora1 tcorb0 ? timer constant register b0 h'fff86 8-bit timer channel 0 tcorb1 ? timer constant register b1 h'fff87 8-bit timer channel 1 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcorb0 tcorb1 8tcnt0 ? timer counter 0 h'fff88 8-bit timer channel 0 8tcnt1 ? timer counter 1 h'fff89 8-bit timer channel 1 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 8tcnt0 8tcnt1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 693 of 764 rej09b0396-0500 tcsr ? timer control/status register h'fff8c wdt bit initial value read/write 0 r/(w) * 7 ovf 0 r/w 6 wt/ it 0 r/w 5 tme 4 ? 1 ? 3 ? 1 ? 0 r/w 2 cks2 0 r/w 1 cks1 clock select 2 to 0 0 0 /2 /32 /64 /128 /256 /512 /2048 /4096 1 0 cks0 0 r/w 0 1 0 1 0 1 0 1 1 0 1 timer enable 0 timer disabled ? tcnt is initialized to h'00 and halted 1 timer enabled ? tcnt is counting timer mode select 0 interval timer: requests interval timer interrupts 1 watchdog timer: generates a reset signal overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 1 [setting condition] tcnt changes from h'ff to h'00 note: * only 0 can be written, to clear the flag. cks2 cks1 cks0 description appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 694 of 764 rej09b0396-0500 tcnt ? timer counter h'fff8d (read), h'fff8c (write) wdt bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 count value rstcsr ? reset control/status register h' fff8f (read), h'fff8e (write) wdt bit initial value read/write 0 r/(w) * 7 wrst 0 r/w 6 rstoe 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? reset output enable 0 external output of reset signal is disabled external output of reset signal is enabled 1 watchdog timer reset 0 [clearing conditions] ? reset signal at res pin ? read wrst when wrst = 1, then write 0 in wrst 1 [setting condition] tcnt overflow generates a reset signal note: * only 0 can be written in bit 7, to clear the flag. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 695 of 764 rej09b0396-0500 8tcr2 ? timer control register 2 h'fff90 8-bit timer channel 2 8tcr3 ? timer control register 3 h'fff91 8-bit timer channel 3 bit initial value read/write 0 r/w 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 0 cks0 clock select 2 to 0 0 0 0 1 0 1 0 0 1 1 0 1 1 clock input is disabled internal clock, counted on risin g ed g e of /8 internal clock, counted on risin g ed g e of /64 internal clock, counted on risin g ed g e of /8192 external clock, counted on fallin g ed g e external clock, counted on risin g ed g e external clock, counted on both risin g and fallin g ed g es counter clear 1 and 0 0 0 1 0 1 clearin g is disabled cleared by compare match a cleared by compare match b/input capture b cleared by input capture b 1 timer overflow interrupt enable 0 1 ovi interrupt requested by ovf is disabled ovi interrupt requested by ovf is enabled compare match interrupt enable a 0 1 cmia interrupt requested by cmfa is disabled cmia interrupt requested by cmfa is enabled compare match interrupt enable b 0 1 cmib interrupt requested by cmfb is disabled cmib interrupt requested by cmfb is enabled 1 cks2 cks1 cks0 description channel 2: count on 8tcnt3 overflow si g nal * channel 3: count on 8tcnt2 compare match a * note: * if the clock input of channel 2 is the 8tcnt3 overflow si g nal and that of channel 3 is the 8tcnt2 compare match si g nal, no incrementin g clock is g enerated. do not use this settin g . appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 696 of 764 rej09b0396-0500 8tcsr2 ? timer control/status register 2 h'fff92 8-bit timer channel 2 8tcsr3 ? timer control/status register 3 h'fff93 8-bit timer channel 3 bit initial value read/write 0 r/(w) * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/w 4 ice 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 timer overflow flag 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf. bit initial value read/write 0 r/(w) * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 4 ? 1 ? 0 r/w 3 ois3 0 r/w 2 ois2 0 r/w 1 os1 0 r/w 0 os0 8tcsr3 8tcsr2 1 [setting condition] 8tcnt overflows from h'ff to h'00. compare match/input capture flag a 0 [clearing condition] read cmfa when cmfa = 1, then write 0 in cmfa. 1 [setting condition] 8tcnt = tcora compare match/input capture flag b 0 [clearing condition] read cmfb when cmfb = 1, then write 0 in cmfb. 1 [setting conditions] ? 8tcnt = tcorb ? the 8tcnt value is transferred to tcorb by an input capture signal when tcorb functions as an input capture register. note: * only 0 can be written to bits 7 to 5, to clear these flags. output select a1 and a0 0 description bit 1 os1 bit 0 os0 1 0 1 no change at compare match a 0 output at compare match a 1 output at compare match a output toggles at compare match a 0 1 description ice in 8tcsr3 bit 3 ois3 bit 2 ois2 output/input capture edge select b3 and b2 0 0 1 0 1 0 1 0 1 0 1 0 1 no change at compare match b 0 output at compare match b 1 output at compare match b output toggles at compare match b tcorb input capture on rising edge tcorb input capture on falling edge tcorb input capture on both rising and falling edges 1 input capture enable 0 1 tcorb is a compare match register tcorb is an input capture register appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 697 of 764 rej09b0396-0500 tcora2 ? timer constant register a2 h'fff94 8-bit timer channel 2 tcora3 ? timer constant register a3 h'fff95 8-bit timer channel 3 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcora2 tcora3 tcorb2 ? timer constant register b2 h'fff96 8-bit timer channel 2 tcorb3 ? timer constant register b3 h'fff97 8-bit timer channel 3 bit initial value read/write 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w tcorb2 tcorb3 8tcnt2 ? timer counter 2 h'fff98 8-bit timer channel 2 8tcnt3 ? timer counter 3 h'fff99 8-bit timer channel 3 bit initial value read/write 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 8tcnt2 8tcnt3 dadr0 ? d/a data register 0 h'fff9c d/a bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 d/a conversion data appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 698 of 764 rej09b0396-0500 dadr1 ? d/a data register 1 h'fff9d d/a bit initial value read/write 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 d/a conversion data appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 699 of 764 rej09b0396-0500 dacr ? d/a control register h'fff9e d/a bit initial value read/write 0 r/w 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? d/a enable bit 7 daoe1 d/a conversion is disabled in channels 0 and 1 d/a conversion is enabled in channel 0 d/a conversion is disabled in channel 1 d/a conversion is disabled in channel 0 d/a conversion is enabled in channel 1 description d/a conversion is enabled in channels 0 and 1 d/a conversion is enabled in channels 0 and 1 d/a conversion is enabled in channels 0 and 1 bit 6 bit 5 daoe0 dae 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 d/a output enable 0 0 da 0 analo g output is disabled 1 channel-0 d/a conversion and da 0 analo g output are enabled d/a output enable 1 0 da 1 analo g output is disabled 1 channel-1 d/a conversion and da 1 analo g output are enabled ? ? appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 700 of 764 rej09b0396-0500 tpmr ? tpc output mode register h'fffa0 tpc bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 0 r/w 3 g3nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w 0 g0nov group 0 non-overlap 0 normal tpc output in group 0. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 0, controlled by compare match a and b in the selected 16-bit timer channel group 1 non-overlap 0 normal tpc output in group 1. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 1, controlled by compare match a and b in the selected 16-bit timer channel group 2 non-overlap 0 normal tpc output in group 2. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 2, controlled by compare match a and b in the selected 16-bit timer channel group 3 non-overlap 0 normal tpc output in group 3. output values change at compare match a in the selected 16-bit timer channel 1 non-overlapping tpc output in group 3, controlled by compare match a and b in the selected 16-bit timer channel appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 701 of 764 rej09b0396-0500 tpcr ? tpc output control register h'fffa1 tpc group 0 compare match select 1 and 0 bit 1 g0cms1 16-bit timer channel selected as output trigger bit 0 g0cms0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 0 (tp 3 to tp 0 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 1 compare match select 1 and 0 bit 3 g1cms1 16-bit timer channel selected as output trigger bit 2 g1cms0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 1 (tp 7 to tp 4 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 2 compare match select 1 and 0 bit 5 g2cms1 16-bit timer channel selected as output trigger bit 4 g2cms0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 2 (tp 11 to tp 8 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 group 3 compare match select 1 and 0 bit 7 g3cms1 16-bit timer channel selected as output trigger bit 6 g3cms0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 0 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 1 tpc output group 3 (tp 15 to tp 12 ) is triggered by compare match in 16-bit timer channel 2 0 1 0 1 0 1 bit initial value read/write 7 g3cms1 6 g3cms0 5 g2cms1 4 g2cms0 1 r/w 3 g1cms1 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w 0 g0cms0 1 r/w 1 r/w 1 r/w 1 r/w appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 702 of 764 rej09b0396-0500 nderb ? next data enable register b h'fffa2 tpc bit initial value read/write 0 r/w 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w 0 nder8 next data enable 15 to 8 bits 7 to 0 nder15 to nder8 description tpc outputs tp 15 to tp 8 are disabled (ndr15 to ndr8 are not transferred to pb 7 to pb 0 ) tpc outputs tp 15 to tp 8 are enabled (ndr15 to ndr8 are transferred to pb 7 to pb 0 ) 0 1 ndera ? next data enable register a h'fffa3 tpc bit initial value read/write 0 r/w 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w 0 nder0 next data enable 7 to 0 bits 7 to 0 nder7 to nder0 description tpc outputs tp 7 to tp 0 are disabled (ndr7 to ndr0 are not transferred to pa 7 to pa 0 ) tpc outputs tp 7 to tp 0 are enabled (ndr7 to ndr0 are transferred to pa 7 to pa 0 ) 0 1 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 703 of 764 rej09b0396-0500 ndrb ? next data register b h'fffa4/h'fffa6 tpc ? same trigger for tpc output groups 2 and 3 ? address h'fffa4 bit initial value read/write 0 r/w 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w 0 ndr8 store the next output data for tpc output g roup 3 store the next output data for tpc output g roup 2 ? address h'fffa6 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? bit initial value read/write ? different triggers for tpc output groups 2 and 3 ? address h'fffa4 bit initial value read/write 0 r/w 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? store the next output data for tpc output g roup 3 ? address h'fffa6 bit initial value read/write 0 r/w 7 ? 1 ? 0 r/w 6 ? 1 ? 0 r/w 5 ? 1 ? 0 r/w 4 ? 1 ? 3 ndr11 2 ndr10 1 ndr9 0 ndr8 store the next output data for tpc output g roup 2 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 704 of 764 rej09b0396-0500 ndra ? next data register a h'fffa5/h'fffa7 tpc ? same trigger for tpc output groups 0 and 1 ? address h'fffa5 bit initial value read/write 0 r/w 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w 0 ndr0 store the next output data for tpc output g roup 1 store the next output data for tpc output g roup 0 ? address h'fffa7 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? bit initial value read/write ? different triggers for tpc output groups 0 and 1 ? address h'fffa5 bit initial value read/write 0 r/w 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 1 ? store the next output data for tpc output g roup 1 ? address h'fffa7 bit initial value read/write 0 r/w 7 ? 1 ? 0 r/w 6 ? 1 ? 0 r/w 5 ? 1 ? 0 r/w 4 ? 1 ? 3 ndr3 2 ndr2 1 ndr1 0 ndr0 store the next output data for tpc output g roup 0 appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 705 of 764 rej09b0396-0500 smr ? serial mode register h'fffb0 sci0 bit initial value read/write 0 r/w 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 4 o/ e 0 r/w 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 clock select 1 and 0 0 bit 0 clock /4 clock /16 clock /64 clock 1 0 cks0 0 r/w multiprocessor mode 0 multiprocessor function disabled multiprocessor function selected 1 bit 1 clock source cks0 cks1 0 1 0 1 stop bit len g th 0 one stop bit two stop bits 1 parity mode 0 even parity odd parity 1 parity enable 0 parity bit is not added or checked parity bit is added and checked 1 gsm mode (for smart card interface) 0 tend fla g is set 12.5 etu * after start bit tend fla g is set 11.0 etu * after start bit 1 character len g th 0 8-bit data 7-bit data 1 communication mode (for serial communication interface) 0 asynchronous mode synchronous mode 1 note: * etu: elementary time unit (time required to transmit one bit) appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 706 of 764 rej09b0396-0500 brr ? bit rate register h'fffb1 sci0 bit initial value read/write 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 serial communication bit rate settin g appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 707 of 764 rej09b0396-0500 scr ? serial control register h'fffb2 sci0 bit initial value read/write 0 r/w 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 clock enable 1 and 0 (for serial communication interface) bit 1 cke1 bit 0 cke0 asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode synchronous mode asynchronous mode synchronous mode 0 1 0 1 0 1 description transmit-end interrupt enable 0 1 transmit-end interrupt requests (tei) are disabled transmit-end interrupt requests (tei) are enabled receive interrupt enable 0 1 receive-data-full (rxi) and receive-error (eri) interrupt requests are disabled receive-data-full (rxi) and receive-error (eri) interrupt requests are enabled internal clock, sck pin available for g eneric i/o internal clock, sck pin used for serial clock output internal clock, sck pin used for clock output internal clock, sck pin used for serial clock output external clock, sck pin used for clock input external clock, sck pin used for serial clock input external clock, sck pin used for clock input external clock, sck pin used for serial clock input multiprocessor interrupt enable 0 1 multiprocessor interrupts are disabled (normal receive operation) multiprocessor interrupts are enabled receive enable 0 1 receivin g is disabled receivin g is enabled transmit enable 0 1 transmittin g is disabled transmittin g is enabled transmit interrupt enable 0 1 transmit-data-empty interrupt request (txi) is disabled transmit-data-empty interrupt request (txi) is enabled clock enable 1 and 0 (for smart card interface) smr gm bit 1 cke1 bit 0 cke0 0 0 1 0 1 0 1 0 1 0 1 description sck pin available for g eneric i/o sck pin used for clock output sck pin output fixed low sck pin used for clock output sck pin output fixed hi g h sck pin used for clock output appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 708 of 764 rej09b0396-0500 tdr ? transmit data register h'fffb3 sci0 bit initial value read/write 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 serial transmit data appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 709 of 764 rej09b0396-0500 ssr ? serial status register h'fffb4 sci0 bit initial value read/write 1 r/(w) * 7 tdre 0 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer/ers 0 r/(w) * 3 per 1 r 2 tend 0 r 1 mpb 0 r/w 0 mpbt transmit end (for serial communication interface) 0 multiprocessor bit transfer 0 1 multiprocessor bit value in transmit data is 0 multiprocessor bit value in transmit data is 1 multiprocessor bit 0 1 multiprocessor bit value in receive data is 0 multiprocessor bit value in receive data is 1 [clearing conditions] ? read tdre when tdre = 1, then write 0 in tdre. ? the dmac writes data in tdr. [setting conditions] ? reset or transition to standby mode ? te is cleared to 0 in scr. ? tdre is 1 when last bit of 1-byte serial character is transmitted. parity error 0 1 [clearing conditions] ? reset or transition to standby mode ? read per when per = 1, then write 0 in per. [setting condition] parity error (parity of receive data does not match parity setting of o/ e bit in smr) framing error (for serial communication interface) 0 [clearing conditions] ? reset or transition to standby mode ? read fer when fer = 1, then write 0 in fer. [setting condition] framing error (stop bit is 0) error signal status (for smart card interface) 0 [clearing conditions] ? reset or transition to standby mode ? read ers when ers = 1, then write 0 in ers. [setting condition] a low error signal is received. 1 1 overrun error 0 [clearing conditions] ? reset or transition to standby mode ? read orer when orer = 1, then write 0 in orer. [setting condition] overrun error (reception of the next serial data ends when rdrf = 1) 1 receive data register full 0 [clearing conditions] ? reset or transition to standby mode ? read rdrf when rdrf = 1, then write 0 in rdrf. ? the dmac reads data from rdr. [setting condition] serial data is received normally and transferred from rsr to rdr. 1 transmit data register empty note: * only 0 can be written, to clear the flag. 0 [clearing conditions] ? read tdre when tdre = 1, then write 0 in tdre. ? the dmac writes data in tdr. [setting conditions] ? reset or transition to standby mode ? te is 0 in scr. ? data is transferred from tdr to tsr, enabling new data to be written in tdr 1 1 transmit end (for smart card interface) 0 [clearing conditions] ? read tdre when tdre = 1, then write 0 in tdre. ? the dmac writes data in tdr. [setting conditions] ? reset or transition to standby mode ? te is cleared to 0 in scr and fer/ers is cleared to 0. ? tdre is 1 and fer/ers is 0 (normal transmission) 2.5 etu * (when gm = 0) or 1.0 etu (when gm = 1) after 1-byte serial character is transmitted. 1 note: * etu: elementary time unit (time required to transmit one bit) appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 710 of 764 rej09b0396-0500 rdr ? receive data register h'fffb5 sci0 bit initial value read/write 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 serial receive data scmr ? smart card mode register h'fffb6 sci0 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 0 r/w 3 sdir 0 r/w 2 sinv 1 ? 1 ? 0 r/w 0 smif smart card interface mode select 0 1 smart card interface function is disabled (initial value) smart card interface function is enabled smart card data invert 0 1 unmodified tdr contents are transmitted (initial value) receive data is stored unmodified in rdr inverted tdr contents are transmitted received data are inverted before stora g e in rdr smart card data transfer direction 0 1 tdr contents are transmitted lsb-first (initial value) receive data is stored lsb-first in rdr tdr contents are transmitted msb-first receive data is stored msb-first in rdr bit initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 711 of 764 rej09b0396-0500 smr ? serial mode register h'fffb8 sci1 0 r/w 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 note: bit functions are the same as for sci0. bit initial value read/write brr ? bit rate register h'fffb9 sci1 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 note: bit functions are the same as for sci0. bit initial value read/write scr ? serial control register h'fffba sci1 0 r/w 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 note: bit functions are the same as for sci0. bit initial value read/write tdr ? transmit data register h'fffbb sci1 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 bit initial value read/write note: bit functions are the same as for sci0. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 712 of 764 rej09b0396-0500 ssr ? serial status register h'fffbc sci1 0 r/(w) * 7 tdre 0 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer/ers 0 r/(w) * 3 per 1 r 2 tend 0 r 1 mpb 0 r/w 0 mpbt bit initial value read/write notes: bit functions are the same as for sci0. * only 0 can be written, to clear the fla g . rdr ? receive data register h'fffbd sci1 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 bit initial value read/write note: bit functions are the same as for sci0. scmr ? smart card mode register h'fffbe sci1 0 r/w 7 ? 1 ? 0 r/w 6 ? 1 ? 5 ? 1 ? 0 r/w 4 ? 1 ? 3 sdir 2 sinv 1 ? 1 ? 0 smif bit initial value read/write note: bit functions are the same as for sci0. smr ? serial mode register h'fffc0 sci2 0 r/w 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 bit initial value read/write note: bit functions are the same as for sci0. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 713 of 764 rej09b0396-0500 brr ? bit rate register h'fffc1 sci2 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 bit initial value read/write note: bit functions are the same as for sci0. scr ? serial control register h'fffc2 sci2 0 r/w 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 bit initial value read/write note: bit functions are the same as for sci0. tdr ? transmit data register h'fffc3 sci2 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 bit initial value read/write note: bit functions are the same as for sci0. ssr ? serial status register h'fffc4 sci2 1 r/(w) * 7 tdre 0 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer/ers 0 r/(w) * 3 per 1 r 2 tend 0 r 1 mpb 0 r/w 0 mpbt bit initial value read/write notes: bit functions are the same as for sci0. * only 0 can be written, to clear the flag. appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 714 of 764 rej09b0396-0500 rdr ? receive data register h'fffc5 sci2 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 bit initial value read/write note: bit functions are the same as for sci0. scmr ? smart card mode register h'fffc6 sci2 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 2 sinv 0 r/w 1 ? 1 ? 0 smif 0 r/w bit initial value read/write note: bit functions are the same as for sci0. p4dr ? port 4 data register h'fffd3 port 4 7 p4 7 0 r/w 6 p4 6 0 r/w 5 p4 5 0 r/w 4 p4 4 0 r/w 3 p4 3 0 r/w 2 p4 2 0 r/w 1 p4 1 0 r/w 0 p4 0 0 r/w data for port 4 pins bit initial value read/write p6dr ? port 6 data register h'fffd5 port 6 * r 7 p6 7 0 r/w 6 p6 6 0 r/w 5 p6 5 0 r/w 4 p6 4 0 r/w 3 p6 3 0 r/w 2 p6 2 0 r/w 1 p6 1 0 r/w 0 p6 0 data for port 6 pins bit note: * determined by pin p6 7 . initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 715 of 764 rej09b0396-0500 p7dr ? port 7 data register h'fffd6 port 7 7 p7 7 ? * r 6 p7 6 ? * r 5 p7 5 ? * r 4 p7 4 ? * r 3 p7 3 ? * r 2 p7 2 ? * r 1 p7 1 ? * r 0 p7 0 ? * r data for port 7 pins note: * determined by pins p7 7 to p7 0 . bit initial value read/write p8dr ? port 8 data register h'fffd7 port 8 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 0 r/w 4 p8 4 0 r/w 3 p8 3 0 r/w 2 p8 2 0 r/w 1 p8 1 0 r/w 0 p8 0 data for port 8 pins bit initial value read/write p9dr ? port 9 data register h'fffd8 port 9 7 ? 1 ? 6 ? 1 ? 0 r/w 5 p9 5 0 r/w 4 p9 4 0 r/w 3 p9 3 0 r/w 2 p9 2 0 r/w 1 p9 1 0 r/w 0 p9 0 data for port 9 pins bit initial value read/write padr ? port a data register h'fffd9 port a 0 r/w 7 pa 7 0 r/w 6 pa 6 0 r/w 5 pa 5 0 r/w 4 pa 4 0 r/w 3 pa 3 0 r/w 2 pa 2 0 r/w 1 pa 1 0 r/w 0 pa 0 data for port a pins bit initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 716 of 764 rej09b0396-0500 pbdr ? port b data register h'fffda port b 0 r/w 7 pb 7 0 r/w 6 pb 6 0 r/w 5 pb 5 0 r/w 4 pb 4 0 r/w 3 pb 3 0 r/w 2 pb 2 0 r/w 1 pb 1 0 r/w 0 pb 0 data for port b pins bit initial value read/write addra h/l ? a/d data register a h/ l h'fffe0, h'fffe1 a/d 0 r 15 ad9 a/d c onversion data 10-bit data g ivin g an a/d conversion result 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrah addral bit initial value read/write addrb h/l ? a/d data register b h/ l h'fffe2, h'fffe3 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrbh addrbl a/d c onversion data 10-bit data g ivin g an a/d conversion result bit initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 717 of 764 rej09b0396-0500 addrc h/l ? a/d data register c h/ l h'fffe4, h'fffe5 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrch addrcl a/d c onversion data 10-bit data g ivin g an a/d conversion result bit initial value read/write addrd h/l ? a/d data register d h/ l h'fffe6, h'fffe7 a/d 0 r 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? addrdh addrdl a/d c onversion data 10-bit data g ivin g an a/d conversion result bit initial value read/write adcr ? a/d control register h'fffe9 a/d 0 r/w 7 trge 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 2 ? 1 ? 1 ? 1 ? 0 ? 0 r/w tri gg er enable 0 1 a/d conversion start by external tri gg er or 8-bit timer compare match is disabled a/d conversion is started by fallin g ed g e of external tri gg er si g nal ( adtrg ) or 8-bit timer compare match bit initial value read/write appendix b internal i/o registers rev.5.00 sep. 12, 2007 page 718 of 764 rej09b0396-0500 adcsr ? a/d control/status register h'fffe8 a/d 0 r/(w) * 7 adf 0 r/w 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w 0 ch0 channel select group selection 0 1 0 1 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 0 ch2 1 0 1 0 1 0 1 0 1 description single mode scan mode clock select 0 1 conversion time = 134 states (maximum) conversion time = 70 states (maximum) channel selection ch1 ch0 an 0 an 0, an 1 an 0 to an 2 an 0 to an 3 an 4 an 4, an 5 an 4 to an 6 an 4 to an 7 scan mode 0 1 single mode scan mode a/d start 0 1 a/d conversion is stopped 1. single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends 2. scan mode: a/d conversion starts and continues, cycling among the selected channels adst is cleared to 0 by software, by a reset, or by a transition to standby mode a/d interrupt enable 0 1 a/d end interrupt request is disabled a/d end interrupt request is enabled a/d end flag 0 [clearing conditions] ? read adf when adf = 1, then write 0 in adf ? the dmac is activated by an adi interrupt [setting conditions] ? single mode: a/d conversion ends ? scan mode: a/d conversion ends in all selected channels 1 note: * only 0 can be written, to clear the flag. bit initial value read/write appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 719 of 764 rej09b0396-0500 appendix c i/o port block diagrams c.1 port 4 block diagram p4 n rp4p rp4 wp4 wp4d wp4p reset reset reset qd r c p4 pcr n qd r c p4 ddr n qd r c p4 dr n le g end: wp4p: rp4p: wp4d: wp4: rp4: write to p4pcr read p4pcr write to p4ddr write to port 4 read port 4 write to external address read external address internal data bus (upper) internal data bus (lower) 8-bit bus mode 16-bit bus mode note: n = 0 to 7 figure c.1 port 4 block diagram appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 720 of 764 rej09b0396-0500 c.2 port 6 block diagrams le g end: wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 rp6 input wp6d reset qd r c p6 ddr 0 wp6 reset qd r c p6 dr 0 p6 0 internal data bus bus controller wait input enable bus controller wait figure c.2 (a) port 6 block diagram (pin p6 0 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 721 of 764 rej09b0396-0500 p6 1 le g end: wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 wp6d reset qd r c p6 ddr 1 wp6 reset qd r c p6 dr 1 rp6 internal data bus bus controller bus release enable breq input figure c.2 (b) port 6 block diagram (pin p6 1 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 722 of 764 rej09b0396-0500 wp6d reset qd r c p6 ddr 2 wp6 reset qd r c p6 dr 2 rp6 p6 2 le g end: wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 internal data bus bus controller bus release enable back output figure c.2 (c) port 6 block diagram (pin p6 2 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 723 of 764 rej09b0396-0500 read port 6 le g end: rp6: hardware standby rp6 p6 7 output output enable internal data bus figure c.2 (d) port 6 block diagram (pin p6 7 ) c.3 port 7 block diagrams p7 n rp7 le g end: rp7: read port 7 note: n = 0 to 5 internal data bus a/d converter input enable channel select si g nal analo g input figure c.3 (a) port 7 block diagram (pins p7 0 to p7 5 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 724 of 764 rej09b0396-0500 p7 n rp7 le g end: rp7: read port 7 note: n = 6 and 7 internal data bus d/a converter analo g output output enable a/d converter input enable channel select si g nal analo g input figure c.3 (b) port 7 block diagram (pins p7 6 and p7 7 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 725 of 764 rej09b0396-0500 c.4 port 8 block diagrams p8 0 ddr c qd wp8d rp8 p8 0 internal data bus wp8 r reset reset refresh controller output enable interrupt controller rfsh output irq 0 input p8 0 dr c qd r le g end: wp8d: wp8: rp8: write to p8ddr write to port 8 read port 8 figure c.4 (a) port 8 block diagram (pin p8 0 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 726 of 764 rej09b0396-0500 p8 n ddr c qd wp8d p8 n dr c qd wp8 r r reset internal data bus rp8 p8 n bus controller cs 2 cs 3 output reset ssoe software standby interrupt controller irq 1 irq 2 input write to p8ddr write to port 8 read port 8 software standby output port enable le g end: wp8d: wp8: rp8: ssoe: note: n = 1 and 2 figure c.4 (b) port 8 block diagram (pins p8 1 , p8 2 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 727 of 764 rej09b0396-0500 a/d converter wp8d p8 3 dr c qd wp8 r reset internal data bus rp8 p8 3 bus controller cs 1 output reset interrupt controller irq 3 input adtrg input ssoe software standby p8 3 ddr c qd r write to p8ddr write to port 8 read port 8 software standby output port enable le g end: wp8d: wp8: rp8: ssoe: figure c.4 (c) port 8 block diagram (pin p8 3 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 728 of 764 rej09b0396-0500 ssoe software standby r p8 4 ddr c qd wp8d wp8 rp8 r p8 4 dr c qd p8 4 internal data bus bus controller cs 0 output reset reset write to p8ddr write to port 8 read port 8 software standby output port enable le g end: wp8d: wp8: rp8: ssoe: figure c.4 (d) port 8 block diagram (pin p8 4 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 729 of 764 rej09b0396-0500 c.5 port 9 block diagrams le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 0 rp9 wp9d reset qd r c p9 ddr 0 wp9 reset qd r c p9 dr 0 internal data bus sci output enable serial transmit data guard time figure c.5 (a) port 9 block diagram (pin p9 0 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 730 of 764 rej09b0396-0500 p9 1 ddr c qd wp9d rp9 p9 1 write to p9ddr write to port 9 read port 9 le g end: wp9d: wp9: rp9: wp9 r reset internal data bus reset sci output enable serial transmit data guard time p9 1 dr c qd r figure c.5 (b) port 9 block diagram (pin p9 1 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 731 of 764 rej09b0396-0500 le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 p9 2 wp9d reset qd r c p9 ddr 2 wp9 reset qd r c p9 dr 2 rp9 internal data bus input enable serial receive data sci figure c.5 (c) port 9 block diagram (pin p9 2 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 732 of 764 rej09b0396-0500 p9 3 ddr c qd wp9d rp9 p9 3 dr c qd p9 3 serial receive data input enable write to p9ddr write to port 9 read port 9 le g end: wp9d: wp9: rp9: wp9 r r reset internal data bus reset sci figure c.5 (d) port 9 block diagram (pin p9 3 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 733 of 764 rej09b0396-0500 le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 wp9d reset qd r c p9 ddr 4 wp9 reset qd r c p9 dr 4 rp9 p9 4 internal data bus sci clock input enable clock output enable clock output clock input interrupt controller inputirq 4 figure c.5 (e) port 9 block diagram (pin p9 4 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 734 of 764 rej09b0396-0500 le g end: wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 wp9d reset qd r c p9 ddr 5 wp9 reset qd r c p9 dr 5 rp9 p9 5 internal data bus sci clock input enable clock output enable clock output clock input interrupt controller input irq 5 figure c.5 (f) port 9 block diagram (pin p9 5 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 735 of 764 rej09b0396-0500 c.6 port a block diagrams le g end: wpad: wpa: rpa: write to paddr write to port a read port a pa n wpad reset qd r c pa ddr n reset qd r c pa dr n rpa wpa internal data bus tpc output enable tpc next data output tri gg er output enable transfer end output dma controller counter clock input 16-bit timer counter clock input 8-bit timer note: n = 0 and 1 figure c.6 (a) port a block diagram (pins pa 0 , pa 1 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 736 of 764 rej09b0396-0500 le g end: wpad: wpa: rpa: write to paddr write to port a read port a pa n rpa wpa wpad reset qd r c pa ddr n reset qd r c pa dr n internal data bus tpc output enable tpc next data output tri gg er output enable compare match output input capture counter clock input 16-bit timer counter clock input 8-bit timer note: n = 2 and 3 figure c.6 (b) port a block diagram (pins pa 2 , pa 3 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 737 of 764 rej09b0396-0500 le g end: wpad: wpa: rpa: ssoe: write to paddr write to port a read port a software standby output port enable pa n wpad reset pra wpa qd r c pa n ddr reset qd r c pa n dr internal address bus internal data bus tpc 16-bit timer tpc output enable next data output tri gg er output enable compare match output input capture software standby ssoe bus released mode 3/4 address output enable notes: 1. n = 4 to 7 2. pa 7 address output enable is fixed at 1 in modes 3 and 4. figure c.6 (c) port a block diagram (pins pa 4 to pa 7 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 738 of 764 rej09b0396-0500 c.7 port b block diagrams r pb n ddr c qd reset wpbd wpb rpb r pb n dr c qd reset bus released pb n internal data bus tpc 8-bit timer tpc output enable bus controller cs output enable cs7 cs5 output next data output tri gg er output enable compare match output software standby ssoe le g end: wpbd: wpb: rpb: ssoe: write to pbddr write to port b read port b software standby output port enable note: n = 0 and 2 figure c.7 (a) port b block diagram (pins pb 0 , pb 2 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 739 of 764 rej09b0396-0500 r pb n ddr c qd reset wpbd wpb rpb r pb n dr c qd reset pb n internal data bus tpc 8-bit timer tpc output enable bus controller cs output enable cs6 cs4 output next data output tri gg er output enable compare match output dmac dreq0 dreq1 input tmo2 tmo3 input bus released software standby ssoe write to pbddr write to port b read port b software standby output port enable le g end: wpbd: wpb: rpb: ssoe: note: n = 1 and 3 figure c.7 (b) port b block diagram (pins pb 1 , pb 3 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 740 of 764 rej09b0396-0500 pb 4 le g end: wpbd: wpb: rpb: write to pbddr write to port b read port b wpb rpb reset qd r c pb ddr 4 wpbd reset qd r c pb dr 4 internal data bus tpc output enable next data output tri gg er cas output enable cas output tpc bus controller figure c.7 (c) port b block diagram (pin pb 4 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 741 of 764 rej09b0396-0500 r pb 5 ddr c qd reset wpbd wpb rpb r pb 5 dr c qd reset pb 5 internal data bus tpc sci tpc output enable sci next data output tri gg er clock output enable clock input enable clock output clock input bus controller cas output enable cas output write to pbddr write to port b read port b le g end: wpbd: wpb: rpb: figure c.7 (d) port b block diagram (pin pb 5 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 742 of 764 rej09b0396-0500 wpbd reset reset qd r c pb ddr qd r c pb dr 6 rpb wpb tpc sci le g end: wpbd: wpb: rpb: write to pbddr write to port b read port b tpc output enable next data output tri gg er output enable serial transmit data guard time internal data bus 6 pb 6 figure c.7 (e) port b block diagram (pin pb 6 ) appendix c i/o port block diagrams rev.5.00 sep. 12, 2007 page 743 of 764 rej09b0396-0500 pb 7 wpbd reset reset qd r c pb ddr qd r c pb dr 7 rpb wpb sci tpc sci le g end: wpbd: wpb: rpb: write to pbddr write to port b read port b tpc output enable next data input enable output tri gg er internal data bus 7 serial receive data figure c.7 (f) port b block diagram (pin pb 7 ) appendix d pin states rev.5.00 sep. 12, 2007 page 744 of 764 rej09b0396-0500 appendix d pin states d.1 port states in each mode table d.1 port states in each processing state port name pin name mode reset hardware standby mode software standby mode bus-released state program execution state reso ? t * 1 t t t * 1 t * 1 a 19 to a 0 1 to 4 l t [ssoe = 0] t [ssoe = 1] keep t a 19 to a 0 d 15 to d 8 1 to 4 t t t t d 15 to d 8 as , rd , hwr , lwr 1 to 4 h t [ssoe = 0] t [ssoe = 1] h t as , rd , hwr , lwr p4 7 to p4 0 1, 3 t t keep keep i/o port 2, 4 t t t t d 7 to d 0 p6 0 1 to 4 t t keep keep i/o port wait p6 1 1 to 4 t t [brle = 0] keep [brle = 1] t t i/o port breq p6 2 1 to 4 t t [brle = 0] keep [brle = 1] h l [brle = 0] i/o port [brle = 1] back p6 7 1 to 4 clock output t [pstop = 0] h [pstop = 1] keep [pstop = 0] [pstop = 1] keep [pstop = 0] [pstop = 1] input port p7 7 to p7 0 1 to 4 t t t t input port appendix d pin states rev.5.00 sep. 12, 2007 page 745 of 764 rej09b0396-0500 port name pin name mode reset hardware standby mode software standby mode bus-released state program execution state p8 0 1 to 4 t t ? when dram space is not selected * 2 [rfshe = 0] keep [rfshe = 1] illegal setting ? when dram space is selected * 3 [rfshe = 0] keep [rfshe = 1, srfmd = 0, ssoe = 0] t [rfshe = 1, srfmd = 0, ssoe = 1] h [rfshe = 1, srfmd = 1] rfsh ? when dram space is not selected * 2 [rfshe = 0] keep [rfshe = 1] illegal setting ? when dram space is selected * 3 [rfshe = 0] keep [rfshe = 1] t [rfshe = 0] i/o port [rfshe = 1] rfsh p8 1 1 to 4 t t ? ras 3 output * 4 [ssoe = 0] t [ssoe = 1] h ? otherwise * 5 [ddr = 0] t [ddr = 1, ssoe = 0] t [ddr = 1, ssoe = 1] h ? ras 3 output * 4 t ? otherwise * 5 [ddr = 0] keep [ddr = 1] t ? ras 3 output ras 3 ? otherwise [ddr = 0] input port [ ddr = 1] cs 3 appendix d pin states rev.5.00 sep. 12, 2007 page 746 of 764 rej09b0396-0500 port name pin name mode reset hardware standby mode software standby mode bus-released state program execution state p8 2 1 to 4 t t ? ras 2 output * 3 [ssoe = 0] t [ssoe = 1] h ? otherwise * 2 [ddr = 0] t [ddr = 1, ssoe = 0] t [ddr = 1, ssoe = 1] h ? ras 2 output * 3 t ? otherwise * 2 [ddr = 0] keep [ddr = 1] t ? ras 2 output ras 2 ? otherwise [ddr = 0] input port [ddr = 1] cs 2 p8 3 1 to 4 t t [ddr = 0] t [ddr = 1, ssoe = 0] t [ddr = 1, ssoe = 1] h [ddr = 0] keep [ddr = 1] t [ddr = 0] input port [ddr = 1] cs 1 p8 4 1 to 4 h t [ddr = 0] t [ddr = 1, ssoe = 0] t [ddr = 1, ssoe = 1] h [ddr = 0] keep [ddr = 1] t [ddr = 0] input port [ddr = 1] cs 0 p9 5 to p9 0 1 to 4 t t keep keep i/o port pa 3 to pa 0 1 to 4 t t keep keep i/o port pa 6 to pa 4 1, 2 t t keep keep i/o port 3, 4 t t ? address output * 6 [ssoe = 0] t [ssoe = 1] keep ? otherwise * 7 keep ? address output * 6 t ? otherwise * 7 keep ? address output a 23 to a 21 ? otherwise ? i/o port appendix d pin states rev.5.00 sep. 12, 2007 page 747 of 764 rej09b0396-0500 port name pin name mode reset hardware standby mode software standby mode bus-released state program execution state pa 7 1, 2 t t keep keep i/o port 3, 4 l t [ssoe = 0] t [ssoe = 1] keep t a 20 pb 1 , pb 0 1 to 4 t t ? cs output * 8 [ssoe = 0] t [ssoe = 1] h ? otherwise * 9 keep ? cs output * 8 t ? otherwise * 9 keep ? cs output cs 7 , cs 6 ? otherwise i/o port pb 2 1 to 4 t t ? ras 5 output * 10 [ssoe = 0] t [ssoe = 1] h ? cs output * 11 [ssoe = 0] t [ssoe = 1] h ? otherwise * 12 keep ? ras 5 output * 10 t ? cs output * 11 t ? otherwise * 12 keep ? ras 5 output ras 5 ? cs output cs 5 ? otherwise i/o port pb 3 1 to 4 t t ? ras 4 output * 13 [ssoe = 0] t [ssoe = 1] h ? cs output * 14 [ssoe = 0] t [ssoe = 1] h ? otherwise * 15 keep ? ras 4 output * 13 t ? cs output * 14 t ? otherwise * 15 keep ? ras 4 output ras 4 ? cs output cs 4 ? otherwise i/o port appendix d pin states rev.5.00 sep. 12, 2007 page 748 of 764 rej09b0396-0500 port name pin name mode reset hardware standby mode software standby mode bus-released state program execution state pb 5 , pb 4 1 to 4 t t ? cas output * 16 [ssoe = 0] t [ssoe = 1] h ? otherwise * 17 keep ? cas output * 16 t ? otherwise * 17 keep ? cas output ucas , lcas ? otherwise i/o port pb 7 , pb 6 1 to 4 t t keep keep i/o port legend: h: high l: low t: high-impedance state keep: input pins are in the high-impedance state; output pins maintain their previous state. ddr: data direction register notes: 1. low only when wdt overflow causes a reset. 2. when bits dras2, dras1, and dras0 in drcra (dram control register a) are all cleared to 0. 3. when any of bits dras2, dras1, or dras0 in drcra (dram control register a) is set to 1. 4. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is 010, 100, or 101. 5. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is other than 010, 100, or 101. 6. when bit a23e, a22e, or a21e, respectively, in brcr (bus release control register) is cleared to 0. 7 when bit a23e, a22e, or a21e, respectively, in brcr (bus release control register) is set to 1. 8. when bit cs7e or cs6e, respectively, in cscr (chip select control register) is set to 1. 9. when bit cs7e or cs6e, respectively, in cscr (chip select control register) is cleared to 0. 10. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is 101. 11. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is other than 101, and bit cs5e in cscr (chip select control register) is set to 1. 12. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is other than 101, and bit cs5e in cscr (chip select control register) is cleared to 0. appendix d pin states rev.5.00 sep. 12, 2007 page 749 of 764 rej09b0396-0500 13. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is 100, 101, or 110. 14. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is other than 100, 101, or 110, and bit cs4e in cscr (chip select control register) is set to 1. 15. when the setting of bits dras2, dras1, and dras0 in drcra (dram control register a) is other than 100, 101, or 110, and bit cs4e in cscr (chip select control register) is cleared to 0. 16. when any of bits dras2, dras1, or dras0 in drcra (dram control register a) is set to 1, and bit csel in drcrb (dram control register b) is cleared to 0. 17. when any of bits dras2, dras1, or dras0 in drcra (dram control register a) is set to 1, and bit csel in drcrb (dram control register b) is set to 1; or, when bits dras2, dras1, and dras0 are cleared to 0. appendix d pin states rev.5.00 sep. 12, 2007 page 750 of 764 rej09b0396-0500 d.2 pin states at reset modes 1 and 2: figure d.1 is a timing diagram for the case in which res goes low during an external memory access in mode 1 or 2. as soon as res goes low, all ports are initialized to the input state. as , rd , hwr , lwr , and cs 0 go high, and d 15 to d 0 go to the high-impedance state. the address bus is initialized to the low output level 2.5 clock cycles after the low level of res is sampled. clock pin p6 7 / goes to the output state at the next rise of after res goes low. as , rd (read) d 15 to d 0 (write) hwr , lwr (write) internal reset si g nal res p6 7 / i/o port, cs 7 to cs 1 cs 0 a 19 to a 0 t1 t2 t3 access to external memory h'00000 hi g h impedance hi g h impedance figure d.1 reset during memory access (modes 1 and 2) appendix d pin states rev.5.00 sep. 12, 2007 page 751 of 764 rej09b0396-0500 modes 3 and 4: figure d.2 is a timing diagram for the case in which res goes low during an external memory access in mode 3 or 4. as soon as res goes low, all ports are initialized to the input state. as , rd , hwr , lwr , and cs 0 go high, and d 15 to d 0 go to the high-impedance state. the address bus is initialized to the low output level 2.5 clock cycles after the low level of res is sampled. however, when pa 4 to pa 6 are used as address bus pins, or when p8 3 to p8 1 and pb 0 to pb 3 are used as cs output pins, they go to th e high-impedance state at the same time as res goes low. clock pin p6 7 / goes to the output state at the next rise of after res goes low. t1 t2 t3 access to external memory h'000000 hi g h impedance hi g h impedance as , rd (read) d 15 to d 0 (write) hwr , lwr (write) internal reset si g nal res p6 7 / i/o port, pa 4 /a 23 to pa 6 / a 21 , cs 7 to cs 1 cs 0 a 20 to a 0 figure d.2 reset during memory access (modes 3 and 4) appendix e timing of transition to and recovery from hardware standby mode rev.5.00 sep. 12, 2007 page 752 of 764 rej09b0396-0500 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must r emain low until stby goes low (minimum delay from stby low to res high: 0 ns). t 1 10t cyc t 2 0 ns stby res (2) to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. stby res t 100 ns t osc appendix f list of product codes rev.5.00 sep. 12, 2007 page 753 of 764 rej09b0396-0500 appendix f list of product codes table f.1 h8/3007, h8/3006 product code lineup part no. product code mark code package code h8/3007 hd6413007f hd6413007f 100-pin qfp (fp-100b) 5.0 v 10 % (5 v) hd6413007te hd6413007te 100-pin tqfp (tfp-100b) hd6413007fp hd6413007fp 100-pin qfp (fp-100a) hd6413007vf hd6413007vf 100-pin qfp (fp-100b) hd6413007vte hd6413007vte 100-pin tqfp (tfp-100b) 2.7 to 5.5 v (low voltage) hd6413007vfp hd6413007vfp 100-pin qfp (fp-100a) h8/3006 hd6413006f hd6413006f 100-pin qfp (fp-100b) 5.0 v 10 % (5 v) hd6413006te hd6413006te 100-pin tqfp (tfp-100b) hd6413006fp hd6413006fp 100-pin qfp (fp-100a) hd6413006vf hd6413006vf 100-pin qfp (fp-100b) hd6413006vte hd6413006vte 100-pin tqfp (tfp-100b) 2.7 to 5.5 v (low voltage) hd6413006vfp hd6413006vfp 100-pin qfp (fp-100a) appendix g package dimensions rev.5.00 sep. 12, 2007 page 754 of 764 rej09b0396-0500 appendix g package dimensions the package dimention that is shown in the renesas semiconductor package data book has priority. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. * 1 * 2 * 3 p e d e d f 100 125 26 76 75 51 50 xm y z z d h e h b terminal cross section p 1 1 c b c b 2 1 1 detail f c a a l l a 1.0 1.0 0.08 0.10 0.5 8 0 0.25 0.12 0.15 0.20 0.00 0.27 0.22 0.17 0.22 0.17 0.12 3.05 16.3 16.0 15.7 l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l h e 0.7 0.5 0.3 max nom min dimension in millimeters symbol reference 14 2.70 16.3 16.0 15.7 1.0 14 p-qfp100-14x14-0.50 1.2g mass[typ.] fp-100b/fp-100bv prqp0100ka-a renesas code jeita package code previous code figure g.1 package dimensions (fp-100b) appendix g package dimensions rev.5.00 sep. 12, 2007 page 755 of 764 rej09b0396-0500 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 1.00 1.00 0.08 0.10 0.5 8 0 15.8 16.0 16.2 0.15 0.20 1.20 0.20 0.10 0.00 0.27 0.22 0.17 0.22 0.17 0.12 l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l h e 0.6 0.5 0.4 max nom min dimension in millimeters symbol reference 14 1.00 16.2 16.0 15.8 1.0 14 index mark * 1 * 2 * 3 p e d e d 100 1 f xm y 26 25 76 75 50 51 z z h e h d b 2 1 1 detail f c l a a a l terminal cross section p 1 1 b c b c p-tqfp100-14x14-0.50 0.5g mass[typ.] tfp-100b/tfp-100bv ptqp0100ka-a renesas code jeita package code previous code figure g.2 package dimensions (tfp-100b) appendix g package dimensions rev.5.00 sep. 12, 2007 page 756 of 764 rej09b0396-0500 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 0.83 0.58 0.15 0.13 0.65 10 0 19.2 18.8 18.4 3.10 0.12 0.17 0.22 0.24 0.32 0.40 0.00 0.30 0.15 0.20 0.30 20 14 l 1 d z e z d y x c b 1 b p a h d a 2 e a 1 c 1 e e l h e 2.4 24.4 24.8 25.2 2.70 reference symbol dimension in millimeters min nom max 1.0 1.2 1.4 * 1 * 2 * 3 p e d e d 51 50 80 81 30 31 1 100 f ym x z z b h e h d 2 1 1 detail f c l a a a l terminal cross section p 1 1 b c b c p-qfp100-14x20-0.65 1.7g mass[typ.] fp-100a/fp-100av prqp0100je-b renesas code jeita package code previous code figure g.3 package dimensions (fp-100a) appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 757 of 764 rej09b0396-0500 appendix h comparison of h8/300h series product specifications h.1 differences between h8/3067 and h8/3062 group, h8/3048 group, h8/3006 and h8/3007, and h8/3002 item h8/3067, h8/3062 group h8/3048 group h8/3006, h8/3007 h8/3002 1 operating mode mode 5 16 mb rom enabled expanded mode 1 mb rom enabled expanded mode mode 6 64 kb single-chip mode 16 mb rom enabled expanded mode 2 interrupt controller internal interrupt sources 36 (h8/3067) 27 (h8/3062) 30 36 30 3 bus controller burst rom interface yes (h8/3067) no (h8/3062) no yes no idle cycle insertion function yes no yes no wait mode 2 modes 4 modes 2 modes 4 modes wait state numbe r setting per area common to all areas per area common to all areas address output method choice of address update mode (mask rom and flash memory r versions only) fixed fixed fixed 4 dram interface connectable areas area 2/3/4/5 (h8/3067 only) area 3 area 2/3/4/5 area 3 precharge cycle insertion function yes (h8/3067 only) no yes no fast page mode yes (h8/3067 only) no yes no address shift amount 8 bit/9 bit/10 bit (h8/3067 only) 8 bit/9 bit 8 bit/9 bit/10 bit 8 bit/9 bit appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 758 of 764 rej09b0396-0500 item h8/3067, h8/3062 group h8/3048 group h8/3006, h8/3007 h8/3002 5 timer functions 16-bit timers 8-bit timers itu 16-bit timers 8-bit timers itu number of channels 16 bits 3 8 bits 4 (16 bits 2) 16 bits 5 16 bits 3 8 bits 4 (16 bits 2) 16 bits 5 pulse output 6 pins 4 pins (2 pins) 12 pins 6 pins 4 pins (2 pins) 12 pins input capture 6 2 10 6 2 10 external clock 4 systems (selectable) 4 systems (fixed) 4 systems (selectable) 4 systems (selectable) 4 systems (fixed) 4 systems (selectable) internal clock , /2, /4, /8 /8, /64, /8192 , /2, /4, /8 , /2, /4, /8 /8, /64, /8192 , /2, /4, /8 complementary pwm function no no yes no no yes reset- synchronous pwm function no no yes no no yes buffer operation no no yes no no yes output initialization function yes no no yes no no pwm output 3 4 (2) 5 3 4 (2) 5 dmac activation 3 channels (h8/3067 only) no 4 channels 3 channels no 4 channels a/d conversion activation no yes no no yes no interrupt sources 3 sources 3 8 sources 3 sources 5 3 sources 3 8 sources 3 sources 5 6 tpc time base 3 kinds, 16-bit timer base 4 kinds, itu base 3 kinds, 16-bit timer base 4 kinds, itu base 7 wdt reset signal external output function yes (except products with on-chip flash memory) yes yes yes 8 sci number of channels 3 channels (h8/3067) 2 channels (h8/3062) 2 channels 3 channels 2 channels smart card interface supported on all channels supported on sci0 only supported on all channels no appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 759 of 764 rej09b0396-0500 item h8/3067, h8/3062 group h8/3048 group h8/3006, h8/3007 h8/3002 9 a/d converter conversion start trigger input external trigger/8-bit timer compare match external trigger external trigger/8-bit timer compare match external trigger conversion states 70/134 134/266 70/134 134/266 10 pin control pin /input port multiplexing output only /input port multiplexing output only a 20 in 16 mb rom enabled expanded mode a 20 / i/o port multiplexing a 20 output address bus, as , rd , hwr , lwh , cs 7 to cs 0 , rfsh in software standby state high-level output/high- impedance selectable ( rfsh : h8/3067 only) high-level output (except cs 0 ) low-level output ( cs 0 ) high-level output/high- impedance selectable high-level output (except cs 0 ) low-level output ( cs 0 ) cs 7 to cs 0 in bus- released state high-impedance high-level output high-impedance high-level output 11 flash memory functions program/erase voltage 12 v application unnecessary. single-power-supply programming. 12 v application from off-chip block divisions 8 blocks 16 blocks appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 760 of 764 rej09b0396-0500 h.2 comparison of pin function s of 100-pin package products (fp-100b, tfp-100b) table h.1 pin arrangement of each product (fp-100b, tfp-100b) pin on-chip-rom products romless products no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3002 1 vcc vcc vcc vcc vcc vcc 2 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 / tioca3 pb 0 /tp 8 / tioca3 pb 0 /tp 8 /tmo 0 / cs 7 pb 0 /tp 8 / tioca3 3 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 /tmio 1 / cs 6 pb 1 /tp 9 / tiocb3 pb 1 /tp 9 / tiocb3 pb 1 /tp 9 /tmio 1 / dreq 0 / cs 6 pb 1 /tp 9 / tiocb3 4 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 / tioca4 pb 2 /tp 10 / tioca4 pb 2 /tp 10 /tmo 2 / cs 5 pb 2 /tp 10 / tioca4 5 pb 3 /tp 11 / tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 / tmio 3 / cs 4 pb 3 /tp 11 / tiocb4 pb 3 /tp 11 / tioc4 pb 3 /tp 11 / tmio 3 / dreq 1 / cs 4 pb 3 /tp 11 / tiocb4 6 pb 4 /tp 12 / ucas pb 4 /tp 12 pb 4 /tp 12 / tocxa4 pb 4 /tp 12 / tocxa4 pb 4 /tp 12 / ucas pb 4 /tp 12 / tocxa4 7 pb 5 /tp 13 / lcas /sck 2 pb 5 /tp 13 pb 5 /tp 13 / tocxb4 pb 5 /tp 13 / tocxb4 pb 5 /tp 13 / lcas /sck 2 pb 5 /tp 13 / tocxb4 8 pb 6 /tp 14 /txd 2 pb 6 /tp 14 pb 6 /tp 14 / dreq 0 / cs 7 pb 6 /tp 14 / dreq 0 pb 6 /tp 14 /txd 2 pb 6 /tp 14 / dreq 0 9 pb 7 /tp 15 /rxd 2 pb 7 /tp 15 pb 7 /tp 15 / dreq 1 / adtrg pb 7 /tp 15 / dreq 1 / adtrg pb 7 /tp 15 /rxd 2 pb 7 /tp 15 / dreq 1 / adtrg 10 reso /fwe * reso /fwe * reso /v pp * reso reso reso 11 vss vss vss vss vss vss 12 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 p9 0 /txd 0 13 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 p9 1 /txd 1 14 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 p9 2 /rxd 0 15 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 p9 3 /rxd 1 16 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 p9 4 /sck 0 / irq 4 17 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 p9 5 /sck 1 / irq 5 18 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 p4 0 /d 0 19 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 p4 1 /d 1 20 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 p4 2 /d 2 21 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 p4 3 /d 3 22 vss vss vss vss vss vss 23 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 p4 4 /d 4 24 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 p4 5 /d 5 appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 761 of 764 rej09b0396-0500 pin on-chip-rom products romless products no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3002 25 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 p4 6 /d 6 26 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 p4 7 /d 7 27 p3 0 /d 8 p3 0 /d 8 p3 0 /d 8 p3 0 /d 8 d 8 d 8 28 p3 1 /d 9 p3 1 /d 9 p3 1 /d 9 p3 1 /d 9 d 9 d 9 29 p3 2 /d 10 p3 2 /d 10 p3 2 /d 10 p3 2 /d 10 d 10 d 10 30 p3 3 /d 11 p3 3 /d 11 p3 3 /d 11 p3 3 /d 11 d 11 d 11 31 p3 4 /d 12 p3 4 /d 12 p3 4 /d 12 p3 4 /d 12 d 12 d 12 32 p3 5 /d 13 p3 5 /d 13 p3 5 /d 13 p3 5 /d 13 d 13 d 13 33 p3 6 /d 14 p3 6 /d 14 p3 6 /d 14 p3 6 /d 14 d 14 d 14 34 p3 7 /d 15 p3 7 /d 15 p3 7 /d 15 p3 7 /d 15 d 15 d 15 35 vcc vcc vcc vcc vcc vcc 36 p1 0 /a 0 p1 0 /a 0 p1 0 /a 0 p1 0 /a 0 a 0 a 0 37 p1 1 /a 1 p1 1 /a 1 p1 1 /a 1 p1 1 /a 1 a 1 a 1 38 p1 2 /a 2 p1 2 /a 2 p1 2 /a 2 p1 2 /a 2 a 2 a 2 39 p1 3 /a 3 p1 3 /a 3 p1 3 /a 3 p1 3 /a 3 a 3 a 3 40 p1 4 /a 4 p1 4 /a 4 p1 4 /a 4 p1 4 /a 4 a 4 a 4 41 p1 5 /a 5 p1 5 /a 5 p1 5 /a 5 p1 5 /a 5 a 5 a 5 42 p1 6 /a 6 p1 6 /a 6 p1 6 /a 6 p1 6 /a 6 a 6 a 6 43 p1 7 /a 7 p1 7 /a 7 p1 7 /a 7 p1 7 /a 7 a 7 a 7 44 vss vss vss vss vss vss 45 p2 0 /a 8 p2 0 /a 8 p2 0 /a 8 p2 0 /a 8 a 8 a 8 46 p2 1 /a 9 p2 1 /a 9 p2 1 /a 9 p2 1 /a 9 a 9 a 9 47 p2 2 /a 10 p2 2 /a 10 p2 2 /a 10 p2 2 /a 10 a 10 a 10 48 p2 3 /a 11 p2 3 /a 11 p2 3 /a 11 p2 3 /a 11 a 11 a 11 49 p2 4 /a 12 p2 4 /a 12 p2 4 /a 12 p2 4 /a 12 a 12 a 12 50 p2 5 /a 13 p2 5 /a 13 p2 5 /a 13 p2 5 /a 13 a 13 a 13 51 p2 6 /a 14 p2 6 /a 14 p2 6 /a 14 p2 6 /a 14 a 14 a 14 52 p2 7 /a 15 p2 7 /a 15 p2 7 /a 15 p2 7 /a 15 a 15 a 15 53 p5 0 /a 16 p5 0 /a 16 p5 0 /a 16 p5 0 /a 16 a 16 a 16 54 p5 1 /a 17 p5 1 /a 17 p5 1 /a 17 p5 1 /a 17 a 17 a 17 55 p5 2 /a 18 p5 2 /a 18 p5 2 /a 18 p5 2 /a 18 a 18 a 18 56 p5 3 /a 19 p5 3 /a 19 p5 3 /a 19 p5 3 /a 19 a 19 a 19 appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 762 of 764 rej09b0396-0500 pin on-chip-rom products romless products no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3002 57 vss vss vss vss vss vss 58 p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait p6 0 / wait 59 p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq p6 1 / breq 60 p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 / back p6 2 / back 61 p6 7 / p6 7 / p6 7 / 62 stby stby stby stby stby stby 63 res res res res res res 64 nmi nmi nmi nmi nmi nmi 65 vss vss vss vss vss vss 66 extal extal extal extal extal extal 67 xtal xtal xtal xtal xtal xtal 68 vcc vcc vcc vcc vcc vcc 69 p6 3 / as p6 3 / as p6 3 / as p6 3 / as as as 70 p6 4 / rd p6 4 / rd p6 4 / rd p6 4 / rd rd rd 71 p6 5 / hwr p6 5 / hwr p6 5 / hwr p6 5 / hwr hwr hwr 72 p6 6 / lwr p6 6 / lwr p6 6 / lwr p6 6 / lwr lwr lwr 73 md 0 md 0 md 0 md 0 md 0 md 0 74 md 1 md 1 md 1 md 1 md 1 md 1 75 md 2 md 2 md 2 md 2 md 2 md 2 76 avcc avcc avcc avcc avcc avcc 77 v ref v ref v ref v ref v ref v ref 78 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 p7 0 /an 0 79 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 p7 1 /an 1 80 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 p7 2 /an 2 81 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 p7 3 /an 3 82 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 p7 4 /an 4 83 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 p7 5 /an 5 84 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 /da 0 p7 6 /an 6 85 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 /da 1 p7 7 /an 7 86 avss avss avss avss avss avss 87 p8 0 / rfsh / irq 0 p8 0 / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 p8 0 / rfsh / irq 0 88 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 p8 1 / cs 3 / irq 1 appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 763 of 764 rej09b0396-0500 pin on-chip-rom products romless products no. h8/3067 group h8/3062 group h8/3048 group h8/3042 group h8/3006, h8/3007 h8/3002 89 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 p8 2 / cs 2 / irq 2 90 p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 p8 3 / cs 1 / irq 3 p8 3 / cs 1 / irq 3 / adtrg p8 3 / cs 1 / irq 3 91 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 p8 4 / cs 0 92 vss vss vss vss vss vss 93 pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka pa 0 /tp 0 / tend 0 /tclka 94 pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb pa 1 /tp 1 / tend 1 /tclkb 95 pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc pa 2 /tp 2 / tioca 0 /tclkc 96 pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd pa 3 /tp 3 / tiocb 0 /tclkd 97 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 / cs 6 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 pa 4 /tp 4 / tioca 1 /a 23 98 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 / cs 5 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 pa 5 /tp 5 / tiocb 1 /a 22 99 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 / cs 4 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 pa 6 /tp 6 / tioca 2 /a 21 100 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 pa 7 /tp 7 / tiocb 2 /a 20 note: * functions as reso in the mask rom versions, and as fwe in the flash memory and flash memory r versions. appendix h comparison of h8/300h series product specifications rev.5.00 sep. 12, 2007 page 764 of 764 rej09b0396-0500 renesas 16-bit single-chip microcomputer hardware manual h8/3006, h8/3007 publication date: 1st edition, december 1997 rev.5.00, september 12, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0 h8/3006, h8/3007 rej09b0396-0500 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan |
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